boards: arm: nucleo_f756zg: Created new board and soc definition

Added board definitions for nucleo_f756zg. Features include gpio,
pinmux, uart (ST Zio, ST-Link and Arduino Uno v3 interfaces).

Added basic documentation and some soc definitions for the
stm32 f756XX soc.

Signed-off-by: AJ Palmer <ajpcode@hotmail.com>

boards/arm/nucleo_f756zg/CMakeLists.txt

@@ -0,0 +1,3 @@
+zephyr_library()
+zephyr_library_sources(pinmux.c)
+zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)

boards/arm/nucleo_f756zg/Kconfig.board

@@ -0,0 +1,10 @@
+# Kconfig - STM32F756ZG Nucleo board configuration
+#
+# Copyright (c) 2018 AJ Palmer
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_NUCLEO_F756ZG
+	bool "Nucleo F756ZG Development Board"
+	depends on SOC_STM32F756XX

boards/arm/nucleo_f756zg/Kconfig.defconfig

@@ -0,0 +1,30 @@
+# Kconfig - STM32F756ZG Nucleo board configuration
+#
+# Copyright (c) 2018 AJ Palmer
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_NUCLEO_F756ZG
+
+config BOARD
+	default "nucleo_f756zg"
+
+if UART_CONSOLE
+
+config UART_3
+	default y
+
+endif # UART_CONSOLE
+
+if SERIAL
+
+config UART_2
+	default y
+
+config UART_6
+	default y
+
+endif # SERIAL
+
+endif # BOARD_NUCLEO_F756ZG

boards/arm/nucleo_f756zg/board.cmake

@@ -0,0 +1 @@
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/arm/nucleo_f756zg/doc/nucleof756zg.rst

@@ -0,0 +1,202 @@
+.. _nucleo_f756zg_board:
+
+ST Nucleo F756ZG
+################
+
+Overview
+********
+
+The STM32 Nucleo-144 boards offer combinations of performance and power that
+provide an affordable and flexible way for users to build prototypes and try
+out new concepts. For compatible boards, the SMPS significantly reduces power
+consumption in Run mode.
+
+The Arduino-compatible ST Zio connector expands functionality of the Nucleo
+open development platform, with a wide choice of specialized Arduino* Uno V3
+shields.
+
+The STM32 Nucleo-144 board does not require any separate probe as it integrates
+the ST-LINK/V2-1 debugger/programmer.
+
+The STM32 Nucleo-144 board comes with the STM32 comprehensive free software
+libraries and examples available with the STM32Cube MCU Package.
+
+Key Features
+
+- STM32 microcontroller in LQFP144 package
+- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support)
+- USB OTG or full-speed device (depending on STM32 support)
+- 3 user LEDs
+- 2 user and reset push-buttons
+- 32.768 kHz crystal oscillator
+- Board connectors:
+
+  - USB with Micro-AB
+  - SWD
+  - Ethernet RJ45 (depending on STM32 support)
+  - ST Zio connector including Arduino* Uno V3
+  - ST morpho
+
+- Flexible power-supply options: ST-LINK USB VBUS or external sources.
+- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration
+  capability: mass storage, virtual COM port and debug port.
+- Comprehensive free software libraries and examples available with the
+- STM32Cube MCU package.
+- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers)
+
+.. image:: img/en.high-perf_nucleo-144_mbed.jpg
+   :width: 720px
+   :align: center
+   :height: 720px
+   :alt: Nucleo F756ZG
+
+More information about the board can be found at the `Nucleo F756ZG website`_.
+
+Hardware
+********
+
+Nucleo F756ZG provides the following hardware components:
+
+- STM32F756ZG in LQFP144 package
+- ARM 32-bit Cortex-M7 CPU with FPU
+- Chrom-ART Accelerator
+- ART Accelerator
+- 216 MHz max CPU frequency
+- VDD from 1.7 V to 3.6 V
+- 1 MB Flash
+- 320 KB SRAM
+- 16-bit timers(10)
+- 32-bit timers(2)
+- SPI(6)
+- I2C(4)
+- I2S (3)
+- USART(4)
+- UART(4)
+- USB OTG Full Speed and High Speed(1)
+- USB OTG Full Speed(1)
+- CAN(2)
+- SAI(2)
+- SPDIF_Rx(4)
+- HDMI_CEC(1)
+- Dual Mode Quad SPI(1)
+- Camera Interface
+- GPIO(up to 168) with external interrupt capability
+- 12-bit ADC(3) with 24 channels / 2.4 MSPS
+- 12-bit DAC with 2 channels(2)
+- True Random Number Generator (RNG)
+- 16-channel DMA
+- LCD-TFT Controller with XGA resolution
+
+Supported Features
+==================
+
+The Zephyr nucleo_f756zg board configuration supports the following hardware
+features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port                         |
++-----------+------------+-------------------------------------+
+| PINMUX    | on-chip    | pinmux                              |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+
+Other hardware features are not yet supported on this Zephyr port.
+
+The default configuration can be found in the defconfig file:
+``boards/arm/nucleo_f756zg/nucleo_f756zg_defconfig``
+
+For mode details please refer to `STM32 Nucleo-144 board User Manual`_.
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+The Nucleo F756ZG board features a ST Zio connector (extended Arduino Uno V3)
+and a ST morpho connector. Board is configured as follows:
+
+- UART_2 TX/RX/RTS/CTS : PD5/PD6/PD4/PD3
+- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com)
+- UART_6 TX/RX : PG14/PG9 (Arduino UART)
+- USER_PB : PC13
+- LD1 : PB0
+- LD2 : PB7
+- LD3 : PB14
+
+System Clock
+------------
+
+Nucleo F756ZG System Clock could be driven by an internal or external
+oscillator, as well as the main PLL clock. By default, the System clock is
+driven by the PLL clock at 72MHz, driven by an 8MHz high-speed external clock.
+
+Serial Port
+-----------
+
+Nucleo F756ZG board has 4 UARTs and 4 USARTs. The Zephyr console output is
+assigned to UART3. Default settings are 115200 8N1.
+
+
+Programming and Debugging
+*************************
+
+Applications for the ``nucleo_f756zg`` board configuration can be built and
+flashed in the usual way (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Flashing
+========
+
+Nucleo F756ZG board includes an ST-LINK/V2-1 embedded debug tool interface.
+
+Flashing an application to Nucleo F756ZG
+----------------------------------------
+
+Here is an example for the :ref:`hello_world` application.
+
+Run a serial host program to connect with your Nucleo board.
+
+.. code-block:: console
+
+   $ minicom -b 115200 -D /dev/ttyACM0
+
+Build and flash the application:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: nucleo_f756zg
+   :goals: build flash
+
+You should see the following message on the console:
+
+.. code-block:: console
+
+   $ Hello World! nucleo_f756zg
+
+Debugging
+=========
+
+You can debug an application in the usual way.  Here is an example for the
+:ref:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: nucleo_f756zg
+   :maybe-skip-config:
+   :goals: debug
+
+.. _Nucleo F756ZG website:
+   https://www.st.com/en/evaluation-tools/nucleo-f756zg.html
+
+.. _STM32 Nucleo-144 board User Manual:
+   http://www.st.com/resource/en/user_manual/dm00105823.pdf
+
+.. _STM32F756ZG on www.st.com:
+   https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x6/stm32f756zg.html
+
+.. _STM32F756 reference manual:
+   https://www.st.com/resource/en/reference_manual/dm00124865.pdf
+

boards/arm/nucleo_f756zg/nucleo_f756zg.dts

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2018 AJ Palmer
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/f7/stm32f756Xg.dtsi>
+
+/ {
+	model = "STMicroelectronics STM32F756ZG-NUCLEO board";
+	compatible = "st,stm32f756zg-nucleo", "st,stm32f756";
+
+	chosen {
+		zephyr,console = &usart3;
+		zephyr,shell-uart = &usart3;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		green_led: led_0 {
+			gpios = <&gpiob 0 GPIO_INT_ACTIVE_HIGH>;
+			label = "User LD1";
+		};
+		blue_led: led_1 {
+			gpios = <&gpiob 7 GPIO_INT_ACTIVE_HIGH>;
+			label = "User LD2";
+		};
+		red_led: led_2 {
+			gpios = <&gpiob 14 GPIO_INT_ACTIVE_HIGH>;
+			label = "User LD3";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button: button_0 {
+			label = "User";
+			gpios = <&gpioc 13 GPIO_INT_ACTIVE_LOW>;
+		};
+	};
+
+	aliases {
+		led0 = &green_led;
+		led1 = &blue_led;
+		led2 = &red_led;
+		sw0 = &user_button;
+	};
+};
+
+arduino_serial: &usart6 {};
+
+&usart2 {
+	current-speed = <115200>;
+	pinctrl-0 = <&usart2_pins_b>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&usart3 {
+	current-speed = <115200>;
+	pinctrl-0 = <&usart3_pins_b>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&usart6 {
+	current-speed = <115200>;
+	pinctrl-0 = <&usart6_pins_a>;
+	pinctrl-names = "default";
+	status = "ok";
+};

boards/arm/nucleo_f756zg/nucleo_f756zg.yaml

@@ -0,0 +1,12 @@
+identifier: nucleo_f756zg
+name: NUCLEO-F756ZG
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 320
+flash: 1024
+supported:
+  - uart
+  - gpio

boards/arm/nucleo_f756zg/nucleo_f756zg_defconfig

@@ -0,0 +1,44 @@
+CONFIG_ARM=y
+CONFIG_BOARD_NUCLEO_F756ZG=y
+CONFIG_SOC_SERIES_STM32F7X=y
+CONFIG_SOC_STM32F756XX=y
+# 72MHz system clock (CubeMX Defaults)
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable UART
+CONFIG_SERIAL=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable Pinmux
+CONFIG_PINMUX=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Clock Configuration
+CONFIG_CLOCK_CONTROL=y
+
+# STLINK provides 8MHz clock input
+CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
+CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
+# Use HSE as PLL input
+CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
+# Nucleo-144 boards do not have an external oscillator, so just use
+# the 8MHz clock signal coming from integrated STLink
+CONFIG_CLOCK_STM32_HSE_BYPASS=y
+
+# Produce 72MHz clock at PLL output
+CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4
+CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=72
+CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
+CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=3
+CONFIG_CLOCK_STM32_AHB_PRESCALER=1
+CONFIG_CLOCK_STM32_APB1_PRESCALER=2
+CONFIG_CLOCK_STM32_APB2_PRESCALER=1

boards/arm/nucleo_f756zg/pinmux.c

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2018 AJ Palmer
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel.h>
+#include <device.h>
+#include <init.h>
+#include <pinmux.h>
+#include <sys_io.h>
+
+#include <pinmux/stm32/pinmux_stm32.h>
+
+/* NUCLEO-F756ZG pin configurations  */
+static const struct pin_config pinconf[] = {
+#ifdef CONFIG_UART_2
+	{ STM32_PIN_PD5, STM32F7_PINMUX_FUNC_PD5_USART2_TX },
+	{ STM32_PIN_PD6, STM32F7_PINMUX_FUNC_PD6_USART2_RX },
+	{ STM32_PIN_PD4, STM32F7_PINMUX_FUNC_PD4_USART2_RTS },
+	{ STM32_PIN_PD3, STM32F7_PINMUX_FUNC_PD3_USART2_CTS },
+#endif
+#ifdef CONFIG_UART_3
+	{ STM32_PIN_PD8, STM32F7_PINMUX_FUNC_PD8_USART3_TX },
+	{ STM32_PIN_PD9, STM32F7_PINMUX_FUNC_PD9_USART3_RX },
+#endif
+#ifdef CONFIG_UART_6
+	{ STM32_PIN_PG14, STM32F7_PINMUX_FUNC_PG14_USART6_TX },
+	{ STM32_PIN_PG9, STM32F7_PINMUX_FUNC_PG9_USART6_RX },
+#endif
+};
+
+static int pinmux_stm32_init(struct device *port)
+{
+	ARG_UNUSED(port);
+
+	stm32_setup_pins(pinconf, ARRAY_SIZE(pinconf));
+
+	return 0;
+}
+
+SYS_INIT(pinmux_stm32_init, PRE_KERNEL_1,
+	 CONFIG_PINMUX_STM32_DEVICE_INITIALIZATION_PRIORITY);

boards/arm/nucleo_f756zg/support/openocd.cfg

@@ -0,0 +1,12 @@
+source [find board/st_nucleo_f7.cfg]
+
+$_TARGETNAME configure -event gdb-attach {
+        echo "Debugger attaching: halting execution"
+        reset halt
+        gdb_breakpoint_override hard
+}
+
+$_TARGETNAME configure -event gdb-detach {
+        echo "Debugger detaching: resuming execution"
+        resume
+}

dts/arm/st/f7/stm32f756.dtsi

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2018 AJ Palmer
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f7/stm32f746.dtsi>

dts/arm/st/f7/stm32f756Xg.dtsi

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2018 AJ Palmer
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f7/stm32f756.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(320)>;
+	};
+
+	flash0: flash@8000000 {
+		reg = <0x08000000 DT_SIZE_K(1024)>;
+	};
+};

soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f756xx

@@ -0,0 +1,34 @@
+# Kconfig - ST STM32F756XX MCU configuration options
+#
+# Copyright (c) 2018 AJ Palmer
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F756XX
+
+config SOC
+	string
+	default "stm32f756xx"
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTF
+	default y
+
+config GPIO_STM32_PORTG
+	default y
+
+config GPIO_STM32_PORTJ
+	default y
+
+config GPIO_STM32_PORTK
+	default y
+
+endif # GPIO_STM32
+
+config NUM_IRQS
+	int
+	default 98
+
+endif # SOC_STM32F756XX

soc/arm/st_stm32/stm32f7/Kconfig.soc

@@ -15,6 +15,9 @@ config SOC_STM32F723XE
 config SOC_STM32F746XG
 	bool "STM32F746XG"
 
+config SOC_STM32F756XX
+	bool "STM32F756XX"
+
 config SOC_STM32F769XI
 	bool "STM32F769XI"