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drivers: clock_control: infineon_cat1: Support for LF clocks

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Add support to configure LF clocks: clk_pilo, clk_wco, clk_ilo, clk_lf

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
This commit is contained in:
Sreeram Tatapudi 2025-05-08 10:43:47 -07:00 • committed by Benjamin Cabé
commit 2ef8ff4e04
2 changed files with 221 additions and 78 deletions
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198
drivers/clock_control/clock_control_ifx_cat1.c
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@ -126,21 +126,46 @@ enum {
INFINEON_CAT1_CLOCK_FLL0,
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_pilo))
INFINEON_CAT1_CLOCK_PILO,
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_wco))
INFINEON_CAT1_CLOCK_WCO,
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_ilo))
INFINEON_CAT1_CLOCK_ILO,
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_lf))
INFINEON_CAT1_CLOCK_LF,
#endif
/* Count of enabled clock */
INFINEON_CAT1_ENABLED_CLOCK_COUNT
}; /* infineon_cat1_clock_info_name_t */
/* Clock info structure */
struct infineon_cat1_clock_info_t {
cyhal_clock_t obj; /* Hal Clock object */
union clock_obj {
/* For all clock instance which configure via cyhal,
* we should keep cyhal_clock_t object.
*/
cyhal_clock_t cyhal_clock; /* Hal Clock object */
/* For all clklf (in sources keep) information about the
* name (cy_en_clklf_in_sources_t).
*/
cy_en_clklf_in_sources_t clklf_in_source;
} obj;
uint32_t dt_ord; /* Device tree node's dependency ordinal */
};
/* Lookup table which presents clock objects (cyhal_clock_t) correspondence to ordinal
* number of device tree clock nodes.
*/
static struct infineon_cat1_clock_info_t
clock_info_table[INFINEON_CAT1_ENABLED_CLOCK_COUNT] = {
static struct infineon_cat1_clock_info_t clock_info_table[INFINEON_CAT1_ENABLED_CLOCK_COUNT] = {
/* We always have IMO */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_imo))
[INFINEON_CAT1_CLOCK_IMO] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_imo))},
@ -249,10 +274,29 @@ static struct infineon_cat1_clock_info_t
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(fll0))
[INFINEON_CAT1_CLOCK_FLL0] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(fll0))},
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_pilo))
[INFINEON_CAT1_CLOCK_PILO] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_pilo)),
.obj.clklf_in_source = CY_SYSCLK_CLKLF_IN_PILO},
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_wco))
[INFINEON_CAT1_CLOCK_WCO] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_wco)),
.obj.clklf_in_source = CY_SYSCLK_CLKLF_IN_WCO},
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_ilo))
[INFINEON_CAT1_CLOCK_ILO] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_ilo)),
.obj.clklf_in_source = CY_SYSCLK_CLKLF_IN_ILO},
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_lf))
[INFINEON_CAT1_CLOCK_LF] = {.dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_lf))},
#endif
};
static cy_rslt_t _configure_path_mux(cyhal_clock_t *clock_obj,
cyhal_clock_t *clock_source_obj,
static cy_rslt_t _configure_path_mux(cyhal_clock_t *clock_obj, cyhal_clock_t *clock_source_obj,
const cyhal_clock_t *reserve_obj)
{
cy_rslt_t rslt;
@ -268,10 +312,8 @@ static cy_rslt_t _configure_path_mux(cyhal_clock_t *clock_obj,
return rslt;
}
static cy_rslt_t _configure_clk_hf(cyhal_clock_t *clock_obj,
cyhal_clock_t *clock_source_obj,
const cyhal_clock_t *reserve_obj,
uint32_t clock_div)
static cy_rslt_t _configure_clk_hf(cyhal_clock_t *clock_obj, cyhal_clock_t *clock_source_obj,
const cyhal_clock_t *reserve_obj, uint32_t clock_div)
{
cy_rslt_t rslt;
@ -319,14 +361,30 @@ static cyhal_clock_t *_get_hal_obj_from_ord(uint32_t dt_ord)
for (uint32_t i = 0u; i < INFINEON_CAT1_ENABLED_CLOCK_COUNT; i++) {
if (clock_info_table[i].dt_ord == dt_ord) {
ret_obj = &clock_info_table[i].obj;
ret_obj = &clock_info_table[i].obj.cyhal_clock;
return ret_obj;
}
}
return ret_obj;
}
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dpll_hp))
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_lf))
static cy_en_clklf_in_sources_t _get_clklf_source_from_ord(uint32_t dt_ord)
{
cy_en_clklf_in_sources_t ret_clklf_in_source = CY_SYSCLK_CLKLF_IN_ILO;
for (uint32_t i = 0u; i < INFINEON_CAT1_ENABLED_CLOCK_COUNT; i++) {
if (clock_info_table[i].dt_ord == dt_ord) {
return clock_info_table[i].obj.clklf_in_source;
}
}
return ret_clklf_in_source;
}
#endif
#define CY_CFG_SYSCLK_PLL_ERROR 3
#define CY_CFG_SYSCLK_WCO_ERROR 2
__WEAK void cycfg_ClockStartupError(uint32_t error)
{
(void)error; /* Suppress the compiler warning */
@ -334,10 +392,9 @@ __WEAK void cycfg_ClockStartupError(uint32_t error)
}
}
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dpll_hp))
void Cy_SysClk_Dpll_Hp0_Init(void)
{
#define CY_CFG_SYSCLK_PLL_ERROR 3
static cy_stc_dpll_hp_config_t srss_0_clock_0_pll500m_0_hp_pllConfig = {
.pDiv = 0,
.nDiv = 15,
@ -377,7 +434,43 @@ void Cy_SysClk_Dpll_Hp0_Init(void)
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
}
#endif
#endif /* DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dpll_hp)) */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_pilo))
static inline void Cy_SysClk_PiloInit(void)
{
Cy_SysClk_PiloEnable();
if (!Cy_SysClk_PiloOkay()) {
Cy_SysPm_TriggerXRes();
}
}
#endif /* DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_pilo)) */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_wco))
#define CY_CFG_SYSCLK_WCO_IN_PRT GPIO_PRT5
#define CY_CFG_SYSCLK_WCO_IN_PIN 0U
#define CY_CFG_SYSCLK_WCO_OUT_PRT GPIO_PRT5
#define CY_CFG_SYSCLK_WCO_OUT_PIN 1U
static inline void Cy_SysClk_WcoInit(void)
{
(void)Cy_GPIO_Pin_FastInit(GPIO_PRT5, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
(void)Cy_GPIO_Pin_FastInit(GPIO_PRT5, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) {
cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
}
}
#endif /* DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_wco)) */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_ilo))
static inline void Cy_SysClk_IloInit(void)
{
/* The WDT is unlocked in the default startup code */
Cy_SysClk_IloEnable();
Cy_SysClk_IloHibernateOn(true);
}
#endif /* DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_ilo)) */
static int clock_control_infineon_cat1_init(const struct device *dev)
{
@ -391,13 +484,13 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure IMO */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_imo))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_IMO].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_IMO].obj.cyhal_clock;
if (cyhal_clock_get(clock_obj, &CYHAL_CLOCK_RSC_IMO)) {
return -EIO;
}
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_iho))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_IHO].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_IHO].obj.cyhal_clock;
if (cyhal_clock_get(clock_obj, &CYHAL_CLOCK_RSC_IHO)) {
return -EIO;
}
@ -409,7 +502,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the PathMux[0] to source defined in tree device 'path_mux0' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux0))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX0].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX0].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(path_mux0));
if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[0])) {
@ -419,7 +512,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the PathMux[1] to source defined in tree device 'path_mux1' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux1))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX1].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX1].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(path_mux1));
if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[1])) {
@ -429,7 +522,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the PathMux[2] to source defined in tree device 'path_mux2' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux2))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX2].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX2].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(path_mux2));
if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[2])) {
@ -439,7 +532,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the PathMux[3] to source defined in tree device 'path_mux3' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux3))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX3].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX3].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(path_mux3));
if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[3])) {
@ -449,7 +542,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the PathMux[4] to source defined in tree device 'path_mux4' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux4))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX4].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX4].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(path_mux4));
if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[4])) {
@ -459,7 +552,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure FLL0 */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(fll0))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_FLL0].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_FLL0].obj.cyhal_clock;
frequency = DT_PROP(DT_NODELABEL(fll0), clock_frequency);
rslt = _configure_clk_frequency_and_enable(clock_obj, clock_source_obj,
@ -471,7 +564,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure PLL0 */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll0))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PLL0].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PLL0].obj.cyhal_clock;
frequency = DT_PROP(DT_NODELABEL(pll0), clock_frequency);
rslt = _configure_clk_frequency_and_enable(clock_obj, clock_source_obj,
@ -484,7 +577,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure PLL1 */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll1))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PLL1].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PLL1].obj.cyhal_clock;
frequency = DT_PROP(DT_NODELABEL(pll1), clock_frequency);
rslt = _configure_clk_frequency_and_enable(clock_obj, clock_source_obj,
@ -496,7 +589,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the HF[0] to source defined in tree device 'clk_hf0' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf0))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF0].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF0].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf0));
clock_div = DT_PROP(DT_NODELABEL(clk_hf0), clock_div);
@ -507,7 +600,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the HF[1] to source defined in tree device 'clk_hf1' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf1))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF1].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF1].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf1));
clock_div = DT_PROP(DT_NODELABEL(clk_hf1), clock_div);
@ -518,7 +611,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the HF[2] to source defined in tree device 'clk_hf2' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf2))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF2].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF2].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf2));
clock_div = DT_PROP(DT_NODELABEL(clk_hf2), clock_div);
@ -529,12 +622,11 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the HF[3] to source defined in tree device 'clk_hf3' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf3))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF3].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF3].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf3));
clock_div = DT_PROP(DT_NODELABEL(clk_hf3), clock_div);
#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1B) && \
defined(CONFIG_USE_INFINEON_ADC)
#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1B) && defined(CONFIG_USE_INFINEON_ADC)
Cy_SysClk_ClkHfSetSource(3, CY_SYSCLK_CLKHF_IN_CLKPATH1);
Cy_SysClk_ClkHfSetDivider(3, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfEnable(3);
@ -547,7 +639,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the HF[4] to source defined in tree device 'clk_hf4' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf4))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF4].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF4].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf4));
clock_div = DT_PROP(DT_NODELABEL(clk_hf4), clock_div);
@ -558,7 +650,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the HF[5] to source defined in tree device 'clk_hf5' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf5))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF5].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF5].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf5));
clock_div = DT_PROP(DT_NODELABEL(clk_hf5), clock_div);
@ -569,7 +661,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the HF[6] to source defined in tree device 'clk_hf6' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf6))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF6].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF6].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf6));
clock_div = DT_PROP(DT_NODELABEL(clk_hf6), clock_div);
@ -580,7 +672,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the HF[7] to source defined in tree device 'clk_hf7' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf7))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF7].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF7].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf7));
clock_div = DT_PROP(DT_NODELABEL(clk_hf7), clock_div);
@ -591,7 +683,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the HF[8] to source defined in tree device 'clk_hf8' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf8))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF8].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF8].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf8));
clock_div = DT_PROP(DT_NODELABEL(clk_hf8), clock_div);
@ -602,7 +694,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the HF[9] to source defined in tree device 'clk_hf9' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf9))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF9].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF9].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf9));
clock_div = DT_PROP(DT_NODELABEL(clk_hf9), clock_div);
@ -613,7 +705,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the HF[10] to source defined in tree device 'clk_hf10' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf10))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF10].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF10].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf10));
clock_div = DT_PROP(DT_NODELABEL(clk_hf10), clock_div);
@ -624,7 +716,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the HF[11] to source defined in tree device 'clk_hf11' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf11))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF11].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF11].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf11));
clock_div = DT_PROP(DT_NODELABEL(clk_hf11), clock_div);
@ -635,7 +727,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the HF[12] to source defined in tree device 'clk_hf12' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf12))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF12].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF12].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf12));
clock_div = DT_PROP(DT_NODELABEL(clk_hf12), clock_div);
@ -646,7 +738,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the HF[13] to source defined in tree device 'clk_hf13' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf13))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF13].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF13].obj.cyhal_clock;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf13));
clock_div = DT_PROP(DT_NODELABEL(clk_hf13), clock_div);
@ -657,7 +749,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the clock fast to source defined in tree device 'clk_fast' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_fast))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_FAST].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_FAST].obj.cyhal_clock;
clock_div = DT_PROP(DT_NODELABEL(clk_fast), clock_div);
rslt = cyhal_clock_reserve(clock_obj, &CYHAL_CLOCK_FAST);
@ -671,7 +763,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the clock peri to source defined in tree device 'clk_peri' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_peri))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PERI].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PERI].obj.cyhal_clock;
clock_div = DT_PROP(DT_NODELABEL(clk_peri), clock_div);
rslt = cyhal_clock_reserve(clock_obj, &CYHAL_CLOCK_PERI);
@ -685,7 +777,7 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
/* Configure the clock slow to source defined in tree device 'clk_slow' node */
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_slow))
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_SLOW].obj;
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_SLOW].obj.cyhal_clock;
clock_div = DT_PROP(DT_NODELABEL(clk_slow), clock_div);
rslt = cyhal_clock_reserve(clock_obj, &CYHAL_CLOCK_SLOW);
@ -702,11 +794,27 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
SystemCoreClockUpdate();
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_pilo))
Cy_SysClk_PiloInit();
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_wco))
Cy_SysClk_WcoInit();
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_ilo))
Cy_SysClk_IloInit();
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_lf))
/* set ClkLf source (PILO, ILO, WCO) */
Cy_SysClk_ClkLfSetSource(_get_clklf_source_from_ord(GET_CLK_SOURCE_ORD(clk_lf)));
#endif
return (int)rslt;
}
static int clock_control_infineon_cat_on_off(const struct device *dev,
clock_control_subsys_t sys)
static int clock_control_infineon_cat_on_off(const struct device *dev, clock_control_subsys_t sys)
{
ARG_UNUSED(dev);
ARG_UNUSED(sys);

35
dts/arm/infineon/cat1b/cyw20829/system_clocks.dtsi
View file

@ -100,6 +100,41 @@
status = "disabled";
};
/* LF frequency */
/* pilo */
clk_pilo: clk_pilo {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
status = "okay";
};
/* wco */
clk_wco: clk_wco {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
status = "disabled";
};
/* ilo */
clk_ilo: clk_ilo {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
status = "disabled";
};
/* clk_lf */
clk_lf: clk_lf {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_pilo>;
status = "okay";
};
};
};