From 2ec7a8df3a15ea4befbf032bfe7e21dd83be7ae2 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 13 Mar 2024 16:59:48 -0500 Subject: [PATCH] dts: bindings: add devicetree binding for NXP LCDIC Add devicetree binding for NXP LCDIC. This controller is capable of driving displays in 8080 or SPI 3/4 wire mode, and optionally swapping endianness of display data as it sends it. Signed-off-by: Daniel DeGrasse --- dts/bindings/mipi-dbi/nxp,lcdic.yaml | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 dts/bindings/mipi-dbi/nxp,lcdic.yaml diff --git a/dts/bindings/mipi-dbi/nxp,lcdic.yaml b/dts/bindings/mipi-dbi/nxp,lcdic.yaml new file mode 100644 index 00000000000..b8a38ba2c74 --- /dev/null +++ b/dts/bindings/mipi-dbi/nxp,lcdic.yaml @@ -0,0 +1,25 @@ +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: | + NXP LCDIC Controller. This controller implements 8080 and SPI mode MIPI-DBI + compliant transfers. Only SPI mode is currently supported. +compatible: "nxp,lcdic" + +include: ["mipi-dbi-controller.yaml", "pinctrl-device.yaml"] + +properties: + reg: + required: true + + interrupts: + required: true + + clocks: + required: true + + nxp,swap-bytes: + type: boolean + description: | + Swap bytes while transferring on LCDIC. When set, the LCDIC will send + the most significant byte first when using multibyte pixel formats.