arch: x86: Reorder the SoC power states for Quark SE
Re-oredered the SoC power states such that SYS_POWER_STATE_CPU_LPS is the lowest possible Low Power State(LPS) and SYS_POWER_STATE_CPU_LPS_2 is the highest possible Low Power State(LPS). This is need to maintain the LPS state consistency across different architectures. Also removed the redundant SYS_POWER_STATE_DEEP_SLEEP_2 state. Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
This commit is contained in:
parent
83db9ad753
commit
2e615181f0
2 changed files with 14 additions and 21 deletions
|
@ -45,11 +45,10 @@ static void _deep_sleep(enum power_states state)
|
|||
qm_power_soc_set_x86_restore_flag();
|
||||
|
||||
switch (state) {
|
||||
case SYS_POWER_STATE_DEEP_SLEEP_1:
|
||||
case SYS_POWER_STATE_DEEP_SLEEP:
|
||||
_power_soc_sleep();
|
||||
break;
|
||||
case SYS_POWER_STATE_DEEP_SLEEP:
|
||||
case SYS_POWER_STATE_DEEP_SLEEP_2:
|
||||
case SYS_POWER_STATE_DEEP_SLEEP_1:
|
||||
_power_soc_deep_sleep();
|
||||
break;
|
||||
default:
|
||||
|
@ -62,18 +61,17 @@ void _sys_soc_set_power_state(enum power_states state)
|
|||
{
|
||||
switch (state) {
|
||||
case SYS_POWER_STATE_CPU_LPS:
|
||||
qm_power_cpu_c2lp();
|
||||
qm_power_cpu_c1();
|
||||
break;
|
||||
case SYS_POWER_STATE_CPU_LPS_1:
|
||||
qm_power_cpu_c2();
|
||||
break;
|
||||
case SYS_POWER_STATE_CPU_LPS_2:
|
||||
qm_power_cpu_c1();
|
||||
qm_power_cpu_c2lp();
|
||||
break;
|
||||
#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP))
|
||||
case SYS_POWER_STATE_DEEP_SLEEP:
|
||||
case SYS_POWER_STATE_DEEP_SLEEP_1:
|
||||
case SYS_POWER_STATE_DEEP_SLEEP_2:
|
||||
_deep_sleep(state);
|
||||
break;
|
||||
#endif
|
||||
|
@ -85,19 +83,19 @@ void _sys_soc_set_power_state(enum power_states state)
|
|||
void _sys_soc_power_state_post_ops(enum power_states state)
|
||||
{
|
||||
switch (state) {
|
||||
case SYS_POWER_STATE_CPU_LPS:
|
||||
case SYS_POWER_STATE_CPU_LPS_2:
|
||||
*_REG_TIMER_ICR = 1;
|
||||
case SYS_POWER_STATE_CPU_LPS_1:
|
||||
case SYS_POWER_STATE_CPU_LPS:
|
||||
__asm__ volatile("sti");
|
||||
break;
|
||||
#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP))
|
||||
case SYS_POWER_STATE_DEEP_SLEEP_2:
|
||||
case SYS_POWER_STATE_DEEP_SLEEP_1:
|
||||
#ifdef CONFIG_ARC_INIT
|
||||
_arc_init(NULL);
|
||||
#endif /* CONFIG_ARC_INIT */
|
||||
/* Fallthrough */
|
||||
case SYS_POWER_STATE_DEEP_SLEEP:
|
||||
case SYS_POWER_STATE_DEEP_SLEEP_1:
|
||||
__asm__ volatile("sti");
|
||||
break;
|
||||
#endif
|
||||
|
|
|
@ -20,14 +20,12 @@ extern "C" {
|
|||
#define GP0_BIT_SLEEP_READY BIT(0)
|
||||
|
||||
enum power_states {
|
||||
SYS_POWER_STATE_CPU_LPS, /* C2LP state */
|
||||
SYS_POWER_STATE_CPU_LPS, /* C1 state */
|
||||
SYS_POWER_STATE_CPU_LPS_1, /* C2 state */
|
||||
SYS_POWER_STATE_CPU_LPS_2, /* C1 state */
|
||||
SYS_POWER_STATE_DEEP_SLEEP, /* DEEP SLEEP state */
|
||||
SYS_POWER_STATE_DEEP_SLEEP_1, /* SLEEP state */
|
||||
SYS_POWER_STATE_DEEP_SLEEP_2, /* Multicore support for
|
||||
* DEEP_SLEEP state.
|
||||
*/
|
||||
SYS_POWER_STATE_CPU_LPS_2, /* C2LP state */
|
||||
SYS_POWER_STATE_DEEP_SLEEP, /* SLEEP state */
|
||||
SYS_POWER_STATE_DEEP_SLEEP_1, /* SLEEP state with LPMODE enabled */
|
||||
|
||||
SYS_POWER_STATE_MAX
|
||||
};
|
||||
|
||||
|
@ -38,13 +36,13 @@ enum power_states {
|
|||
* to put the processor into available power states.
|
||||
*
|
||||
* Wake up considerations:
|
||||
* SYS_POWER_STATE_CPU_LPS_2: Any interrupt works as wake event.
|
||||
* SYS_POWER_STATE_CPU_LPS: Any interrupt works as wake event.
|
||||
*
|
||||
* SYS_POWER_STATE_CPU_LPS_1: Any interrupt works as wake event except
|
||||
* if the core enters LPSS where SYS_POWER_STATE_DEEP_SLEEP wake events
|
||||
* applies.
|
||||
*
|
||||
* SYS_POWER_STATE_CPU_LPS: Any interrupt works as wake event except the
|
||||
* SYS_POWER_STATE_CPU_LPS_2: Any interrupt works as wake event except the
|
||||
* PIC timer which is gated. If the core enters LPSS only
|
||||
* SYS_POWER_STATE_DEEP_SLEEP wake events applies.
|
||||
*
|
||||
|
@ -53,9 +51,6 @@ enum power_states {
|
|||
*
|
||||
* SYS_POWER_STATE_DEEP_SLEEP_1: Only Always-On peripherals can wake up
|
||||
* the SoC. This consists of the Counter, RTC, GPIO 1 and AIO Comparator.
|
||||
*
|
||||
* SYS_POWER_STATE_DEEP_SLEEP_2: Only Always-On peripherals can wake up
|
||||
* the SoC. This consists of the Counter, RTC, GPIO 1 and AIO Comparator.
|
||||
*/
|
||||
void _sys_soc_set_power_state(enum power_states state);
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue