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soc: riscv: esp32c3: adds _PrepC to the startup code

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The _PrepC() function is the standard risc-v way
of zephyr entry point, so let it call the z_cstart instead
of calling this function directly.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
This commit is contained in:
Felipe Neves 2021-06-17 11:46:07 -03:00 • committed by Anas Nashif
commit 2d1bdd86b6
2 changed files with 4 additions and 10 deletions
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6
boards/riscv/esp32c3_devkitm/doc/index.rst
View file

@ -1,7 +1,7 @@
.. _esp32c3_devkitm:
ESP32-C3
#####
########
Overview
********
@ -71,9 +71,7 @@ machine without any other such converters.
The baud rate of 921600bps is recommended. If experiencing issues when
flashing, try halving the value a few times (460800, 230400, 115200,
etc). It might be necessary to change the flash frequency or the flash
mode; please refer to the `esptool documentation`_ for guidance on these
settings.
etc).
All flashing options are now handled by the :ref:`west` tool, including flashing
with custom options such as a different serial port. The ``west`` tool supports

8
soc/riscv/esp32c3/soc.c
View file

@ -22,9 +22,8 @@
#define ESP32C3_INTC_DEFAULT_PRIO 15
extern void z_cstart(void);
extern void _PrepC(void);
extern void esprv_intc_int_set_threshold(int priority_threshold);
extern void z_bss_zero(void);
/*
* This is written in C rather than assembly since, during the port bring up,
@ -51,9 +50,6 @@ void __attribute__((section(".iram1"))) __start(void)
/* Disable normal interrupts. */
csr_read_clear(mstatus, MSTATUS_MIE);
/* Zero out BSS */
z_bss_zero();
#if !CONFIG_BOOTLOADER_ESP_IDF
/* The watchdog timer is enabled in the 1st stage (ROM) bootloader.
* We're done booting, so disable it.
@ -99,7 +95,7 @@ void __attribute__((section(".iram1"))) __start(void)
esprv_intc_int_set_threshold(1);
/* Start Zephyr */
z_cstart();
_PrepC();
CODE_UNREACHABLE;
}