spi: Fixing documentation for groups of macros

Group macros documentation properly.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka 2021-11-17 09:50:36 +01:00 committed by Carles Cufí
commit 2cf6c8061e
2 changed files with 22 additions and 7 deletions

View file

@ -30,15 +30,18 @@ extern "C" {
#endif #endif
/** /**
* @brief SPI operational mode * @name SPI operational mode
* @{
*/ */
#define SPI_OP_MODE_MASTER 0U #define SPI_OP_MODE_MASTER 0U
#define SPI_OP_MODE_SLAVE BIT(0) #define SPI_OP_MODE_SLAVE BIT(0)
#define SPI_OP_MODE_MASK 0x1U #define SPI_OP_MODE_MASK 0x1U
#define SPI_OP_MODE_GET(_operation_) ((_operation_) & SPI_OP_MODE_MASK) #define SPI_OP_MODE_GET(_operation_) ((_operation_) & SPI_OP_MODE_MASK)
/** @} */
/** /**
* @brief SPI Polarity & Phase Modes * @name SPI Polarity & Phase Modes
* @{
*/ */
/** /**
@ -68,14 +71,19 @@ extern "C" {
#define SPI_MODE_GET(_mode_) \ #define SPI_MODE_GET(_mode_) \
((_mode_) & SPI_MODE_MASK) ((_mode_) & SPI_MODE_MASK)
/** @} */
/** /**
* @brief SPI Transfer modes (host controller dependent) * @name SPI Transfer modes (host controller dependent)
* @{
*/ */
#define SPI_TRANSFER_MSB (0U) #define SPI_TRANSFER_MSB (0U)
#define SPI_TRANSFER_LSB BIT(4) #define SPI_TRANSFER_LSB BIT(4)
/** @} */
/** /**
* @brief SPI word size * @name SPI word size
* @{
*/ */
#define SPI_WORD_SIZE_SHIFT (5U) #define SPI_WORD_SIZE_SHIFT (5U)
#define SPI_WORD_SIZE_MASK (0x3FU << SPI_WORD_SIZE_SHIFT) #define SPI_WORD_SIZE_MASK (0x3FU << SPI_WORD_SIZE_SHIFT)
@ -84,9 +92,11 @@ extern "C" {
#define SPI_WORD_SET(_word_size_) \ #define SPI_WORD_SET(_word_size_) \
((_word_size_) << SPI_WORD_SIZE_SHIFT) ((_word_size_) << SPI_WORD_SIZE_SHIFT)
/** @} */
/** /**
* @brief Specific SPI devices control bits * @name Specific SPI devices control bits
* @{
*/ */
/* Requests - if possible - to keep CS asserted after the transaction */ /* Requests - if possible - to keep CS asserted after the transaction */
#define SPI_HOLD_ON_CS BIT(12) #define SPI_HOLD_ON_CS BIT(12)
@ -105,9 +115,11 @@ extern "C" {
* the solution. * the solution.
*/ */
#define SPI_CS_ACTIVE_HIGH BIT(14) #define SPI_CS_ACTIVE_HIGH BIT(14)
/** @} */
/** /**
* @brief SPI MISO lines (if @kconfig{CONFIG_SPI_EXTENDED_MODES} is enabled) * @name SPI MISO lines (if @kconfig{CONFIG_SPI_EXTENDED_MODES} is enabled)
* @{
* *
* Some controllers support dual, quad or octal MISO lines connected to slaves. * Some controllers support dual, quad or octal MISO lines connected to slaves.
* Default is single, which is the case most of the time. * Default is single, which is the case most of the time.
@ -120,6 +132,7 @@ extern "C" {
#define SPI_LINES_OCTAL (3U << 16) #define SPI_LINES_OCTAL (3U << 16)
#define SPI_LINES_MASK (0x3U << 16) #define SPI_LINES_MASK (0x3U << 16)
/** @} */
/** /**
* @brief SPI Chip Select control structure * @brief SPI Chip Select control structure

View file

@ -14,13 +14,15 @@
*/ */
/** /**
* @brief SPI duplex mode * @name SPI duplex mode
* @{
* *
* Some controllers support half duplex transfer, which results in 3-wire usage. * Some controllers support half duplex transfer, which results in 3-wire usage.
* By default, full duplex will prevail. * By default, full duplex will prevail.
*/ */
#define SPI_FULL_DUPLEX (0U << 11) #define SPI_FULL_DUPLEX (0U << 11)
#define SPI_HALF_DUPLEX (1U << 11) #define SPI_HALF_DUPLEX (1U << 11)
/** @} */
/** /**
* @} * @}