driver: i2s: fixing build error
some build error due to adding rt11xx support without testing update mclk enable to avoid add pinmux driver note: some other PRs still in progress to full enable i2s on rt platform this fixing: #41153 Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
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dbe473bc83
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2cbdd12e9c
1 changed files with 33 additions and 37 deletions
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@ -18,7 +18,6 @@
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#include <drivers/dma.h>
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#include <drivers/dma.h>
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#include <drivers/i2s.h>
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#include <drivers/i2s.h>
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#include <drivers/pinmux.h>
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#include <drivers/clock_control.h>
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#include <drivers/clock_control.h>
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#include <dt-bindings/clock/imx_ccm.h>
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#include <dt-bindings/clock/imx_ccm.h>
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#include <soc.h>
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#include <soc.h>
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@ -69,7 +68,6 @@ struct i2s_mcux_config {
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uint32_t clk_src;
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uint32_t clk_src;
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uint32_t clk_pre_div;
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uint32_t clk_pre_div;
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uint32_t clk_src_div;
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uint32_t clk_src_div;
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uint32_t clk_src;
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uint32_t pll_src;
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uint32_t pll_src;
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uint32_t pll_lp;
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uint32_t pll_lp;
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uint32_t pll_pd;
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uint32_t pll_pd;
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@ -80,7 +78,6 @@ struct i2s_mcux_config {
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uint32_t tx_channel;
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uint32_t tx_channel;
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clock_control_subsys_t clk_sub_sys;
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clock_control_subsys_t clk_sub_sys;
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const struct device *ccm_dev;
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const struct device *ccm_dev;
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const struct device *pinmux_dev;
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void (*irq_connect)(const struct device *dev);
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void (*irq_connect)(const struct device *dev);
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bool rx_sync_mode;
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bool rx_sync_mode;
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bool tx_sync_mode;
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bool tx_sync_mode;
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@ -329,25 +326,17 @@ static void i2s_dma_rx_callback(const struct device *dma_dev,
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static void enable_mclk_direction(const struct device *dev, bool dir)
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static void enable_mclk_direction(const struct device *dev, bool dir)
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{
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{
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const struct i2s_mcux_config *dev_cfg = dev->config;
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const struct i2s_mcux_config *dev_cfg = dev->config;
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const struct device *iomuxgpr_dev = dev_cfg->pinmux_dev;
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uint32_t offset = dev_cfg->mclk_pin_offset;
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uint32_t offset = dev_cfg->mclk_pin_offset;
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uint32_t mask = dev_cfg->mclk_pin_mask;
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uint32_t mask = dev_cfg->mclk_pin_mask;
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uint32_t value = 0;
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uint32_t value = 0;
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uint32_t *gpr = (uint32_t *)DT_REG_ADDR(DT_NODELABEL(iomuxcgpr)) + offset;
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if (iomuxgpr_dev == NULL) {
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LOG_ERR("fail to find pinmux controller\n");
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return;
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}
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pinmux_pin_get(iomuxgpr_dev, offset, &value);
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if (dir) {
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if (dir) {
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/* enable MCLK output */
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*gpr |= mask;
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value |= mask;
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} else {
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} else {
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/* disable MCLK output */
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*gpr &= ~mask;
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value &= ~mask;
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}
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}
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pinmux_pin_set(iomuxgpr_dev, offset, value);
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}
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}
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static void get_mclk_rate(const struct device *dev, uint32_t *mclk)
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static void get_mclk_rate(const struct device *dev, uint32_t *mclk)
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@ -961,10 +950,11 @@ static void audio_clock_settings(const struct device *dev)
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{
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{
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clock_audio_pll_config_t audioPllConfig;
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clock_audio_pll_config_t audioPllConfig;
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const struct i2s_mcux_config *dev_cfg = dev->config;
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const struct i2s_mcux_config *dev_cfg = dev->config;
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uint32_t clock_name = (uint32_t) dev_cfg->clk_sub_sys;
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/*Clock setting for SAI*/
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/*Clock setting for SAI*/
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#if CONFIG_CLOCK_CONTROL_MCUX_CCM_REV2
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#if CONFIG_CLOCK_CONTROL_MCUX_CCM_REV2
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switch (dev_cfg->clk_sub_sys) {
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switch (clock_name) {
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case IMX_CCM_SAI1_CLK:
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case IMX_CCM_SAI1_CLK:
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CLOCK_SetRootClockMux(kCLOCK_Root_Sai1, dev_cfg->clk_src);
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CLOCK_SetRootClockMux(kCLOCK_Root_Sai1, dev_cfg->clk_src);
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CLOCK_SetRootClockDiv(kCLOCK_Root_Sai1, dev_cfg->clk_src_div);
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CLOCK_SetRootClockDiv(kCLOCK_Root_Sai1, dev_cfg->clk_src_div);
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@ -988,7 +978,7 @@ static void audio_clock_settings(const struct device *dev)
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#endif
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#endif
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#if CONFIG_CLOCK_CONTROL_MCUX_CCM
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#if CONFIG_CLOCK_CONTROL_MCUX_CCM
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switch (dev_cfg->clk_sub_sys) {
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switch (clock_name) {
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case IMX_CCM_SAI1_CLK:
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case IMX_CCM_SAI1_CLK:
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CLOCK_SetMux(kCLOCK_Sai1Mux, dev_cfg->clk_src);
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CLOCK_SetMux(kCLOCK_Sai1Mux, dev_cfg->clk_src);
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CLOCK_SetDiv(kCLOCK_Sai1PreDiv, dev_cfg->clk_pre_div);
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CLOCK_SetDiv(kCLOCK_Sai1PreDiv, dev_cfg->clk_pre_div);
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@ -1097,29 +1087,35 @@ static const struct i2s_driver_api i2s_mcux_driver_api = {
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\
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\
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static const struct i2s_mcux_config i2s_##i2s_id##_config = { \
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static const struct i2s_mcux_config i2s_##i2s_id##_config = { \
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.base = (I2S_Type *)DT_INST_REG_ADDR(i2s_id), \
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.base = (I2S_Type *)DT_INST_REG_ADDR(i2s_id), \
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.clk_src = DT_INST_CLOCKS_CELL_BY_IDX(i2s_id, 0, bits), \
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.clk_src = \
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.clk_pre_div = DT_INST_PROP(i2s_id, pre_div); \
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DT_CLOCKS_CELL_BY_IDX(DT_DRV_INST(i2s_id), \
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.clk_src_div = DT_INST_PROP(i2s_id, podf); \
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0, bits), \
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.pll_src = DT_INST_PHA_BY_NAME(i2s_id, pll_clocks, src, \
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.clk_pre_div = DT_INST_PROP(i2s_id, pre_div), \
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value), \
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.clk_src_div = DT_INST_PROP(i2s_id, podf), \
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.pll_lp = DT_INST_PHA_BY_NAME(i2s_id, pll_clocks, lp, \
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.pll_src = \
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value), \
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DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), \
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.pll_pd = DT_INST_PHA_BY_NAME(i2s_id, pll_clocks, pd, \
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pll_clocks, src, value), \
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value), \
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.pll_lp = \
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.pll_num = DT_INST_PHA_BY_NAME(i2s_id, pll_clocks, num, \
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DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), \
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value), \
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pll_clocks, lp, value), \
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.pll_den = DT_INST_PHA_BY_NAME(i2s_id, pll_clocks, den, \
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.pll_pd = \
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value), \
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DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), \
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.mclk_pin_mask = DT_INST_PHA_BY_IDX(i2s_id, pinmuxes, \
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pll_clocks, pd, value), \
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0, function), \
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.pll_num = \
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.mclk_pin_offset = DT_INST_PHA_BY_IDX(i2s_id, pinmuxs, \
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DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), \
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0, pin), \
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pll_clocks, num, value), \
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.pll_den = \
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DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), \
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pll_clocks, den, value), \
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.mclk_pin_mask = \
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DT_PHA_BY_IDX(DT_DRV_INST(i2s_id), \
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pinmuxes, 0, function), \
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.mclk_pin_offset = \
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DT_PHA_BY_IDX(DT_DRV_INST(i2s_id), \
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pinmuxes, 0, pin), \
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.clk_sub_sys = (clock_control_subsys_t) \
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.clk_sub_sys = (clock_control_subsys_t) \
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DT_INST_CLOCKS_CELL_BY_IDX(i2s_id, 0, name), \
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DT_INST_CLOCKS_CELL_BY_IDX(i2s_id, 0, name), \
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.ccm_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(i2s_id)), \
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.ccm_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(i2s_id)), \
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.pinmux_dev = DEVICE_DT_GET( \
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DT_INST_PHANDLE_BY_IDX(i2s_id, pinmuxes,\
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0)), \
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.irq_connect = i2s_irq_connect_##i2s_id, \
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.irq_connect = i2s_irq_connect_##i2s_id, \
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.tx_sync_mode = \
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.tx_sync_mode = \
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DT_INST_PROP(i2s_id, nxp_tx_sync_mode), \
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DT_INST_PROP(i2s_id, nxp_tx_sync_mode), \
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