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drivers: udc_dwc2: Add DMA register bit defines

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Add register bit defines for registers needed for DMA operation.

Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
This commit is contained in:
Tomasz Moń 2024-05-31 14:50:41 +02:00 • committed by Anas Nashif
commit 2c9371ea45
1 changed files with 116 additions and 0 deletions
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116
drivers/usb/common/usb_dwc2_hw.h
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@ -147,11 +147,45 @@ BUILD_ASSERT(sizeof(struct usb_dwc2_reg) == 0x0D00);
/* AHB configuration register */
#define USB_DWC2_GAHBCFG 0x0008UL
#define USB_DWC2_GAHBCFG_LOA_EOP_WORD_POS 27UL
#define USB_DWC2_GAHBCFG_LOA_EOP_WORD_MASK (0x3UL << USB_DWC2_GAHBCFG_LOA_EOP_WORD_POS)
#define USB_DWC2_GAHBCFG_LOA_EOP_WORD_ONE 1
#define USB_DWC2_GAHBCFG_LOA_EOP_WORD_TWO 2
#define USB_DWC2_GAHBCFG_LOA_EOP_BYTE_POS 25UL
#define USB_DWC2_GAHBCFG_LOA_EOP_BYTE_MASK (0x3UL << USB_DWC2_GAHBCFG_LOA_EOP_BYTE_POS)
#define USB_DWC2_GAHBCFG_LOA_EOP_BYTE_ONE 1
#define USB_DWC2_GAHBCFG_LOA_EOP_BYTE_TWO 2
#define USB_DWC2_GAHBCFG_INVDESCENDIANESS_POS 24UL
#define USB_DWC2_GAHBCFG_INVDESCENDIANESS BIT(USB_DWC2_GAHBCFG_INVDESCENDIANESS_POS)
#define USB_DWC2_GAHBCFG_AHBSINGLE_POS 23UL
#define USB_DWC2_GAHBCFG_AHBSINGLE BIT(USB_DWC2_GAHBCFG_AHBSINGLE_POS)
#define USB_DWC2_GAHBCFG_NOTIALLDMAWRIT_POS 22UL
#define USB_DWC2_GAHBCFG_NOTIALLDMAWRIT BIT(USB_DWC2_GAHBCFG_NOTIALLDMAWRIT_POS)
#define USB_DWC2_GAHBCFG_REMMEMSUPP_POS 21UL
#define USB_DWC2_GAHBCFG_REMMEMSUPP BIT(USB_DWC2_GAHBCFG_REMMEMSUPP_POS)
#define USB_DWC2_GAHBCFG_PTXFEMPLVL_POS 8UL
#define USB_DWC2_GAHBCFG_PTXFEMPLVL BIT(USB_DWC2_GAHBCFG_PTXFEMPLVL_POS)
#define USB_DWC2_GAHBCFG_NPTXFEMPLVL_POS 7UL
#define USB_DWC2_GAHBCFG_NPTXFEMPLVL BIT(USB_DWC2_GAHBCFG_NPTXFEMPLVL_POS)
#define USB_DWC2_GAHBCFG_DMAEN_POS 5UL
#define USB_DWC2_GAHBCFG_DMAEN BIT(USB_DWC2_GAHBCFG_DMAEN_POS)
#define USB_DWC2_GAHBCFG_HBSTLEN_POS 1UL
#define USB_DWC2_GAHBCFG_HBSTLEN_MASK (0xFUL << USB_DWC2_GAHBCFG_HBSTLEN_POS)
#define USB_DWC2_GAHBCFG_HBSTLEN_SINGLE 0
#define USB_DWC2_GAHBCFG_HBSTLEN_INCR 1
#define USB_DWC2_GAHBCFG_HBSTLEN_INCR4 3
#define USB_DWC2_GAHBCFG_HBSTLEN_INCR8 5
#define USB_DWC2_GAHBCFG_HBSTLEN_INCR16 7
#define USB_DWC2_GAHBCFG_GLBINTRMASK_POS 0UL
#define USB_DWC2_GAHBCFG_GLBINTRMASK BIT(USB_DWC2_GAHBCFG_GLBINTRMASK_POS)
USB_DWC2_SET_FIELD_DEFINE(gahbcfg_loa_eop_word, GAHBCFG_LOA_EOP_WORD)
USB_DWC2_SET_FIELD_DEFINE(gahbcfg_loa_eop_byte, GAHBCFG_LOA_EOP_BYTE)
USB_DWC2_SET_FIELD_DEFINE(gahbcfg_hbstlen, GAHBCFG_HBSTLEN)
USB_DWC2_GET_FIELD_DEFINE(gahbcfg_loa_eop_word, GAHBCFG_LOA_EOP_WORD)
USB_DWC2_GET_FIELD_DEFINE(gahbcfg_loa_eop_byte, GAHBCFG_LOA_EOP_BYTE)
USB_DWC2_GET_FIELD_DEFINE(gahbcfg_hbstlen, GAHBCFG_HBSTLEN)
/* USB configuration register */
#define USB_DWC2_GUSBCFG 0x000CUL
#define USB_DWC2_GUSBCFG_FORCEDEVMODE_POS 30UL
@ -411,6 +445,18 @@ USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_numctleps, GHWCFG4_NUMCTLEPS)
USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_phydatawidth, GHWCFG4_PHYDATAWIDTH)
USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_numdevperioeps, GHWCFG4_NUMDEVPERIOEPS)
/* GDFIFOCFG register */
#define USB_DWC2_GDFIFOCFG 0x005CUL
#define USB_DWC2_GDFIFOCFG_EPINFOBASEADDR_POS 16UL
#define USB_DWC2_GDFIFOCFG_EPINFOBASEADDR_MASK (0xFFFFUL << USB_DWC2_GDFIFOCFG_EPINFOBASEADDR_POS)
#define USB_DWC2_GDFIFOCFG_GDFIFOCFG_POS 0UL
#define USB_DWC2_GDFIFOCFG_GDFIFOCFG_MASK (0xFFFFUL << USB_DWC2_GDFIFOCFG_GDFIFOCFG_POS)
USB_DWC2_GET_FIELD_DEFINE(gdfifocfg_epinfobaseaddr, GDFIFOCFG_EPINFOBASEADDR)
USB_DWC2_GET_FIELD_DEFINE(gdfifocfg_gdfifocfg, GDFIFOCFG_GDFIFOCFG)
USB_DWC2_SET_FIELD_DEFINE(gdfifocfg_epinfobaseaddr, GDFIFOCFG_EPINFOBASEADDR)
USB_DWC2_SET_FIELD_DEFINE(gdfifocfg_gdfifocfg, GDFIFOCFG_GDFIFOCFG)
/* Device IN endpoint transmit FIFO size register */
#define USB_DWC2_DIEPTXF1 0x0104UL
#define USB_DWC2_DIEPTXF_INEPNTXFDEP_POS 16UL
@ -425,8 +471,38 @@ USB_DWC2_SET_FIELD_DEFINE(dieptxf_inepntxfstaddr, DIEPTXF_INEPNTXFSTADDR)
/* Device configuration registers */
#define USB_DWC2_DCFG 0x0800UL
#define USB_DWC2_DCFG_RESVALID_POS 26UL
#define USB_DWC2_DCFG_RESVALID_MASK (0x3FUL << USB_DWC2_DCFG_RESVALID_POS)
#define USB_DWC2_DCFG_PERSCHINTVL_POS 24UL
#define USB_DWC2_DCFG_PERSCHINTVL_MASK (0x3UL << USB_DWC2_DCFG_PERSCHINTVL_POS)
#define USB_DWC2_DCFG_PERSCHINTVL_MF25 0
#define USB_DWC2_DCFG_PERSCHINTVL_MF50 1
#define USB_DWC2_DCFG_PERSCHINTVL_MF75 2
#define USB_DWC2_DCFG_PERSCHINTVL_RESERVED 3
#define USB_DWC2_DCFG_DESCDMA_POS 23UL
#define USB_DWC2_DCFG_DESCDMA BIT(USB_DWC2_DCFG_DESCDMA_POS)
#define USB_DWC2_DCFG_EPMISCNT_POS 18UL
#define USB_DWC2_DCFG_EPMISCNT_MASK (0x1FUL << USB_DWC2_DCFG_EPMISCNT_POS)
#define USB_DWC2_DCFG_IPGISOCSUPT_POS 17UL
#define USB_DWC2_DCFG_IPGISOCSUPT BIT(USB_DWC2_DCFG_IPGISOCSUPT_POS)
#define USB_DWC2_DCFG_ERRATICINTMSK_POS 15UL
#define USB_DWC2_DCFG_ERRATICINTMSK BIT(USB_DWC2_DCFG_ERRATICINTMSK_POS)
#define USB_DWC2_DCFG_XCVRDLY_POS 14UL
#define USB_DWC2_DCFG_XCVRDLY BIT(USB_DWC2_DCFG_XCVRDLY_POS)
#define USB_DWC2_DCFG_ENDEVOUTNAK_POS 13UL
#define USB_DWC2_DCFG_ENDEVOUTNAK BIT(USB_DWC2_DCFG_ENDEVOUTNAK_POS)
#define USB_DWC2_DCFG_PERFRINT_POS 11UL
#define USB_DWC2_DCFG_PERFRINT_MASK (0x3UL << USB_DWC2_DCFG_PERFRINT_POS)
#define USB_DWC2_DCFG_PERFRINT_EOPF80 0
#define USB_DWC2_DCFG_PERFRINT_EOPF85 1
#define USB_DWC2_DCFG_PERFRINT_EOPF90 2
#define USB_DWC2_DCFG_PERFRINT_EOPF95 3
#define USB_DWC2_DCFG_DEVADDR_POS 4UL
#define USB_DWC2_DCFG_DEVADDR_MASK (0x7FUL << USB_DWC2_DCFG_DEVADDR_POS)
#define USB_DWC2_DCFG_ENA32KHZSUSP_POS 3UL
#define USB_DWC2_DCFG_ENA32KHZSUSP BIT(USB_DWC2_DCFG_ENA32KHZSUSP_POS)
#define USB_DWC2_DCFG_NZSTSOUTHSHK_POS 2UL
#define USB_DWC2_DCFG_NZSTSOUTHSHK BIT(USB_DWC2_DCFG_NZSTSOUTHSHK_POS)
#define USB_DWC2_DCFG_DEVSPD_POS 0UL
#define USB_DWC2_DCFG_DEVSPD_MASK (0x03UL << USB_DWC2_DCFG_DEVSPD_POS)
#define USB_DWC2_DCFG_DEVSPD_USBHS20 0
@ -434,7 +510,17 @@ USB_DWC2_SET_FIELD_DEFINE(dieptxf_inepntxfstaddr, DIEPTXF_INEPNTXFSTADDR)
#define USB_DWC2_DCFG_DEVSPD_USBLS116 2
#define USB_DWC2_DCFG_DEVSPD_USBFS1148 3
USB_DWC2_SET_FIELD_DEFINE(dcfg_resvalid, DCFG_RESVALID)
USB_DWC2_SET_FIELD_DEFINE(dcfg_perschintvl, DCFG_PERSCHINTVL)
USB_DWC2_SET_FIELD_DEFINE(dcfg_epmiscnt, DCFG_EPMISCNT)
USB_DWC2_SET_FIELD_DEFINE(dcfg_perfrint, DCFG_PERFRINT)
USB_DWC2_SET_FIELD_DEFINE(dcfg_devaddr, DCFG_DEVADDR)
USB_DWC2_SET_FIELD_DEFINE(dcfg_devspd, DCFG_DEVSPD)
USB_DWC2_GET_FIELD_DEFINE(dcfg_resvalid, DCFG_RESVALID)
USB_DWC2_GET_FIELD_DEFINE(dcfg_perschintvl, DCFG_PERSCHINTVL)
USB_DWC2_GET_FIELD_DEFINE(dcfg_epmiscnt, DCFG_EPMISCNT)
USB_DWC2_GET_FIELD_DEFINE(dcfg_perfrint, DCFG_PERFRINT)
USB_DWC2_GET_FIELD_DEFINE(dcfg_devaddr, DCFG_DEVADDR)
USB_DWC2_GET_FIELD_DEFINE(dcfg_devspd, DCFG_DEVSPD)
/* Device control register */
@ -494,6 +580,34 @@ USB_DWC2_GET_FIELD_DEFINE(dsts_enumspd, DSTS_ENUMSPD)
#define USB_DWC2_DAINT_OUTEPINT(ep_num) BIT(16UL + ep_num)
#define USB_DWC2_DAINT_INEPINT(ep_num) BIT(ep_num)
/* Device threshold control register */
#define USB_DWC2_DTHRCTL 0x0830UL
#define USB_DWC2_DTHRCTL_ARBPRKEN_POS 27UL
#define USB_DWC2_DTHRCTL_ARBPRKEN BIT(USB_DWC2_DTHRCTL_ARBPRKEN_POS)
#define USB_DWC2_DTHRCTL_RXTHRLEN_POS 17UL
#define USB_DWC2_DTHRCTL_RXTHRLEN_MASK (0x1FFUL << USB_DWC2_DTHRCTL_RXTHRLEN_POS)
#define USB_DWC2_DTHRCTL_RXTHREN_POS 16UL
#define USB_DWC2_DTHRCTL_RXTHREN BIT(USB_DWC2_DTHRCTL_RXTHREN_POS)
#define USB_DWC2_DTHRCTL_AHBTHRRATIO_POS 11UL
#define USB_DWC2_DTHRCTL_AHBTHRRATIO_MASK (0x3UL << USB_DWC2_DTHRCTL_AHBTHRRATIO_POS)
#define USB_DWC2_DTHRCTL_AHBTHRRATIO_THRESZERO 0
#define USB_DWC2_DTHRCTL_AHBTHRRATIO_THRESONE 1
#define USB_DWC2_DTHRCTL_AHBTHRRATIO_THRESTWO 2
#define USB_DWC2_DTHRCTL_AHBTHRRATIO_THRESTHREE 3
#define USB_DWC2_DTHRCTL_TXTHRLEN_POS 2UL
#define USB_DWC2_DTHRCTL_TXTHRLEN_MASK (0x1FFUL << USB_DWC2_DTHRCTL_TXTHRLEN_POS)
#define USB_DWC2_DTHRCTL_ISOTHREN_POS 1UL
#define USB_DWC2_DTHRCTL_ISOTHREN BIT(USB_DWC2_DTHRCTL_ISOTHREN_POS)
#define USB_DWC2_DTHRCTL_NONISOTHREN_POS 0UL
#define USB_DWC2_DTHRCTL_NONISOTHREN BIT(USB_DWC2_DTHRCTL_NONISOTHREN_POS)
USB_DWC2_GET_FIELD_DEFINE(dthrctl_rxthrlen, DTHRCTL_RXTHRLEN)
USB_DWC2_GET_FIELD_DEFINE(dthrctl_ahbthrratio, DTHRCTL_AHBTHRRATIO)
USB_DWC2_GET_FIELD_DEFINE(dthrctl_txthrlen, DTHRCTL_TXTHRLEN)
USB_DWC2_SET_FIELD_DEFINE(dthrctl_rxthrlen, DTHRCTL_RXTHRLEN)
USB_DWC2_SET_FIELD_DEFINE(dthrctl_ahbthrratio, DTHRCTL_AHBTHRRATIO)
USB_DWC2_SET_FIELD_DEFINE(dthrctl_txthrlen, DTHRCTL_TXTHRLEN)
/*
* Device IN/OUT endpoint control register
* IN endpoint offsets 0x0900 + (0x20 * n), n = 0 .. x,
@ -648,6 +762,8 @@ USB_DWC2_GET_FIELD_DEFINE(dieptsiz0_xfersize, DEPTSIZ0_XFERSIZE)
USB_DWC2_GET_FIELD_DEFINE(deptsizn_pktcnt, DEPTSIZN_PKTCNT)
USB_DWC2_GET_FIELD_DEFINE(deptsizn_xfersize, DEPTSIZN_XFERSIZE)
USB_DWC2_SET_FIELD_DEFINE(deptsizn_pktcnt, DEPTSIZN_PKTCNT)
USB_DWC2_SET_FIELD_DEFINE(deptsizn_xfersize, DEPTSIZN_XFERSIZE)
/*
* Device IN/OUT endpoint transfer size register