drivers: fpga controller: add fpga api

This adds new FPGA controller which allow to control FPGA chips.

FPGA controller has been created to enable bitstream loading
into the reprogrammable logic. It adds completely new API,
which enables to check status of the FPGA chip, power it on
or off and reset it.

Signed-off-by: Mateusz Sierszulski <msierszulski@internships.antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>

drivers/CMakeLists.txt

@@ -60,3 +60,4 @@ add_subdirectory_ifdef(CONFIG_EDAC             edac)
 add_subdirectory_ifdef(CONFIG_CACHE_MANAGEMENT cache)
 add_subdirectory_ifdef(CONFIG_SYSCON           syscon)
 add_subdirectory_ifdef(CONFIG_BBRAM            bbram)
+add_subdirectory_ifdef(CONFIG_FPGA             fpga)

drivers/Kconfig

@@ -121,4 +121,6 @@ source "drivers/syscon/Kconfig"
 
 source "drivers/bbram/Kconfig"
 
+source "drivers/fpga/Kconfig"
+
 endmenu

drivers/fpga/CMakeLists.txt

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()

drivers/fpga/Kconfig

@@ -0,0 +1,17 @@
+# FPGA driver configuration options
+
+# Copyright (c) 2021 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig FPGA
+	bool "FPGA Drivers"
+	help
+	  Enable support for FPGA drivers.
+
+if FPGA
+
+module = fpga
+module-str = fpga
+source "subsys/logging/Kconfig.template.log_config"
+
+endif # FPGA

include/drivers/fpga.h

@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2021 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_FPGA_H_
+#define ZEPHYR_INCLUDE_DRIVERS_FPGA_H_
+
+#include <zephyr/types.h>
+#include <sys/util.h>
+#include <device.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum FPGA_status {
+	/* Inactive is when the FPGA cannot accept the bitstream
+	 * and will not be programmed correctly
+	 */
+	FPGA_STATUS_INACTIVE,
+	/* Active is when the FPGA can accept the bitstream and
+	 * can be programmed correctly
+	 */
+	FPGA_STATUS_ACTIVE
+};
+
+typedef enum FPGA_status (*fpga_api_get_status)(const struct device *dev);
+typedef int (*fpga_api_load)(const struct device *dev, uint32_t *image_ptr,
+			     uint32_t img_size);
+typedef int (*fpga_api_reset)(const struct device *dev);
+typedef int (*fpga_api_on)(const struct device *dev);
+typedef int (*fpga_api_off)(const struct device *dev);
+typedef const char *(*fpga_api_get_info)(const struct device *dev);
+
+__subsystem struct fpga_driver_api {
+	fpga_api_get_status get_status;
+	fpga_api_reset reset;
+	fpga_api_load load;
+	fpga_api_on on;
+	fpga_api_off off;
+	fpga_api_get_info get_info;
+};
+
+/**
+ * @brief Read the status of FPGA.
+ *
+ * @param dev FPGA device structure.
+ *
+ * @retval 0 if the FPGA is in ACTIVE state.
+ * @retval 1 if the FPGA is in INACTIVE state.
+ */
+static inline enum FPGA_status fpga_get_status(const struct device *dev)
+{
+	const struct fpga_driver_api *api =
+		(const struct fpga_driver_api *)dev->api;
+
+	return api->get_status(dev);
+}
+
+/**
+ * @brief Reset the FPGA.
+ *
+ * @param dev FPGA device structure.
+ *
+ * @retval 0 if successful.
+ * @retval Failed Otherwise.
+ */
+static inline int fpga_reset(const struct device *dev)
+{
+	const struct fpga_driver_api *api =
+		(const struct fpga_driver_api *)dev->api;
+
+	return api->reset(dev);
+}
+
+/**
+ * @brief Load the bitstream and program the FPGA
+ *
+ * @param dev FPGA device structure.
+ * @param image_ptr Pointer to bitstream.
+ * @param img_size Bitstream size in bytes.
+ *
+ * @retval 0 if successful.
+ * @retval Failed Otherwise.
+ */
+static inline int fpga_load(const struct device *dev, uint32_t *image_ptr,
+			    uint32_t img_size)
+{
+	const struct fpga_driver_api *api =
+		(const struct fpga_driver_api *)dev->api;
+
+	return api->load(dev, image_ptr, img_size);
+}
+
+/**
+ * @brief Turns on the FPGA.
+ *
+ * @param dev FPGA device structure.
+ *
+ * @retval 0 if successful.
+ * @retval negative errno code on failure.
+ */
+static inline int fpga_on(const struct device *dev)
+{
+	const struct fpga_driver_api *api =
+		(const struct fpga_driver_api *)dev->api;
+
+	if (api->on == NULL) {
+		return -ENOTSUP;
+	}
+
+	return api->on(dev);
+}
+
+/**
+ * @brief Returns information about the FPGA.
+ *
+ * @param dev FPGA device structure.
+ *
+ * @return String containing information.
+ */
+static inline const char *fpga_get_info(const struct device *dev)
+{
+	const struct fpga_driver_api *api =
+		(const struct fpga_driver_api *)dev->api;
+
+	return api->get_info(dev);
+}
+
+/**
+ * @brief Turns off the FPGA.
+ *
+ * @param dev FPGA device structure.
+ *
+ * @retval 0 if successful.
+ * @retval negative errno code on failure.
+ */
+static inline int fpga_off(const struct device *dev)
+{
+	const struct fpga_driver_api *api =
+		(const struct fpga_driver_api *)dev->api;
+
+	if (api->off == NULL) {
+		return -ENOTSUP;
+	}
+
+	return api->off(dev);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_FPGA_H_ */