drivers: espi: Microchip eSPI add SAF support
Add ESPI SAF features to the Microchip eSPI driver as a separate file. ESPI SAF depends upon the core eSPI driver adding the ability to attach the system SPI flash to the EC eSPI endpoint instead of the host eSPI controller. Signed-off-by: Scott Worley <scott.worley@microchip.com>
This commit is contained in:
Scott Worley
Anas Nashif
parent
5c649921de
commit
2b926db4e1
8 changed files with 1882 additions and 4 deletions
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@ -3,7 +3,8 @@
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_ESPI_XEC espi_mchp_xec.c)
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zephyr_library_sources_ifdef(CONFIG_ESPI_NPCX espi_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_ESPI_NPCX host_subs_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE espi_handlers.c)
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zephyr_library_sources_ifdef(CONFIG_ESPI_EMUL espi_emul.c)
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zephyr_library_sources_ifdef(CONFIG_ESPI_NPCX espi_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_ESPI_NPCX host_subs_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE espi_handlers.c)
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zephyr_library_sources_ifdef(CONFIG_ESPI_EMUL espi_emul.c)
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zephyr_library_sources_ifdef(CONFIG_ESPI_SAF espi_saf_mchp_xec.c)
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@ -37,4 +37,19 @@ config ESPI_PERIPHERAL_UART_SOC_MAPPING
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This tells the driver to which SoC UART to direct the UART traffic
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send over eSPI from host.
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config ESPI_SAF
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bool "XEC Microchip ESPI SAF driver"
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depends on ESPI_FLASH_CHANNEL
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default n
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help
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Enable Slave Attached Flash eSPI driver. SAF depends upon ESPI XEC driver
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and flash channel.
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config ESPI_SAF_INIT_PRIORITY
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int "ESPI SAF driver initialization priority"
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depends on ESPI_SAF
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default 4
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help
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Driver initialization priority for eSPI SAF driver.
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endif #ESPI_XEC
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876
drivers/espi/espi_saf_mchp_xec.c
Normal file
876
drivers/espi/espi_saf_mchp_xec.c
Normal file
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@ -0,0 +1,876 @@
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/*
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* Copyright (c) 2019 Intel Corporation
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* Copyright (c) 2020 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_xec_espi_saf
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#include <kernel.h>
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#include <soc.h>
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#include <errno.h>
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#include <drivers/espi.h>
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#include <drivers/espi_saf.h>
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#include <logging/log.h>
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#include "espi_utils.h"
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LOG_MODULE_REGISTER(espi_saf, CONFIG_ESPI_LOG_LEVEL);
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/* SAF EC Portal read/write flash access limited to 1-64 bytes */
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#define MAX_SAF_ECP_BUFFER_SIZE 64ul
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/* 1 second maximum for flash operations */
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#define MAX_SAF_FLASH_TIMEOUT 125000ul /* 1000ul */
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/* 64 bytes @ 24MHz quad is approx. 6 us */
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#define SAF_WAIT_INTERVAL 8
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/* After 8 wait intervals yield */
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#define SAF_YIELD_THRESHOLD 64
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struct espi_isr {
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uint32_t girq_bit;
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void (*the_isr)(const struct device *dev);
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};
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/*
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* SAF configuration from Device Tree
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* SAF controller register block base address
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* QMSPI controller register block base address
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* SAF communications register block base address
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* Flash STATUS1 poll timeout in 32KHz periods
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* Flash consecutive read timeout in units of 20 ns
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* Delay before first Poll-1 command after suspend in 20 ns units
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* Hold off suspend for this interval if erase or program in 32KHz periods.
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* Add delay between Poll STATUS1 commands in 20 ns units.
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*/
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struct espi_saf_xec_config {
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uintptr_t saf_base_addr;
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uintptr_t qmspi_base_addr;
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uintptr_t saf_comm_base_addr;
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uint32_t poll_timeout;
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uint32_t consec_rd_timeout;
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uint32_t sus_chk_delay;
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uint16_t sus_rsm_interval;
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uint16_t poll_interval;
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};
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struct espi_saf_xec_data {
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sys_slist_t callbacks;
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struct k_sem ecp_lock;
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uint32_t hwstatus;
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};
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/* convenience defines */
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#define DEV_CFG(dev) ((const struct espi_saf_xec_config *const)(dev)->config)
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#define DEV_DATA(dev) ((struct espi_saf_xec_data *const)(dev)->data)
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/* EC portal local flash r/w buffer */
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static uint32_t slave_mem[MAX_SAF_ECP_BUFFER_SIZE];
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/*
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* @brief eSPI SAF configuration
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*/
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static inline void mchp_saf_cs_descr_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs,
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uint32_t val)
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{
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regs->SAF_CS_OP[cs].OP_DESCR = val;
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}
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static inline void mchp_saf_poll2_mask_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs,
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uint16_t val)
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{
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LOG_DBG("%s cs: %d mask %x", __func__, cs, val);
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if (cs == 0) {
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regs->SAF_CS0_CFG_P2M = val;
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} else {
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regs->SAF_CS1_CFG_P2M = val;
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}
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}
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static inline void mchp_saf_cm_prefix_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs,
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uint16_t val)
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{
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if (cs == 0) {
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regs->SAF_CS0_CM_PRF = val;
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} else {
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regs->SAF_CS1_CM_PRF = val;
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}
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}
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/* busy wait or yield until we have SAF interrupt support */
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static int xec_saf_spin_yield(int *counter)
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{
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*counter = *counter + 1;
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if (*counter > MAX_SAF_FLASH_TIMEOUT) {
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return -ETIMEDOUT;
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}
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if (*counter > SAF_YIELD_THRESHOLD) {
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k_yield();
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} else {
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k_busy_wait(SAF_WAIT_INTERVAL);
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}
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return 0;
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}
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/*
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* Initialize SAF flash protection regions.
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* SAF HW implements 17 protection regions.
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* At least one protection region must be configured to allow
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* EC access to the local flash through the EC Portal.
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* Each protection region is composed of 4 32-bit registers
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* Start bits[19:0] = bits[31:12] region start address (4KB boundaries)
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* Limit bits[19:0] = bits[31:12] region limit address (4KB boundaries)
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* Write protect b[7:0] = masters[7:0] allow write/erase. 1=allowed
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* Read protetc b[7:0] = masters[7:0] allow read. 1=allowed
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*
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* This routine configures protection region 0 for full flash array
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* address range and read-write-erase for all masters.
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* This routine must be called AFTER the flash configuration size/limit and
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* threshold registers have been programmed.
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*
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* POR default values:
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* Start = 0x7ffff
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* Limit = 0
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* Write Prot = 0x01 Master 0 always granted write/erase
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* Read Prot = 0x01 Master 0 always granted read
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*
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* Sample code configures PR[0]
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* Start = 0
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* Limit = 0x7ffff
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* WR = 0xFF
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* RD = 0xFF
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*/
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static void saf_protection_regions_init(MCHP_SAF_HW_REGS *regs)
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{
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LOG_DBG("%s", __func__);
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for (size_t n = 0; n < MCHP_ESPI_SAF_PR_MAX; n++) {
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if (n == 0) {
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regs->SAF_PROT_RG[0].START = 0U;
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regs->SAF_PROT_RG[0].LIMIT =
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regs->SAF_FL_CFG_SIZE_LIM >> 12;
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regs->SAF_PROT_RG[0].WEBM = MCHP_SAF_MSTR_ALL;
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regs->SAF_PROT_RG[0].RDBM = MCHP_SAF_MSTR_ALL;
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} else {
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regs->SAF_PROT_RG[n].START =
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MCHP_SAF_PROT_RG_START_DFLT;
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regs->SAF_PROT_RG[n].LIMIT =
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MCHP_SAF_PROT_RG_LIMIT_DFLT;
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regs->SAF_PROT_RG[n].WEBM = 0U;
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regs->SAF_PROT_RG[n].RDBM = 0U;
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}
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LOG_DBG("PROT[%d] START %x", n, regs->SAF_PROT_RG[n].START);
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LOG_DBG("PROT[%d] LIMIT %x", n, regs->SAF_PROT_RG[n].LIMIT);
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LOG_DBG("PROT[%d] WEBM %x", n, regs->SAF_PROT_RG[n].WEBM);
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LOG_DBG("PROT[%d] RDBM %x", n, regs->SAF_PROT_RG[n].RDBM);
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}
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}
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static uint32_t qmspi_freq_div(uint32_t freqhz)
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{
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uint32_t fdiv;
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if (freqhz < (MCHP_QMSPI_MIN_FREQ_KHZ * 1000U)) {
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fdiv = 0U; /* freq divider field -> 256 */
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} else if (freqhz >= (MCHP_QMSPI_MAX_FREQ_KHZ * 1000U)) {
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fdiv = 1U;
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} else {
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/* truncation produces next higher integer frequency */
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fdiv = MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ / freqhz;
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}
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fdiv &= MCHP_QMSPI_M_FDIV_MASK0;
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fdiv <<= MCHP_QMSPI_M_FDIV_POS;
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return fdiv;
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}
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/*
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* Take over and re-initialize QMSPI for use by SAF HW engine.
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* When SAF is activated, QMSPI registers are controlled by SAF
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* HW engine. CPU no longer has access to QMSPI registers.
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* 1. Save QMSPI driver frequency divider, SPI signalling mode, and
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* chip select timing.
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* 2. Put QMSPI controller in a known state by performing a soft reset.
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* 3. Clear QMSPI GIRQ status
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* 4. Configure QMSPI interface control for SAF.
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* 5. Load flash device independent (generic) descriptors.
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* 6. Enable transfer done interrupt in QMSPI
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* 7. Enable QMSPI SAF mode
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* 8. If user configuration overrides frequency, signalling mode,
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* or chip select timing derive user values.
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* 9. Program QMSPI MODE and CSTIM registers with activate set.
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*/
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static int saf_qmspi_init(const struct espi_saf_xec_config *xcfg,
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const struct espi_saf_cfg *cfg)
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{
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uint32_t qmode, cstim, n;
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QMSPI_Type *regs = (QMSPI_Type *)xcfg->qmspi_base_addr;
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const struct espi_saf_hw_cfg *hwcfg = &cfg->hwcfg;
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qmode = regs->MODE;
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if (!(qmode & MCHP_QMSPI_M_ACTIVATE)) {
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return -EAGAIN;
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}
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qmode = regs->MODE & (MCHP_QMSPI_M_FDIV_MASK | MCHP_QMSPI_M_SIG_MASK);
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cstim = regs->CSTM;
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regs->MODE = MCHP_QMSPI_M_SRST;
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regs->STS = MCHP_QMSPI_STS_RW1C_MASK;
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MCHP_GIRQ_ENCLR(MCHP_QMSPI_GIRQ_NUM) = MCHP_QMSPI_GIRQ_VAL;
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MCHP_GIRQ_SRC(MCHP_QMSPI_GIRQ_NUM) = MCHP_QMSPI_GIRQ_VAL;
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regs->IFCTRL =
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(MCHP_QMSPI_IFC_WP_OUT_HI | MCHP_QMSPI_IFC_WP_OUT_EN |
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MCHP_QMSPI_IFC_HOLD_OUT_HI | MCHP_QMSPI_IFC_HOLD_OUT_EN);
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for (n = 0; n < MCHP_SAF_NUM_GENERIC_DESCR; n++) {
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regs->DESCR[MCHP_SAF_CM_EXIT_START_DESCR + n] =
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hwcfg->generic_descr[n];
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}
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regs->IEN = MCHP_QMSPI_IEN_XFR_DONE;
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qmode |= (MCHP_QMSPI_M_SAF_DMA_MODE_EN | MCHP_QMSPI_M_CS0 |
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MCHP_QMSPI_M_ACTIVATE);
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if (hwcfg->flags & MCHP_SAF_HW_CFG_FLAG_CPHA) {
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qmode = (qmode & ~(MCHP_QMSPI_M_SIG_MASK)) |
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((hwcfg->qmspi_cpha << MCHP_QMSPI_M_SIG_POS) &
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MCHP_QMSPI_M_SIG_MASK);
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}
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if (hwcfg->flags & MCHP_SAF_HW_CFG_FLAG_FREQ) {
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qmode = (qmode & ~(MCHP_QMSPI_M_FDIV_MASK)) |
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qmspi_freq_div(hwcfg->qmspi_freq_hz);
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}
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if (hwcfg->flags & MCHP_SAF_HW_CFG_FLAG_CSTM) {
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cstim = hwcfg->qmspi_cs_timing;
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}
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regs->MODE = qmode;
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regs->CSTM = cstim;
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return 0;
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}
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/*
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* Registers at offsets:
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* SAF Poll timeout @ 0x194. Hard coded to 0x28000. Default value = 0.
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* recommended value = 0x28000 32KHz clocks (5 seconds). b[17:0]
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* SAF Poll interval @ 0x198. Hard coded to 0
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* Default value = 0. Recommended = 0. b[15:0]
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* SAF Suspend/Resume Interval @ 0x19c. Hard coded to 0x8
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* Default value = 0x01. Min time erase/prog in 32KHz units.
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* SAF Consecutive Read Timeout @ 0x1a0. Hard coded to 0x2. b[15:0]
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* Units of MCLK. Recommend < 20us. b[19:0]
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* SAF Suspend Check Delay @ 0x1ac. Not touched.
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* Default = 0. Recommend = 20us. Units = MCLK. b[19:0]
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*/
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static void saf_flash_timing_init(MCHP_SAF_HW_REGS *regs,
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const struct espi_saf_xec_config *cfg)
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{
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LOG_DBG("%s\n", __func__);
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regs->SAF_POLL_TMOUT = cfg->poll_timeout;
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regs->SAF_POLL_INTRVL = cfg->poll_interval;
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regs->SAF_SUS_RSM_INTRVL = cfg->sus_rsm_interval;
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regs->SAF_CONSEC_RD_TMOUT = cfg->consec_rd_timeout;
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regs->SAF_SUS_CHK_DLY = cfg->sus_chk_delay;
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LOG_DBG("SAF_POLL_TMOUT %x\n", regs->SAF_POLL_TMOUT);
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LOG_DBG("SAF_POLL_INTRVL %x\n", regs->SAF_POLL_INTRVL);
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LOG_DBG("SAF_SUS_RSM_INTRVL %x\n", regs->SAF_SUS_RSM_INTRVL);
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LOG_DBG("SAF_CONSEC_RD_TMOUT %x\n", regs->SAF_CONSEC_RD_TMOUT);
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LOG_DBG("SAF_SUS_CHK_DLY %x\n", regs->SAF_SUS_CHK_DLY);
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}
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/*
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* Disable DnX bypass feature.
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*/
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static void saf_dnx_bypass_init(MCHP_SAF_HW_REGS *regs)
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{
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regs->SAF_DNX_PROT_BYP = 0;
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regs->SAF_DNX_PROT_BYP = 0xffffffff;
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}
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/*
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* Bitmap of flash erase size from 1KB up to 128KB.
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* eSPI SAF specification requires 4KB erase support.
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* MCHP SAF supports 4KB, 32KB, and 64KB.
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* Only report 32KB and 64KB to Host if supported by both
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* flash devices.
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*/
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static int saf_init_erase_block_size(const struct espi_saf_cfg *cfg)
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{
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struct espi_saf_flash_cfg *fcfg = cfg->flash_cfgs;
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uint32_t opb = fcfg->opb;
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uint8_t erase_bitmap = MCHP_ESPI_SERASE_SZ_4K;
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LOG_DBG("%s\n", __func__);
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if (cfg->nflash_devices > 1) {
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fcfg++;
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opb &= fcfg->opb;
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}
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if ((opb & MCHP_SAF_CS_OPB_ER0_MASK) == 0) {
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/* One or both do not support 4KB erase! */
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return -EINVAL;
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}
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if (opb & MCHP_SAF_CS_OPB_ER1_MASK) {
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erase_bitmap |= MCHP_ESPI_SERASE_SZ_32K;
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}
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if (opb & MCHP_SAF_CS_OPB_ER2_MASK) {
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erase_bitmap |= MCHP_ESPI_SERASE_SZ_64K;
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}
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ESPI_CAP_REGS->FC_SERBZ = erase_bitmap;
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return 0;
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}
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/*
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* Set the continuous mode prefix and 4-byte address mode bits
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* based upon the flash configuration information.
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* Updates:
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* SAF Flash Config Poll2 Mask @ 0x1A4
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* SAF Flash Config Special Mode @ 0x1B0
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* SAF Flash Misc Config @ 0x38
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*/
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static void saf_flash_misc_cfg(MCHP_SAF_HW_REGS *regs, uint8_t cs,
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const struct espi_saf_flash_cfg *fcfg)
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{
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uint32_t d, v;
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d = regs->SAF_FL_CFG_MISC;
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v = MCHP_SAF_FL_CFG_MISC_CS0_CPE;
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if (cs) {
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v = MCHP_SAF_FL_CFG_MISC_CS1_CPE;
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}
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/* Does this flash device require a prefix for continuous mode? */
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if (fcfg->cont_prefix != 0) {
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d |= v;
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} else {
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d &= ~v;
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}
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v = MCHP_SAF_FL_CFG_MISC_CS0_4BM;
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if (cs) {
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v = MCHP_SAF_FL_CFG_MISC_CS1_4BM;
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}
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|
||||
/* Use 32-bit addressing for this flash device? */
|
||||
if (fcfg->flags & MCHP_FLASH_FLAG_ADDR32) {
|
||||
d |= v;
|
||||
} else {
|
||||
d &= ~v;
|
||||
}
|
||||
|
||||
regs->SAF_FL_CFG_MISC = d;
|
||||
LOG_DBG("%s SAF_FL_CFG_MISC: %x", __func__, d);
|
||||
}
|
||||
|
||||
/*
|
||||
* Program flash device specific SAF and QMSPI registers.
|
||||
*
|
||||
* CS0 OpA @ 0x4c or CS1 OpA @ 0x5C
|
||||
* CS0 OpB @ 0x50 or CS1 OpB @ 0x60
|
||||
* CS0 OpC @ 0x54 or CS1 OpC @ 0x64
|
||||
* Poll 2 Mask @ 0x1a4
|
||||
* Continuous Prefix @ 0x1b0
|
||||
* CS0: QMSPI descriptors 0-5 or CS1 QMSPI descriptors 6-11
|
||||
* CS0 Descrs @ 0x58 or CS1 Descrs @ 0x68
|
||||
*/
|
||||
static void saf_flash_cfg(const struct device *dev,
|
||||
const struct espi_saf_flash_cfg *fcfg, uint8_t cs)
|
||||
{
|
||||
uint32_t d, did;
|
||||
const struct espi_saf_xec_config *xcfg = DEV_CFG(dev);
|
||||
MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)xcfg->saf_base_addr;
|
||||
QMSPI_Type *qregs = (QMSPI_Type *)xcfg->qmspi_base_addr;
|
||||
|
||||
LOG_DBG("%s cs=%u", __func__, cs);
|
||||
|
||||
regs->SAF_CS_OP[cs].OPA = fcfg->opa;
|
||||
regs->SAF_CS_OP[cs].OPB = fcfg->opb;
|
||||
regs->SAF_CS_OP[cs].OPC = fcfg->opc;
|
||||
regs->SAF_CS_OP[cs].OP_DESCR = (uint32_t)fcfg->cs_cfg_descr_ids;
|
||||
|
||||
did = MCHP_SAF_QMSPI_CS0_START_DESCR;
|
||||
if (cs != 0) {
|
||||
did = MCHP_SAF_QMSPI_CS1_START_DESCR;
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < MCHP_SAF_QMSPI_NUM_FLASH_DESCR; i++) {
|
||||
d = fcfg->descr[i] & ~(MCHP_QMSPI_C_NEXT_DESCR_MASK);
|
||||
d |= (((did + 1) << MCHP_QMSPI_C_NEXT_DESCR_POS) &
|
||||
MCHP_QMSPI_C_NEXT_DESCR_MASK);
|
||||
qregs->DESCR[did++] = d;
|
||||
}
|
||||
|
||||
mchp_saf_poll2_mask_wr(regs, cs, fcfg->poll2_mask);
|
||||
mchp_saf_cm_prefix_wr(regs, cs, fcfg->cont_prefix);
|
||||
saf_flash_misc_cfg(regs, cs, fcfg);
|
||||
}
|
||||
|
||||
static const uint32_t tag_map_dflt[MCHP_ESPI_SAF_TAGMAP_MAX] = {
|
||||
MCHP_SAF_TAG_MAP0_DFLT, MCHP_SAF_TAG_MAP1_DFLT, MCHP_SAF_TAG_MAP2_DFLT
|
||||
};
|
||||
|
||||
static void saf_tagmap_init(MCHP_SAF_HW_REGS *regs,
|
||||
const struct espi_saf_cfg *cfg)
|
||||
{
|
||||
const struct espi_saf_hw_cfg *hwcfg = &cfg->hwcfg;
|
||||
|
||||
for (int i = 0; i < MCHP_ESPI_SAF_TAGMAP_MAX; i++) {
|
||||
if (hwcfg->tag_map[i] & MCHP_SAF_HW_CFG_TAGMAP_USE) {
|
||||
regs->SAF_TAG_MAP[i] = hwcfg->tag_map[i];
|
||||
} else {
|
||||
regs->SAF_TAG_MAP[i] = tag_map_dflt[i];
|
||||
}
|
||||
}
|
||||
|
||||
LOG_DBG("SAF TAG0 %x", regs->SAF_TAG_MAP[0]);
|
||||
LOG_DBG("SAF TAG1 %x", regs->SAF_TAG_MAP[1]);
|
||||
LOG_DBG("SAF TAG2 %x", regs->SAF_TAG_MAP[2]);
|
||||
}
|
||||
|
||||
/*
|
||||
* Configure SAF and QMSPI for SAF operation based upon the
|
||||
* number and characteristics of local SPI flash devices.
|
||||
* NOTE: SAF is configured but not activated. SAF should be
|
||||
* activated only when eSPI master sends Flash Channel enable
|
||||
* message with MAF/SAF select flag.
|
||||
*/
|
||||
static int espi_saf_xec_configuration(const struct device *dev,
|
||||
const struct espi_saf_cfg *cfg)
|
||||
{
|
||||
int ret = 0;
|
||||
uint32_t totalsz = 0;
|
||||
uint32_t u = 0;
|
||||
|
||||
LOG_DBG("%s", __func__);
|
||||
|
||||
if ((dev == NULL) || (cfg == NULL)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
const struct espi_saf_xec_config *xcfg = DEV_CFG(dev);
|
||||
MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)xcfg->saf_base_addr;
|
||||
const struct espi_saf_flash_cfg *fcfg = cfg->flash_cfgs;
|
||||
|
||||
if ((fcfg == NULL) || (cfg->nflash_devices == 0U) ||
|
||||
(cfg->nflash_devices > MCHP_SAF_MAX_FLASH_DEVICES)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) {
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
saf_qmspi_init(xcfg, cfg);
|
||||
|
||||
regs->SAF_CS0_CFG_P2M = 0;
|
||||
regs->SAF_CS1_CFG_P2M = 0;
|
||||
|
||||
regs->SAF_FL_CFG_GEN_DESCR = MCHP_SAF_FL_CFG_GEN_DESCR_STD;
|
||||
|
||||
/* flash device connected to CS0 required */
|
||||
totalsz = fcfg->flashsz;
|
||||
regs->SAF_FL_CFG_THRH = totalsz;
|
||||
saf_flash_cfg(dev, fcfg, 0);
|
||||
|
||||
/* optional second flash device connected to CS1 */
|
||||
if (cfg->nflash_devices > 1) {
|
||||
fcfg++;
|
||||
totalsz += fcfg->flashsz;
|
||||
}
|
||||
/* Program CS1 configuration (same as CS0 if only one device) */
|
||||
saf_flash_cfg(dev, fcfg, 1);
|
||||
|
||||
if (totalsz == 0) {
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
regs->SAF_FL_CFG_SIZE_LIM = totalsz - 1;
|
||||
|
||||
LOG_DBG("SAF_FL_CFG_THRH = %x SAF_FL_CFG_SIZE_LIM = %x",
|
||||
regs->SAF_FL_CFG_THRH, regs->SAF_FL_CFG_SIZE_LIM);
|
||||
|
||||
saf_tagmap_init(regs, cfg);
|
||||
|
||||
saf_protection_regions_init(regs);
|
||||
|
||||
saf_dnx_bypass_init(regs);
|
||||
|
||||
saf_flash_timing_init(regs, xcfg);
|
||||
|
||||
ret = saf_init_erase_block_size(cfg);
|
||||
if (ret != 0) {
|
||||
LOG_ERR("SAF Config bad flash erase config");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Default or expedited prefetch? */
|
||||
u = MCHP_SAF_FL_CFG_MISC_PFOE_DFLT;
|
||||
if (cfg->hwcfg.flags & MCHP_SAF_HW_CFG_FLAG_PFEXP) {
|
||||
u = MCHP_SAF_FL_CFG_MISC_PFOE_EXP;
|
||||
}
|
||||
|
||||
regs->SAF_FL_CFG_MISC =
|
||||
(regs->SAF_FL_CFG_MISC & ~(MCHP_SAF_FL_CFG_MISC_PFOE_MASK)) | u;
|
||||
|
||||
/* enable prefetch ? */
|
||||
if (cfg->hwcfg.flags & MCHP_SAF_HW_CFG_FLAG_PFEN) {
|
||||
MCHP_SAF_COMM_MODE_REG |= MCHP_SAF_COMM_MODE_PF_EN;
|
||||
} else {
|
||||
MCHP_SAF_COMM_MODE_REG &= ~(MCHP_SAF_COMM_MODE_PF_EN);
|
||||
}
|
||||
|
||||
LOG_DBG("%s SAF_FL_CFG_MISC: %x", __func__, regs->SAF_FL_CFG_MISC);
|
||||
LOG_DBG("%s Aft MCHP_SAF_COMM_MODE_REG: %x", __func__,
|
||||
MCHP_SAF_COMM_MODE_REG);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int espi_saf_xec_set_pr(const struct device *dev,
|
||||
const struct espi_saf_protection *pr)
|
||||
{
|
||||
if ((dev == NULL) || (pr == NULL)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (pr->nregions >= MCHP_ESPI_SAF_PR_MAX) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
const struct espi_saf_xec_config *xcfg = DEV_CFG(dev);
|
||||
MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)xcfg->saf_base_addr;
|
||||
|
||||
if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) {
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
const struct espi_saf_pr *preg = pr->pregions;
|
||||
size_t n = pr->nregions;
|
||||
|
||||
while (n--) {
|
||||
uint8_t regnum = preg->pr_num;
|
||||
|
||||
if (regnum >= MCHP_ESPI_SAF_PR_MAX) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* NOTE: If previously locked writes have no effect */
|
||||
if (preg->flags & MCHP_SAF_PR_FLAG_ENABLE) {
|
||||
regs->SAF_PROT_RG[regnum].START = preg->start >> 12U;
|
||||
regs->SAF_PROT_RG[regnum].LIMIT =
|
||||
(preg->start + preg->size - 1U) >> 12U;
|
||||
regs->SAF_PROT_RG[regnum].WEBM = preg->master_bm_we;
|
||||
regs->SAF_PROT_RG[regnum].RDBM = preg->master_bm_rd;
|
||||
} else {
|
||||
regs->SAF_PROT_RG[regnum].START = 0x7FFFFU;
|
||||
regs->SAF_PROT_RG[regnum].LIMIT = 0U;
|
||||
regs->SAF_PROT_RG[regnum].WEBM = 0U;
|
||||
regs->SAF_PROT_RG[regnum].RDBM = 0U;
|
||||
}
|
||||
|
||||
if (preg->flags & MCHP_SAF_PR_FLAG_LOCK) {
|
||||
regs->SAF_PROT_LOCK |= (1UL << regnum);
|
||||
}
|
||||
|
||||
preg++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool espi_saf_xec_channel_ready(const struct device *dev)
|
||||
{
|
||||
const struct espi_saf_xec_config *cfg = DEV_CFG(dev);
|
||||
MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)cfg->saf_base_addr;
|
||||
|
||||
if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) {
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/*
|
||||
* MCHP SAF hardware supports a range of flash block erase
|
||||
* sizes from 1KB to 128KB. The eSPI Host specification requires
|
||||
* 4KB must be supported. The MCHP SAF QMSPI HW interface only
|
||||
* supported three erase sizes. Most SPI flash devices chosen for
|
||||
* SAF support 4KB, 32KB, and 64KB.
|
||||
* Get flash erase sizes driver has configured from eSPI capabilities
|
||||
* registers. We assume driver flash tables have opcodes to match
|
||||
* capabilities configuration.
|
||||
* Check requested erase size is supported.
|
||||
*/
|
||||
struct erase_size_encoding {
|
||||
uint8_t hwbitpos;
|
||||
uint8_t encoding;
|
||||
};
|
||||
|
||||
static const struct erase_size_encoding ersz_enc[] = {
|
||||
{ MCHP_ESPI_SERASE_SZ_4K_BITPOS, 0 },
|
||||
{ MCHP_ESPI_SERASE_SZ_32K_BITPOS, 1 },
|
||||
{ MCHP_ESPI_SERASE_SZ_64K_BITPOS, 2 }
|
||||
};
|
||||
|
||||
#define SAF_ERASE_ENCODING_MAX_ENTRY \
|
||||
(sizeof(ersz_enc) / sizeof(struct erase_size_encoding))
|
||||
|
||||
static uint32_t get_erase_size_encoding(uint32_t erase_size)
|
||||
{
|
||||
uint8_t supsz = ESPI_CAP_REGS->FC_SERBZ;
|
||||
|
||||
LOG_DBG("%s\n", __func__);
|
||||
for (int i = 0; i < SAF_ERASE_ENCODING_MAX_ENTRY; i++) {
|
||||
uint32_t sz = MCHP_ESPI_SERASE_SZ(ersz_enc[i].hwbitpos);
|
||||
|
||||
if ((sz == erase_size) &&
|
||||
(supsz & (1 << ersz_enc[i].hwbitpos))) {
|
||||
return ersz_enc[i].encoding;
|
||||
}
|
||||
}
|
||||
|
||||
return 0xffffffffU;
|
||||
}
|
||||
|
||||
static int check_ecp_access_size(uint32_t reqlen)
|
||||
{
|
||||
if ((reqlen < MCHP_SAF_ECP_CMD_RW_LEN_MIN) ||
|
||||
(reqlen > MCHP_SAF_ECP_CMD_RW_LEN_MAX)) {
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* EC access (read/erase/write) to SAF atttached flash array
|
||||
* cmd 0 = read
|
||||
* 1 = write
|
||||
* 2 = erase
|
||||
*/
|
||||
static int saf_ecp_access(const struct device *dev,
|
||||
struct espi_saf_packet *pckt, uint8_t cmd)
|
||||
{
|
||||
uint32_t err_mask, n;
|
||||
int rc, counter;
|
||||
struct espi_saf_xec_data *xdat = DEV_DATA(dev);
|
||||
const struct espi_saf_xec_config *cfg = DEV_CFG(dev);
|
||||
MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)cfg->saf_base_addr;
|
||||
|
||||
counter = 0;
|
||||
err_mask = MCHP_SAF_ECP_STS_ERR_MASK;
|
||||
|
||||
LOG_DBG("%s", __func__);
|
||||
|
||||
if (!(regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN)) {
|
||||
LOG_ERR("SAF is disabled");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
if (regs->SAF_ECP_BUSY & MCHP_SAF_ECP_BUSY) {
|
||||
LOG_ERR("SAF EC Portal is busy");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
if ((cmd == MCHP_SAF_ECP_CMD_CTYPE_READ0) ||
|
||||
(cmd == MCHP_SAF_ECP_CMD_CTYPE_WRITE0)) {
|
||||
rc = check_ecp_access_size(pckt->len);
|
||||
if (rc) {
|
||||
LOG_ERR("SAF EC Portal size out of bounds");
|
||||
return rc;
|
||||
}
|
||||
|
||||
if (cmd == MCHP_SAF_ECP_CMD_CTYPE_WRITE0) {
|
||||
memcpy(slave_mem, pckt->buf, pckt->len);
|
||||
}
|
||||
|
||||
n = pckt->len;
|
||||
} else if (cmd == MCHP_SAF_ECP_CMD_CTYPE_ERASE0) {
|
||||
n = get_erase_size_encoding(pckt->len);
|
||||
if (n == 0xffffffff) {
|
||||
LOG_ERR("SAF EC Portal unsupported erase size");
|
||||
return -EAGAIN;
|
||||
}
|
||||
} else {
|
||||
LOG_ERR("SAF EC Portal bad cmd");
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
LOG_DBG("%s params val done", __func__);
|
||||
|
||||
k_sem_take(&xdat->ecp_lock, K_FOREVER);
|
||||
|
||||
regs->SAF_ECP_INTEN = 0;
|
||||
regs->SAF_ECP_STATUS = 0xffffffff;
|
||||
|
||||
/*
|
||||
* TODO - Force SAF Done interrupt disabled until we have support
|
||||
* from eSPI driver.
|
||||
*/
|
||||
MCHP_GIRQ_ENCLR(MCHP_SAF_GIRQ) = MCHP_SAF_GIRQ_ECP_DONE_BIT;
|
||||
MCHP_GIRQ_SRC(MCHP_SAF_GIRQ) = MCHP_SAF_GIRQ_ECP_DONE_BIT;
|
||||
|
||||
regs->SAF_ECP_FLAR = pckt->flash_addr;
|
||||
regs->SAF_ECP_BFAR = (uint32_t)&slave_mem[0];
|
||||
|
||||
regs->SAF_ECP_CMD =
|
||||
MCHP_SAF_ECP_CMD_PUT_FLASH_NP |
|
||||
((uint32_t)cmd << MCHP_SAF_ECP_CMD_CTYPE_POS) |
|
||||
((n << MCHP_SAF_ECP_CMD_LEN_POS) & MCHP_SAF_ECP_CMD_LEN_MASK);
|
||||
|
||||
/* TODO when interrupts are available enable here */
|
||||
regs->SAF_ECP_START = MCHP_SAF_ECP_START;
|
||||
|
||||
/* TODO
|
||||
* ISR is in eSPI driver. Use polling until eSPI driver has been
|
||||
* modified to provide callback for GIRQ19 SAF ECP Done.
|
||||
*/
|
||||
rc = 0;
|
||||
xdat->hwstatus = regs->SAF_ECP_STATUS;
|
||||
while (!(xdat->hwstatus & MCHP_SAF_ECP_STS_DONE)) {
|
||||
rc = xec_saf_spin_yield(&counter);
|
||||
if (rc < 0) {
|
||||
goto ecp_exit;
|
||||
}
|
||||
xdat->hwstatus = regs->SAF_ECP_STATUS;
|
||||
}
|
||||
|
||||
/* clear hardware status and check for errors */
|
||||
regs->SAF_ECP_STATUS = xdat->hwstatus;
|
||||
if (xdat->hwstatus & MCHP_SAF_ECP_STS_ERR_MASK) {
|
||||
rc = -EIO;
|
||||
goto ecp_exit;
|
||||
}
|
||||
|
||||
if (cmd == MCHP_SAF_ECP_CMD_CTYPE_READ0) {
|
||||
memcpy(pckt->buf, slave_mem, pckt->len);
|
||||
}
|
||||
|
||||
ecp_exit:
|
||||
k_sem_give(&xdat->ecp_lock);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* Flash read using SAF EC Portal */
|
||||
static int saf_xec_flash_read(const struct device *dev,
|
||||
struct espi_saf_packet *pckt)
|
||||
{
|
||||
LOG_DBG("%s", __func__);
|
||||
return saf_ecp_access(dev, pckt, MCHP_SAF_ECP_CMD_CTYPE_READ0);
|
||||
}
|
||||
|
||||
/* Flash write using SAF EC Portal */
|
||||
static int saf_xec_flash_write(const struct device *dev,
|
||||
struct espi_saf_packet *pckt)
|
||||
{
|
||||
return saf_ecp_access(dev, pckt, MCHP_SAF_ECP_CMD_CTYPE_WRITE0);
|
||||
}
|
||||
|
||||
/* Flash erase using SAF EC Portal */
|
||||
static int saf_xec_flash_erase(const struct device *dev,
|
||||
struct espi_saf_packet *pckt)
|
||||
{
|
||||
return saf_ecp_access(dev, pckt, MCHP_SAF_ECP_CMD_CTYPE_ERASE0);
|
||||
}
|
||||
|
||||
static int espi_saf_xec_manage_callback(const struct device *dev,
|
||||
struct espi_callback *callback,
|
||||
bool set)
|
||||
{
|
||||
struct espi_saf_xec_data *data = DEV_DATA(dev);
|
||||
|
||||
return espi_manage_callback(&data->callbacks, callback, set);
|
||||
}
|
||||
|
||||
static int espi_saf_xec_activate(const struct device *dev)
|
||||
{
|
||||
const struct espi_saf_xec_config *cfg;
|
||||
MCHP_SAF_HW_REGS *regs;
|
||||
|
||||
if (dev == NULL) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
cfg = DEV_CFG(dev);
|
||||
regs = (MCHP_SAF_HW_REGS *)cfg->saf_base_addr;
|
||||
|
||||
regs->SAF_FL_CFG_MISC |= MCHP_SAF_FL_CFG_MISC_SAF_EN;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int espi_saf_xec_init(const struct device *dev);
|
||||
|
||||
static const struct espi_saf_driver_api espi_saf_xec_driver_api = {
|
||||
.config = espi_saf_xec_configuration,
|
||||
.set_protection_regions = espi_saf_xec_set_pr,
|
||||
.activate = espi_saf_xec_activate,
|
||||
.get_channel_status = espi_saf_xec_channel_ready,
|
||||
.flash_read = saf_xec_flash_read,
|
||||
.flash_write = saf_xec_flash_write,
|
||||
.flash_erase = saf_xec_flash_erase,
|
||||
.manage_callback = espi_saf_xec_manage_callback,
|
||||
};
|
||||
|
||||
static struct espi_saf_xec_data espi_saf_xec_data;
|
||||
|
||||
static const struct espi_saf_xec_config espi_saf_xec_config = {
|
||||
.saf_base_addr = DT_INST_REG_ADDR_BY_IDX(0, 0),
|
||||
.qmspi_base_addr = DT_INST_REG_ADDR_BY_IDX(0, 1),
|
||||
.saf_comm_base_addr = DT_INST_REG_ADDR_BY_IDX(0, 2),
|
||||
.poll_timeout = DT_INST_PROP_OR(inst, poll_timeout,
|
||||
MCHP_SAF_FLASH_POLL_TIMEOUT),
|
||||
.consec_rd_timeout = DT_INST_PROP_OR(
|
||||
inst, consec_rd_timeout, MCHP_SAF_FLASH_CONSEC_READ_TIMEOUT),
|
||||
.sus_chk_delay = DT_INST_PROP_OR(inst, sus_chk_delay,
|
||||
MCHP_SAF_FLASH_SUS_CHK_DELAY),
|
||||
.sus_rsm_interval = DT_INST_PROP_OR(inst, sus_rsm_interval,
|
||||
MCHP_SAF_FLASH_SUS_RSM_INTERVAL),
|
||||
.poll_interval = DT_INST_PROP_OR(inst, poll_interval,
|
||||
MCHP_SAF_FLASH_POLL_INTERVAL),
|
||||
};
|
||||
|
||||
DEVICE_DT_INST_DEFINE(0, &espi_saf_xec_init, device_pm_control_nop,
|
||||
&espi_saf_xec_data, &espi_saf_xec_config, POST_KERNEL,
|
||||
CONFIG_ESPI_SAF_INIT_PRIORITY, &espi_saf_xec_driver_api);
|
||||
|
||||
static int espi_saf_xec_init(const struct device *dev)
|
||||
{
|
||||
struct espi_saf_xec_data *data = DEV_DATA(dev);
|
||||
|
||||
/* ungate SAF clocks by disabling PCR sleep enable */
|
||||
mchp_pcr_periph_slp_ctrl(PCR_ESPI_SAF, MCHP_PCR_SLEEP_DIS);
|
||||
|
||||
/* reset the SAF block */
|
||||
mchp_pcr_periph_reset(PCR_ESPI_SAF);
|
||||
|
||||
/* Configure the channels and its capabilities based on build config */
|
||||
ESPI_CAP_REGS->GLB_CAP0 |= MCHP_ESPI_GBL_CAP0_FC_SUPP;
|
||||
ESPI_CAP_REGS->FC_CAP &= ~(MCHP_ESPI_FC_CAP_SHARE_MASK);
|
||||
ESPI_CAP_REGS->FC_CAP |= MCHP_ESPI_FC_CAP_SHARE_MAF_SAF;
|
||||
|
||||
k_sem_init(&data->ecp_lock, 1, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue