intel_adsp: unify timer registers and simplify timer driver
Declare clock control in the shim header per SoC and remove ifdeffry from the driver simplifiying it and making it ready for the next platform. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif
parent
356779448c
commit
2af59e7d44
7 changed files with 58 additions and 25 deletions
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@ -42,21 +42,12 @@
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BUILD_ASSERT(MIN_DELAY < CYC_PER_TICK);
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BUILD_ASSERT(COMPARATOR_IDX >= 0 && COMPARATOR_IDX <= 1);
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
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#define WCTCS_TTIE(c) BIT(8 + (c))
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/* Basically identical register interface, very slightly different layout */
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# define WCTCS (&MTL_TTS.wctcs)
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# define COUNTER_HI (&MTL_TTS.wc.hi)
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# define COUNTER_LO (&MTL_TTS.wc.lo)
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# define COMPARE_HI (&MTL_TTS.wctc[COMPARATOR_IDX].hi)
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# define COMPARE_LO (&MTL_TTS.wctc[COMPARATOR_IDX].lo)
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#else
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# define WCTCS (&CAVS_SHIM.dspwctcs)
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# define COUNTER_HI (&CAVS_SHIM.dspwc_hi)
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# define COUNTER_LO (&CAVS_SHIM.dspwc_lo)
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# define COMPARE_HI (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, COMPARATOR_IDX), c_hi))
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# define COMPARE_LO (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, COMPARATOR_IDX), c_lo))
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#endif
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#define WCTCS (SHIM_DSPWCTS)
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#define COUNTER_HI (SHIM_DSPWCH)
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#define COUNTER_LO (SHIM_DSPWCL)
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#define COMPARE_HI (SHIM_COMPARE_HI(COMPARATOR_IDX))
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#define COMPARE_LO (SHIM_COMPARE_LO(COMPARATOR_IDX))
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static struct k_spinlock lock;
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static uint64_t last_count;
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@ -200,7 +191,7 @@ static void irq_init(void)
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*/
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
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MTL_DINT[cpu].ie[MTL_INTL_TTS] |= BIT(COMPARATOR_IDX + 1);
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*WCTCS |= WCTCS_TTIE(COMPARATOR_IDX);
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*WCTCS |= SHIM_DSPWCTCS_TTIE(COMPARATOR_IDX);
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#else
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CAVS_INTCTRL[cpu].l2.clear = CAVS_L2_DWCT0;
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#endif
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@ -70,6 +70,14 @@ struct mtl_tts {
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#define MTL_TTS (*(volatile struct mtl_tts *)DFTTS_REG)
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#define SHIM_DSPWCTS (&MTL_TTS.wctcs)
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#define SHIM_DSPWCH (&MTL_TTS.wc.hi)
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#define SHIM_DSPWCL (&MTL_TTS.wc.lo)
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#define SHIM_COMPARE_HI(idx) (&MTL_TTS.wctc[idx].hi)
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#define SHIM_COMPARE_LO(idx) (&MTL_TTS.wctc[idx].lo)
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#define SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c))
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/* Low priority interrupt indices */
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#define MTL_INTL_HIPC 0
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#define MTL_INTL_SBIPC 1
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@ -64,6 +64,8 @@ struct cavs_shim {
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uint32_t svcfg;
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uint32_t _unused9[2];
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};
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#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
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/* L2 Local Memory control (cAVS 1.8+) */
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struct cavs_l2lm {
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@ -95,7 +97,7 @@ struct cavs_win {
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#endif /* _ASMLANGUAGE */
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#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
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/* cAVS 1.8+ CLKCTL bits */
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#define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */
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@ -65,6 +65,16 @@ struct cavs_shim {
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uint32_t _unused9[2];
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};
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#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
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#define SHIM_DSPWCTS (&CAVS_SHIM.dspwctcs)
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#define SHIM_DSPWCH (&CAVS_SHIM.dspwc_hi)
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#define SHIM_DSPWCL (&CAVS_SHIM.dspwc_lo)
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#define SHIM_COMPARE_HI(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_hi))
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#define SHIM_COMPARE_LO(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_lo))
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#define SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c))
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/* L2 Local Memory control (cAVS 1.8+) */
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struct cavs_l2lm {
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uint32_t l2lmcap;
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@ -95,8 +105,6 @@ struct cavs_win {
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#endif /* _ASMLANGUAGE */
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#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
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#define CAVS_CLKCTL_RAPLLC BIT(31)
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#define CAVS_CLKCTL_RFROSCC BIT(29)
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#define CAVS_CLKCTL_HPGPDMAFDCGB BIT(28)
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@ -65,6 +65,16 @@ struct cavs_shim {
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uint32_t _unused9[2];
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};
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#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
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#define SHIM_DSPWCTS (&CAVS_SHIM.dspwctcs)
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#define SHIM_DSPWCH (&CAVS_SHIM.dspwc_hi)
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#define SHIM_DSPWCL (&CAVS_SHIM.dspwc_lo)
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#define SHIM_COMPARE_HI(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_hi))
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#define SHIM_COMPARE_LO(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_lo))
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#define SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c))
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/* L2 Local Memory control (cAVS 1.8+) */
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struct cavs_l2lm {
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uint32_t l2lmcap;
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@ -95,8 +105,6 @@ struct cavs_win {
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#endif /* _ASMLANGUAGE */
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#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
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/* cAVS 1.8+ CLKCTL bits */
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#define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */
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#define CAVS_CLKCTL_RXOSCC BIT(30) /* Request XTAL oscillator */
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@ -65,6 +65,16 @@ struct cavs_shim {
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uint32_t _unused9[2];
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};
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#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
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#define SHIM_DSPWCTS (&CAVS_SHIM.dspwctcs)
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#define SHIM_DSPWCH (&CAVS_SHIM.dspwc_hi)
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#define SHIM_DSPWCL (&CAVS_SHIM.dspwc_lo)
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#define SHIM_COMPARE_HI(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_hi))
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#define SHIM_COMPARE_LO(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_lo))
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#define SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c))
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/* L2 Local Memory control (cAVS 1.8+) */
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struct cavs_l2lm {
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uint32_t l2lmcap;
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@ -95,8 +105,6 @@ struct cavs_win {
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#endif /* _ASMLANGUAGE */
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#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
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/* cAVS 1.8+ CLKCTL bits */
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#define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */
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#define CAVS_CLKCTL_RXOSCC BIT(30) /* Request XTAL oscillator */
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@ -65,6 +65,16 @@ struct cavs_shim {
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uint32_t _unused9[2];
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};
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#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
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#define SHIM_DSPWCTS (&CAVS_SHIM.dspwctcs)
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#define SHIM_DSPWCH (&CAVS_SHIM.dspwc_hi)
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#define SHIM_DSPWCL (&CAVS_SHIM.dspwc_lo)
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#define SHIM_COMPARE_HI(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_hi))
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#define SHIM_COMPARE_LO(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_lo))
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#define SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c))
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/* L2 Local Memory control (cAVS 1.8+) */
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struct cavs_l2lm {
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uint32_t l2lmcap;
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@ -95,8 +105,6 @@ struct cavs_win {
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#endif /* _ASMLANGUAGE */
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#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
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/* cAVS 1.8+ CLKCTL bits */
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#define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */
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#define CAVS_CLKCTL_RXOSCC BIT(30) /* Request XTAL oscillator */
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