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intel_adsp: unify timer registers and simplify timer driver

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Declare clock control in the shim header per SoC and remove ifdeffry
from the driver simplifiying it and making it ready for the next
platform.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2022-07-19 10:07:23 -04:00
commit 2af59e7d44
7 changed files with 58 additions and 25 deletions
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23
drivers/timer/intel_adsp_timer.c
View file

@ -42,21 +42,12 @@
BUILD_ASSERT(MIN_DELAY < CYC_PER_TICK); BUILD_ASSERT(MIN_DELAY < CYC_PER_TICK);
BUILD_ASSERT(COMPARATOR_IDX >= 0 && COMPARATOR_IDX <= 1); BUILD_ASSERT(COMPARATOR_IDX >= 0 && COMPARATOR_IDX <= 1);
#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X #define WCTCS (SHIM_DSPWCTS)
#define WCTCS_TTIE(c) BIT(8 + (c)) #define COUNTER_HI (SHIM_DSPWCH)
/* Basically identical register interface, very slightly different layout */ #define COUNTER_LO (SHIM_DSPWCL)
# define WCTCS (&MTL_TTS.wctcs) #define COMPARE_HI (SHIM_COMPARE_HI(COMPARATOR_IDX))
# define COUNTER_HI (&MTL_TTS.wc.hi) #define COMPARE_LO (SHIM_COMPARE_LO(COMPARATOR_IDX))
# define COUNTER_LO (&MTL_TTS.wc.lo)
# define COMPARE_HI (&MTL_TTS.wctc[COMPARATOR_IDX].hi)
# define COMPARE_LO (&MTL_TTS.wctc[COMPARATOR_IDX].lo)
#else
# define WCTCS (&CAVS_SHIM.dspwctcs)
# define COUNTER_HI (&CAVS_SHIM.dspwc_hi)
# define COUNTER_LO (&CAVS_SHIM.dspwc_lo)
# define COMPARE_HI (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, COMPARATOR_IDX), c_hi))
# define COMPARE_LO (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, COMPARATOR_IDX), c_lo))
#endif
static struct k_spinlock lock; static struct k_spinlock lock;
static uint64_t last_count; static uint64_t last_count;
@ -200,7 +191,7 @@ static void irq_init(void)
*/ */
#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X #ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
MTL_DINT[cpu].ie[MTL_INTL_TTS] |= BIT(COMPARATOR_IDX + 1); MTL_DINT[cpu].ie[MTL_INTL_TTS] |= BIT(COMPARATOR_IDX + 1);
*WCTCS |= WCTCS_TTIE(COMPARATOR_IDX); *WCTCS |= SHIM_DSPWCTCS_TTIE(COMPARATOR_IDX);
#else #else
CAVS_INTCTRL[cpu].l2.clear = CAVS_L2_DWCT0; CAVS_INTCTRL[cpu].l2.clear = CAVS_L2_DWCT0;
#endif #endif

8
soc/xtensa/intel_adsp/ace_v1x/ace_v1x-regs.h
View file

@ -70,6 +70,14 @@ struct mtl_tts {
#define MTL_TTS (*(volatile struct mtl_tts *)DFTTS_REG) #define MTL_TTS (*(volatile struct mtl_tts *)DFTTS_REG)
#define SHIM_DSPWCTS (&MTL_TTS.wctcs)
#define SHIM_DSPWCH (&MTL_TTS.wc.hi)
#define SHIM_DSPWCL (&MTL_TTS.wc.lo)
#define SHIM_COMPARE_HI(idx) (&MTL_TTS.wctc[idx].hi)
#define SHIM_COMPARE_LO(idx) (&MTL_TTS.wctc[idx].lo)
#define SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c))
/* Low priority interrupt indices */ /* Low priority interrupt indices */
#define MTL_INTL_HIPC 0 #define MTL_INTL_HIPC 0
#define MTL_INTL_SBIPC 1 #define MTL_INTL_SBIPC 1

4
soc/xtensa/intel_adsp/ace_v1x/include/adsp_shim.h
View file

@ -64,6 +64,8 @@ struct cavs_shim {
uint32_t svcfg; uint32_t svcfg;
uint32_t _unused9[2]; uint32_t _unused9[2];
}; };
#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
/* L2 Local Memory control (cAVS 1.8+) */ /* L2 Local Memory control (cAVS 1.8+) */
struct cavs_l2lm { struct cavs_l2lm {
@ -95,7 +97,7 @@ struct cavs_win {
#endif /* _ASMLANGUAGE */ #endif /* _ASMLANGUAGE */
#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
/* cAVS 1.8+ CLKCTL bits */ /* cAVS 1.8+ CLKCTL bits */
#define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */ #define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */

12
soc/xtensa/intel_adsp/cavs_v15/include/adsp_shim.h
View file

@ -65,6 +65,16 @@ struct cavs_shim {
uint32_t _unused9[2]; uint32_t _unused9[2];
}; };
#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
#define SHIM_DSPWCTS (&CAVS_SHIM.dspwctcs)
#define SHIM_DSPWCH (&CAVS_SHIM.dspwc_hi)
#define SHIM_DSPWCL (&CAVS_SHIM.dspwc_lo)
#define SHIM_COMPARE_HI(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_hi))
#define SHIM_COMPARE_LO(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_lo))
#define SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c))
/* L2 Local Memory control (cAVS 1.8+) */ /* L2 Local Memory control (cAVS 1.8+) */
struct cavs_l2lm { struct cavs_l2lm {
uint32_t l2lmcap; uint32_t l2lmcap;
@ -95,8 +105,6 @@ struct cavs_win {
#endif /* _ASMLANGUAGE */ #endif /* _ASMLANGUAGE */
#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
#define CAVS_CLKCTL_RAPLLC BIT(31) #define CAVS_CLKCTL_RAPLLC BIT(31)
#define CAVS_CLKCTL_RFROSCC BIT(29) #define CAVS_CLKCTL_RFROSCC BIT(29)
#define CAVS_CLKCTL_HPGPDMAFDCGB BIT(28) #define CAVS_CLKCTL_HPGPDMAFDCGB BIT(28)

12
soc/xtensa/intel_adsp/cavs_v18/include/adsp_shim.h
View file

@ -65,6 +65,16 @@ struct cavs_shim {
uint32_t _unused9[2]; uint32_t _unused9[2];
}; };
#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
#define SHIM_DSPWCTS (&CAVS_SHIM.dspwctcs)
#define SHIM_DSPWCH (&CAVS_SHIM.dspwc_hi)
#define SHIM_DSPWCL (&CAVS_SHIM.dspwc_lo)
#define SHIM_COMPARE_HI(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_hi))
#define SHIM_COMPARE_LO(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_lo))
#define SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c))
/* L2 Local Memory control (cAVS 1.8+) */ /* L2 Local Memory control (cAVS 1.8+) */
struct cavs_l2lm { struct cavs_l2lm {
uint32_t l2lmcap; uint32_t l2lmcap;
@ -95,8 +105,6 @@ struct cavs_win {
#endif /* _ASMLANGUAGE */ #endif /* _ASMLANGUAGE */
#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
/* cAVS 1.8+ CLKCTL bits */ /* cAVS 1.8+ CLKCTL bits */
#define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */ #define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */
#define CAVS_CLKCTL_RXOSCC BIT(30) /* Request XTAL oscillator */ #define CAVS_CLKCTL_RXOSCC BIT(30) /* Request XTAL oscillator */

12
soc/xtensa/intel_adsp/cavs_v20/include/adsp_shim.h
View file

@ -65,6 +65,16 @@ struct cavs_shim {
uint32_t _unused9[2]; uint32_t _unused9[2];
}; };
#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
#define SHIM_DSPWCTS (&CAVS_SHIM.dspwctcs)
#define SHIM_DSPWCH (&CAVS_SHIM.dspwc_hi)
#define SHIM_DSPWCL (&CAVS_SHIM.dspwc_lo)
#define SHIM_COMPARE_HI(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_hi))
#define SHIM_COMPARE_LO(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_lo))
#define SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c))
/* L2 Local Memory control (cAVS 1.8+) */ /* L2 Local Memory control (cAVS 1.8+) */
struct cavs_l2lm { struct cavs_l2lm {
uint32_t l2lmcap; uint32_t l2lmcap;
@ -95,8 +105,6 @@ struct cavs_win {
#endif /* _ASMLANGUAGE */ #endif /* _ASMLANGUAGE */
#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
/* cAVS 1.8+ CLKCTL bits */ /* cAVS 1.8+ CLKCTL bits */
#define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */ #define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */
#define CAVS_CLKCTL_RXOSCC BIT(30) /* Request XTAL oscillator */ #define CAVS_CLKCTL_RXOSCC BIT(30) /* Request XTAL oscillator */

12
soc/xtensa/intel_adsp/cavs_v25/include/adsp_shim.h
View file

@ -65,6 +65,16 @@ struct cavs_shim {
uint32_t _unused9[2]; uint32_t _unused9[2];
}; };
#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
#define SHIM_DSPWCTS (&CAVS_SHIM.dspwctcs)
#define SHIM_DSPWCH (&CAVS_SHIM.dspwc_hi)
#define SHIM_DSPWCL (&CAVS_SHIM.dspwc_lo)
#define SHIM_COMPARE_HI(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_hi))
#define SHIM_COMPARE_LO(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_lo))
#define SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c))
/* L2 Local Memory control (cAVS 1.8+) */ /* L2 Local Memory control (cAVS 1.8+) */
struct cavs_l2lm { struct cavs_l2lm {
uint32_t l2lmcap; uint32_t l2lmcap;
@ -95,8 +105,6 @@ struct cavs_win {
#endif /* _ASMLANGUAGE */ #endif /* _ASMLANGUAGE */
#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
/* cAVS 1.8+ CLKCTL bits */ /* cAVS 1.8+ CLKCTL bits */
#define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */ #define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */
#define CAVS_CLKCTL_RXOSCC BIT(30) /* Request XTAL oscillator */ #define CAVS_CLKCTL_RXOSCC BIT(30) /* Request XTAL oscillator */