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Remove references to BSP from drivers/ directory

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Removes references to obsolete BSP terminology.  Where appropriate, replaces it
with platform terminology.

Change-Id: Ifb17f98bc12d3a28198810351629a109abdc18a5
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
This commit is contained in:
Peter Mitsis 2015-07-27 11:02:41 -04:00 • committed by Anas Nashif
commit 2a4a6cf578
14 changed files with 77 additions and 76 deletions
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4
drivers/interrupt_controller/i8259.c
View file

@ -103,7 +103,7 @@ unsigned int _i8259_spurious_interrupt_count =
/*
* The public interface for enabling/disabling a specific IRQ for the IA-32
* architecture is defined as follows in arch/nanokernel/Intel/arch.h
* architecture is defined as follows in include/arch/x86/arch.h
*
* extern void irq_enable (unsigned int irq);
* extern void irq_disable (unsigned int irq);
@ -269,7 +269,7 @@ static void __I8259IntEnable(
picBaseAdrs = (unsigned char *)PIC_SLAVE_BASE_ADRS;
/*
* BSPs that utilize this interrupt controller driver virtualize IRQs
* Platforms that utilize this interrupt controller driver virtualize IRQs
* as follows:
*
* - IRQ0 to IRQ7 are provided by the master i8259 PIC

29
drivers/interrupt_controller/ioapic_intr.c
View file

@ -204,9 +204,9 @@ static void _IoApicRedUpdateLo(unsigned int irq, uint32_t value,
uint32_t mask);
/*
* The functions irq_enable() and irq_disable() are implemented
* in the BSPs that incorporate this interrupt controller driver due to the
* IRQ virtualization imposed by the BSP.
* The functions irq_enable() and irq_disable() are implemented in the
* interrupt controller driver due to the IRQ virtualization imposed by
* the x86 architecture.
*/
/**
@ -228,20 +228,18 @@ void _ioapic_init(void)
#endif
/*
* The BSP must define the IOAPIC_NUM_RTES macro to indicate the number
* of redirection table entries supported by the IOAPIC on the board.
* The platform must define the IOAPIC_NUM_RTES macro to indicate the
* number of redirection table entries supported by the IOAPIC.
*
* Note: The number of actual IRQs supported by the IOAPIC can be
*determined
* at runtime by computing:
* determined at runtime by computing:
*
* ((__IoApicGet(IOAPIC_VERS) & IOAPIC_MRE_MASK) >> 16) + 1
*
* however, storing the number of IRQs supported in a nanokernel global
* However, storing the number of IRQs supported in a nanokernel global
* variable is not feasible since any references to this global variable
* from a microkernel-split image would not be able to directly access
*the
* variable; access via an indirection would be needed.
* the variable; access via an indirection would be needed.
*/
/*
@ -249,7 +247,7 @@ void _ioapic_init(void)
* actual interrupt vectors are specified during irq_connect().
*
* A future enhancement should make this initialization "table driven":
* use data provided by a BSP to specify the initial state
* use data provided by the platform to specify the initial state
*/
rteValue = IOAPIC_EDGE | IOAPIC_HIGH | IOAPIC_FIXED | IOAPIC_INT_MASK |
@ -307,9 +305,10 @@ void *_ioapic_eoi_get(unsigned int irq, /* INTIN number of interest */
/*
* The parameter to the ioApicIntEoi() routine is the vector programmed
* into the redirection table. The BSPs _SysIntVecAlloc() routine
* must invoke _IoApicIntEoiGet() after _IoApicRedVecSet() to ensure the
* redirection table contains the desired interrupt vector.
* into the redirection table. The interrupt controller's
* _SysIntVecAlloc() routine must invoke _IoApicIntEoiGet() after
* _IoApicRedVecSet() to ensure the redirection table contains the desired
* interrupt vector.
*/
*arg = (void *)(ioApicRedGetLo(irq) & IOAPIC_VEC_MASK);
@ -544,7 +543,7 @@ static void _IoApicRedUpdateLo(
#ifdef IOAPIC_MSI_REDIRECT
/*
* A BSP's board.h file is responsible for setting the IOAPIC_MSI_REDIRECT
* The platform is responsible for defining the IOAPIC_MSI_REDIRECT
* macro if the I/O APIC supports the MSI redirect capability.
*/

13
drivers/interrupt_controller/loapic_intr.c
View file

@ -70,7 +70,7 @@ between the local APICs and the IO APIC is handled through a dedicated 3-wire
APIC bus. Also, some of the architectural features of the local APIC have been
extended and/or modified in the local xAPIC.
The base address of the local APIC and IO APIC is taken from the BSP board.h.
The base address of the local APIC and IO APIC is taken from the platform.
It uses LOAPIC_BASE_ADRS and IOAPIC_BASE_ADRS.
This driver contains three routines for use. They are:
_loapic_init() initializes the Local APIC for the interrupt mode chosen.
@ -116,7 +116,6 @@ INCLUDE FILES: loapic.h
#define LOAPIC_BASE_MASK 0xfffff000 /* LO APIC Base Addr mask */
#define LOAPIC_GLOBAL_ENABLE 0x00000800 /* LO APIC Global Enable */
#define LOAPIC_BSP 0x00000100 /* LO APIC BSP */
/* Local APIC ID Register Bits */
@ -315,18 +314,16 @@ void _loapic_eoi(unsigned int irq)
*
* @brief Set the vector field in the specified RTE
*
* This routine is utilized by the BSP provided routined _SysIntVecAllocate()
* which in turn is provided to support the irq_connect() API. Once
* This routine is utilized by the interrupt controller's _SysIntVecAlloc()
* routine (which exists to support the irq_connect() API). Once
* a vector has been allocated, this routine is invoked to update the LVT
* entry associated with <irq> with the vector.
*
* @return N/A
*/
void _loapic_int_vec_set(unsigned int irq, /* IRQ number of the
interrupt */
unsigned int vector /* vector to copy
into the LVT */
void _loapic_int_vec_set(unsigned int irq, /* IRQ number of the interrupt */
unsigned int vector /* vector to copy into the LVT */
)
{
volatile int *pLvt; /* pointer to local vector table */

36
drivers/interrupt_controller/system_apic.c
View file

@ -47,15 +47,15 @@ for the atom_n28xx configuration of ia32 platform.
*
* @brief Allocate interrupt vector
*
* This BSP provided routine supports the irq_connect() API. This
* routine is required to perform the following 3 functions:
* This routine is used by the x86's irq_connect(). It performs the following
* functions:
*
* a) Allocate a vector satisfying the requested priority. The utility routine
* _IntVecAlloc() provided by the nanokernel will be used to perform the
* the allocation since the local APIC prioritizes interrupts as assumed
* by _IntVecAlloc().
* b) Return End of Interrupt (EOI) and Beginning of Interrupt (BOI) related
* information to be used when generating the interrupt stub code, and
* a) Allocates a vector satisfying the requested priority. The utility
* routine _IntVecAlloc() provided by the nanokernel will be used to
* perform the the allocation since the local APIC prioritizes interrupts
* as assumed by _IntVecAlloc().
* b) Provides End of Interrupt (EOI) and Beginning of Interrupt (BOI) related
* information to be used when generating the interrupt stub code.
* c) If an interrupt vector can be allocated, and the <irq> argument is not
* equal to NANO_SOFT_IRQ, the IOAPIC redirection table (RED) or the
* LOAPIC local vector table (LVT) will be updated with the allocated
@ -174,8 +174,8 @@ int _SysIntVecAlloc(
*
* @brief Program interrupt controller
*
* This BSP provided routine programs the appropriate interrupt controller
* with the given vector based on the given IRQ parameter.
* This routine programs the interrupt controller with the given vector
* based on the given IRQ parameter.
*
* Drivers call this routine instead of irq_connect() when interrupts are
* configured statically.
@ -210,14 +210,15 @@ void _SysIntVecProgram(unsigned int vector, /* vector number */
* @brief Enable an individual interrupt (IRQ)
*
* The public interface for enabling/disabling a specific IRQ for the IA-32
* architecture is defined as follows in include/nanokernel/x86/arch.h
* architecture is defined as follows in include/arch/x86/arch.h
*
* extern void irq_enable (unsigned int irq);
* extern void irq_disable (unsigned int irq);
*
* The irq_enable() routine is provided by the BSP due to the
* IRQ virtualization that is performed by this BSP. See the comments
* in _SysIntVecAlloc() for more information regarding IRQ virtualization.
* The irq_enable() routine is provided by the interrupt controller driver due
* to the IRQ virtualization that is performed by this platform. See the
* comments in _SysIntVecAlloc() for more information regarding IRQ
* virtualization.
*
* @return N/A
*/
@ -235,9 +236,10 @@ void irq_enable(unsigned int irq)
*
* @brief Disable an individual interrupt (IRQ)
*
* The irq_disable() routine is provided by the BSP due to the
* IRQ virtualization that is performed by this BSP. See the comments
* in _SysIntVecAlloc() for more information regarding IRQ virtualization.
* The irq_disable() routine is provided by the interrupt controller driver due
* to the IRQ virtualization that is performed by this platform. See the
* comments in _SysIntVecAlloc() for more information regarding IRQ
* virtualization.
*
* @return N/A
*/

21
drivers/interrupt_controller/system_pic.c
View file

@ -49,16 +49,17 @@ IRQ_CONNECT_STATIC(pic_slave, PIC_SLAVE_STRAY_INT_LVL, 0, _i8259_boi_slave, 0);
*
* @brief Allocate interrupt vector
*
* This BSP provided routine supports the irq_connect() API. This
* routine performs the following functions:
* This routine is used by the x86's irq_connect(). It performs the following
* functions:
*
* a) Allocates a vector satisfying the requested priority, where possible.
* When the <irq> argument is not equal to NANO_SOFT_IRQ, the vector assigned
* to the <irq> during interrupt controller initialization is returned,
* which may or may not have the desired prioritization. (Prioritization of
* such vectors is fixed by the 8259 interrupt controllers, and cannot be
* programmed on an IRQ basis; for example, IRQ0 is always the highest
* priority interrupt no matter which interrupt vector was assigned to IRQ0.)
* When the <irq> argument is not equal to NANO_SOFT_IRQ, the vector
* assigned to the <irq> during interrupt controller initialization is
* returned, which may or may not have the desired prioritization.
* (Prioritization of such vectors is fixed by the 8259 interrupt
* controllers, and cannot be programmed on an IRQ basis; for example, IRQ0
* is always the highest priority interrupt no matter which interrupt
* vector was assigned to IRQ0.)
* b) Provides End of Interrupt (EOI) and Beginning of Interrupt (BOI) related
* information to be used when generating the interrupt stub code.
*
@ -151,8 +152,8 @@ int _SysIntVecAlloc(
*
* @brief Program interrupt controller
*
* This BSP provided routine programs the appropriate interrupt controller
* with the given vector based on the given IRQ parameter.
* This routine programs the interrupt controller with the given vector
* based on the given IRQ parameter.
*
* Drivers call this routine instead of irq_connect() when interrupts are
* configured statically.

2
drivers/pci/pci.c
View file

@ -35,7 +35,7 @@ DESCRIPTION
Module implements routines for PCI bus initialization and query.
USAGE
In order to use the driver, BSP has to define:
To use the driver, the platform must define:
- Numbers of BUSes:
- PCI_BUS_NUMBERS;
- Register addresses:

4
drivers/random/rand32-timer.c
View file

@ -34,8 +34,8 @@
DESCRIPTION
This module provides a non-random implementation of sys_rand32_get(), which is
not meant to be used in a final product as a truly random number generator. It
was provided to allow testing on a BSP that does not (yet) provide a random
number generator.
was provided to allow testing on a platform that does not (yet) provide a
random number generator.
*/
#include <drivers/rand32.h>

4
drivers/random/rand32-timestamp.c
View file

@ -34,8 +34,8 @@
DESCRIPTION
This module provides a non-random implementation of sys_rand32_get(), which is
not meant to be used in a final product as a truly random number generator. It
was provided to allow testing on a BSP that does not (yet) provide a random
number generator.
was provided to allow testing on a platform that does not (yet) provide a
random number generator.
*/
#include <nanokernel.h>

4
drivers/serial/Kconfig
View file

@ -75,7 +75,7 @@ config K20_UART
help
This option enables the K20 serial driver.
This specific driver can be used for the serial hardware
available at the Freescale FRDM K64F BSP.
available at the Freescale FRDM K64F platform.
config STELLARIS_UART
bool "Stellaris serial driver"
@ -83,7 +83,7 @@ config STELLARIS_UART
help
This option enables the Stellaris serial driver.
This specific driver can be used for the serial hardware
available at the Texas Instrument LM3S6965 BSP.
available at the Texas Instrument LM3S6965 platform.
config UART_INTERRUPT_DRIVEN
bool

5
drivers/timer/arcv2_timer0.c
View file

@ -191,9 +191,10 @@ int _sys_clock_driver_init(struct device *device)
/**
*
* @brief Read the BSP timer hardware
* @brief Read the platform's timer hardware
*
* This routine returns the current time in terms of timer hardware clock cycles.
* This routine returns the current time in terms of timer hardware clock
* cycles.
*
* @return up counter of elapsed clock cycles
*/

7
drivers/timer/cortex_m_timer.c
View file

@ -648,11 +648,10 @@ int _sys_clock_driver_init(struct device *device)
/**
*
* @brief Read the BSP timer hardware
* @brief Read the platform's timer hardware
*
* This routine returns the current time in terms of timer hardware clock cycles.
* Some kernel facilities (e.g. benchmarking code) directly call timer_read()
* instead of utilizing the 'timer_read_fptr' function pointer.
* This routine returns the current time in terms of timer hardware clock
* cycles.
*
* @return up counter of elapsed clock cycles
*

14
drivers/timer/hpet.c
View file

@ -43,7 +43,7 @@ The HPET device driver makes no assumption about the initial state of the HPET,
and explicitly puts the device into a reset-like state. It also assumes that
the main up counter never wraps around to 0 during the lifetime of the system.
The BSP can configure the HPET to use level rather than the default edge
The platform can configure the HPET to use level rather than the default edge
sensitive interrupts by adding the following to board.h
#define HPET_USE_LEVEL_INTS
@ -613,10 +613,9 @@ int _sys_clock_driver_init(struct device *device)
*/
/*
* HPET timers IRQ field is 5 bits wide, and hence, can support only
* IRQ's
* up to 31. Some BSPs, however, use IRQs greater than 31. In this case
* program leaves the IRQ fields blank.
* HPET timers IRQ field is 5 bits wide, and hence, can support only IRQ's
* up to 31. Some platforms, however, use IRQs greater than 31. In this
* case program leaves the IRQ fields blank.
*/
*_HPET_TIMER0_CONFIG_CAPS =
@ -655,9 +654,10 @@ int _sys_clock_driver_init(struct device *device)
/**
*
* @brief Read the BSP timer hardware
* @brief Read the platform's timer hardware
*
* This routine returns the current time in terms of timer hardware clock cycles.
* This routine returns the current time in terms of timer hardware clock
* cycles.
*
* @return up counter of elapsed clock cycles
*

5
drivers/timer/i8253.c
View file

@ -504,9 +504,10 @@ int _sys_clock_driver_init(struct device *device)
/**
*
* @brief Read the BSP timer hardware
* @brief Read the platform's timer hardware
*
* This routine returns the current time in terms of timer hardware clock cycles.
* This routine returns the current time in terms of timer hardware clock
* cycles.
*
* @return up counter of elapsed clock cycles
*/

5
drivers/timer/loapic_timer.c
View file

@ -573,9 +573,10 @@ int _sys_clock_driver_init(struct device *device)
/**
*
* @brief Read the BSP timer hardware
* @brief Read the platform's timer hardware
*
* This routine returns the current time in terms of timer hardware clock cycles.
* This routine returns the current time in terms of timer hardware clock
* cycles.
*
* @return up counter of elapsed clock cycles
*/