michaelh/zephyr
1
0
Fork 0
Code Releases Activity

boards: esp32: add XIP support and enable bootloader build

Browse source 
Disable RTC WDT enabled (by default) by 2nd stage bootloader in ESP-IDF.
This WDT timer ensures correct hand-over and startup sequence from
bootloader to application.

Enabling bootloader caused system clock initialization to fail
when clock rate is greater then 80MHz. This also fixes
esp32 clock source code.

Signed-off-by: Mahavir Jain <mahavir@espressif.com>
This commit is contained in:
Mahavir Jain 2020-08-03 20:23:18 +05:30 • committed by Anas Nashif
commit 29f87c3a0f
11 changed files with 154 additions and 26 deletions
Download patch file Download diff file Expand all files Collapse all files

55
soc/xtensa/esp32/linker.ld
View file

@ -19,14 +19,23 @@
#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr
#define ROMABLE_REGION iram0_0_seg :iram0_0_phdr
#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr
#define FLASH_DATA_REGION drom0_0_seg :drom0_0_phdr
PROVIDE ( __stack = 0x3ffe3f20 );
/* Global symbols required for espressif hal build */
PROVIDE ( ets_printf = 0x40007d54 );
PROVIDE ( intr_matrix_set = 0x4000681c );
PROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 );
PROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );
PROVIDE ( ets_delay_us = 0x40008534 );
PROVIDE ( esp32_rom_uart_tx_one_char = 0x40009200 );
PROVIDE ( esp32_rom_uart_rx_one_char = 0x400092d0 );
PROVIDE ( esp32_rom_uart_attach = 0x40008fd0 );
PROVIDE ( esp32_rom_uart_tx_wait_idle = 0x40009278 );
PROVIDE ( esp32_rom_intr_matrix_set = 0x4000681c );
PROVIDE ( esp32_rom_intr_matrix_set = intr_matrix_set );
PROVIDE ( esp32_rom_gpio_matrix_in = 0x40009edc );
PROVIDE ( esp32_rom_gpio_matrix_out = 0x40009f0c );
PROVIDE ( esp32_rom_Cache_Flush = 0x40009a14 );
@ -34,13 +43,17 @@ PROVIDE ( esp32_rom_Cache_Read_Enable = 0x40009a84 );
PROVIDE ( esp32_rom_ets_set_appcpu_boot_addr = 0x4000689c );
PROVIDE ( esp32_rom_i2c_readReg = 0x40004148 );
PROVIDE ( esp32_rom_i2c_writeReg = 0x400041a4 );
PROVIDE ( esp32_rom_ets_printf = ets_printf );
PROVIDE ( esp32_rom_g_ticks_per_us_app = g_ticks_per_us_app );
PROVIDE ( esp32_rom_g_ticks_per_us_pro = g_ticks_per_us_app );
PROVIDE ( esp32_rom_ets_delay_us = ets_delay_us );
MEMORY
{
iram0_0_seg(RX): org = 0x40080000, len = 0x20000
iram0_2_seg(RX): org = 0x400D0018, len = 0x330000
irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20
dram0_0_seg(RW): org = 0x3FFB0000, len = 0x50000
drom0_0_seg(R): org = 0x3F400010, len = 0x800000
drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20
rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000
rtc_slow_seg(RW): org = 0x50000000, len = 0x1000
#ifdef CONFIG_GEN_ISR_TABLES
@ -50,8 +63,10 @@ MEMORY
PHDRS
{
iram0_0_phdr PT_LOAD;
drom0_0_phdr PT_LOAD;
dram0_0_phdr PT_LOAD;
iram0_0_phdr PT_LOAD;
irom0_0_phdr PT_LOAD;
}
/* Default entry point: */
@ -221,7 +236,18 @@ SECTIONS
_iram_text_start = ABSOLUTE(.);
*(.iram1 .iram1.*)
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
*(.literal .text .literal.* .text.*)
*libesp32.a:panic.*(.literal .text .literal.* .text.*)
*librtc.a:(.literal .text .literal.* .text.*)
*libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)
*libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)
*libhal.a:(.literal .text .literal.* .text.*)
*libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)
*libspi_flash.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*)
*libgcov.a:(.literal .text .literal.* .text.*)
*libnet80211.a:( .wifi0iram .wifi0iram.*)
*libpp.a:( .wifi0iram .wifi0iram.*)
*libnet80211.a:( .wifirxiram .wifirxiram.*)
*libpp.a:( .wifirxiram .wifirxiram.*)
_iram_text_end = ABSOLUTE(.);
} GROUP_LINK_IN(ROMABLE_REGION)
@ -244,7 +270,7 @@ SECTIONS
. = ALIGN(4);
} GROUP_LINK_IN(RAMABLE_REGION)
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(4))
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(16))
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
@ -276,8 +302,23 @@ SECTIONS
*(.gnu.version_d)
. = ALIGN(4); /* this table MUST be 4-byte aligned */
_rodata_end = ABSOLUTE(.);
} GROUP_LINK_IN(RAMABLE_REGION)
} GROUP_LINK_IN(FLASH_DATA_REGION)
.flash.text :
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.*)
_text_end = ABSOLUTE(.);
_etext = .;
/* Similar to _iram_start, this symbol goes here so it is
resolved by addr2line in preference to the first symbol in
the flash.text segment.
*/
_flash_cache_start = ABSOLUTE(0);
} GROUP_LINK_IN(FLASH_CODE_REGION)
/* Shared RAM */
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)