boards: esp32: add XIP support and enable bootloader build
Disable RTC WDT enabled (by default) by 2nd stage bootloader in ESP-IDF. This WDT timer ensures correct hand-over and startup sequence from bootloader to application. Enabling bootloader caused system clock initialization to fail when clock rate is greater then 80MHz. This also fixes esp32 clock source code. Signed-off-by: Mahavir Jain <mahavir@espressif.com>
This commit is contained in:
Mahavir Jain
Anas Nashif
parent
5c90612120
commit
29f87c3a0f
11 changed files with 154 additions and 26 deletions
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@ -6,3 +6,13 @@ config SOC_ESP32
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select XTENSA
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select CLOCK_CONTROL
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select CLOCK_CONTROL_ESP32
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config IDF_TARGET_ESP32
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bool "ESP32 as target board"
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default y
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depends on SOC_ESP32
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config ESPTOOLPY_FLASHFREQ_80M
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bool
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default y
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depends on SOC_ESP32
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@ -19,14 +19,23 @@
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#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr
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#define ROMABLE_REGION iram0_0_seg :iram0_0_phdr
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#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr
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#define FLASH_DATA_REGION drom0_0_seg :drom0_0_phdr
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PROVIDE ( __stack = 0x3ffe3f20 );
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/* Global symbols required for espressif hal build */
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PROVIDE ( ets_printf = 0x40007d54 );
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PROVIDE ( intr_matrix_set = 0x4000681c );
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PROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 );
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PROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );
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PROVIDE ( ets_delay_us = 0x40008534 );
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PROVIDE ( esp32_rom_uart_tx_one_char = 0x40009200 );
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PROVIDE ( esp32_rom_uart_rx_one_char = 0x400092d0 );
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PROVIDE ( esp32_rom_uart_attach = 0x40008fd0 );
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PROVIDE ( esp32_rom_uart_tx_wait_idle = 0x40009278 );
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PROVIDE ( esp32_rom_intr_matrix_set = 0x4000681c );
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PROVIDE ( esp32_rom_intr_matrix_set = intr_matrix_set );
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PROVIDE ( esp32_rom_gpio_matrix_in = 0x40009edc );
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PROVIDE ( esp32_rom_gpio_matrix_out = 0x40009f0c );
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PROVIDE ( esp32_rom_Cache_Flush = 0x40009a14 );
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@ -34,13 +43,17 @@ PROVIDE ( esp32_rom_Cache_Read_Enable = 0x40009a84 );
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PROVIDE ( esp32_rom_ets_set_appcpu_boot_addr = 0x4000689c );
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PROVIDE ( esp32_rom_i2c_readReg = 0x40004148 );
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PROVIDE ( esp32_rom_i2c_writeReg = 0x400041a4 );
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PROVIDE ( esp32_rom_ets_printf = ets_printf );
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PROVIDE ( esp32_rom_g_ticks_per_us_app = g_ticks_per_us_app );
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PROVIDE ( esp32_rom_g_ticks_per_us_pro = g_ticks_per_us_app );
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PROVIDE ( esp32_rom_ets_delay_us = ets_delay_us );
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MEMORY
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{
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iram0_0_seg(RX): org = 0x40080000, len = 0x20000
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iram0_2_seg(RX): org = 0x400D0018, len = 0x330000
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irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20
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dram0_0_seg(RW): org = 0x3FFB0000, len = 0x50000
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drom0_0_seg(R): org = 0x3F400010, len = 0x800000
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drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20
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rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000
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rtc_slow_seg(RW): org = 0x50000000, len = 0x1000
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#ifdef CONFIG_GEN_ISR_TABLES
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@ -50,8 +63,10 @@ MEMORY
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PHDRS
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{
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iram0_0_phdr PT_LOAD;
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drom0_0_phdr PT_LOAD;
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dram0_0_phdr PT_LOAD;
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iram0_0_phdr PT_LOAD;
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irom0_0_phdr PT_LOAD;
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}
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/* Default entry point: */
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@ -221,7 +236,18 @@ SECTIONS
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_iram_text_start = ABSOLUTE(.);
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*(.iram1 .iram1.*)
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*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
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*(.literal .text .literal.* .text.*)
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*libesp32.a:panic.*(.literal .text .literal.* .text.*)
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*librtc.a:(.literal .text .literal.* .text.*)
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*libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)
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*libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)
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*libhal.a:(.literal .text .literal.* .text.*)
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*libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)
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*libspi_flash.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*)
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*libgcov.a:(.literal .text .literal.* .text.*)
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*libnet80211.a:( .wifi0iram .wifi0iram.*)
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*libpp.a:( .wifi0iram .wifi0iram.*)
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*libnet80211.a:( .wifirxiram .wifirxiram.*)
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*libpp.a:( .wifirxiram .wifirxiram.*)
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_iram_text_end = ABSOLUTE(.);
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} GROUP_LINK_IN(ROMABLE_REGION)
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@ -244,7 +270,7 @@ SECTIONS
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. = ALIGN(4);
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} GROUP_LINK_IN(RAMABLE_REGION)
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SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(4))
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SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(16))
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{
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_rodata_start = ABSOLUTE(.);
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*(.rodata)
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@ -276,8 +302,23 @@ SECTIONS
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*(.gnu.version_d)
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. = ALIGN(4); /* this table MUST be 4-byte aligned */
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_rodata_end = ABSOLUTE(.);
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} GROUP_LINK_IN(RAMABLE_REGION)
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} GROUP_LINK_IN(FLASH_DATA_REGION)
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.flash.text :
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{
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_stext = .;
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_text_start = ABSOLUTE(.);
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*(.literal .text .literal.* .text.*)
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_text_end = ABSOLUTE(.);
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_etext = .;
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/* Similar to _iram_start, this symbol goes here so it is
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resolved by addr2line in preference to the first symbol in
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the flash.text segment.
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*/
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_flash_cache_start = ABSOLUTE(0);
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} GROUP_LINK_IN(FLASH_CODE_REGION)
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/* Shared RAM */
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SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
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@ -25,8 +25,8 @@ extern void z_cstart(void);
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*/
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void __attribute__((section(".iram1"))) __start(void)
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{
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volatile uint32_t *wdt_rtc_protect = (uint32_t *)RTC_CNTL_WDTWPROTECT_REG;
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volatile uint32_t *wdt_rtc_reg = (uint32_t *)RTC_CNTL_WDTCONFIG0_REG;
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volatile uint32_t *wdt_timg_reg = (uint32_t *)TIMG_WDTCONFIG0_REG(0);
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volatile uint32_t *app_cpu_config_reg = (uint32_t *)DPORT_APPCPU_CTRL_B_REG;
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extern uint32_t _init_start;
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extern uint32_t _bss_start;
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@ -47,11 +47,22 @@ void __attribute__((section(".iram1"))) __start(void)
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: "g"(&_bss_start)
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: "memory");
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/* The watchdog timer is enabled in the bootloader. We're done booting,
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* so disable it.
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#if !CONFIG_BOOTLOADER_ESP_IDF
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/* The watchdog timer is enabled in the 1st stage (ROM) bootloader.
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* We're done booting, so disable it.
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* If 2nd stage bootloader from IDF is enabled, then that will take
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* care of this.
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*/
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volatile uint32_t *wdt_timg_protect = (uint32_t *)TIMG_WDTWPROTECT_REG(0);
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volatile uint32_t *wdt_timg_reg = (uint32_t *)TIMG_WDTCONFIG0_REG(0);
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*wdt_rtc_protect = RTC_CNTL_WDT_WKEY_VALUE;
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*wdt_rtc_reg &= ~RTC_CNTL_WDT_FLASHBOOT_MOD_EN;
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*wdt_rtc_protect = 0;
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*wdt_timg_protect = TIMG_WDT_WKEY_VALUE;
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*wdt_timg_reg &= ~TIMG_WDT_FLASHBOOT_MOD_EN;
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*wdt_timg_protect = 0;
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#endif
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/* Disable normal interrupts. */
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__asm__ __volatile__ (
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@ -68,6 +79,15 @@ void __attribute__((section(".iram1"))) __start(void)
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*/
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__asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0]));
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#if CONFIG_BOOTLOADER_ESP_IDF
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/* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence
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* related issues in application. Hence disable that as we are about to start
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* Zephyr environment.
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*/
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*wdt_rtc_protect = RTC_CNTL_WDT_WKEY_VALUE;
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*wdt_rtc_reg &= ~RTC_CNTL_WDT_EN;
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*wdt_rtc_protect = 0;
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#endif
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/* Start Zephyr */
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z_cstart();
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@ -8,7 +8,7 @@
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#define __SOC_H__
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#include <soc/dport_reg.h>
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#include <soc/rtc_cntl_reg.h>
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#include <rom/ets_sys.h>
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#include <esp32/rom/ets_sys.h>
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#include <zephyr/types.h>
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#include <stdbool.h>
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@ -24,9 +24,7 @@ static inline void esp32_clear_mask32(uint32_t v, uint32_t mem_addr)
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sys_write32(sys_read32(mem_addr) & ~v, mem_addr);
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}
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extern int esp32_rom_intr_matrix_set(int cpu_no,
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int interrupt_src,
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int interrupt_line);
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extern void esp32_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
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extern int esp32_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index,
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bool inverted);
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