cleanup: soc: it8xxx2: remove unnecessary code
Code removed: - IT8XXX2 doesn't support soc level software interrupt hence remove them. - To use common macro to access csr (control status register). - To remove CONFIG_RISCV_HAS_PLIC related code. IT8XXX2 uses its own interrupt controller code. - To remove ite_write and ite_read. We don't use them anymore. Code changed: - Return true from arch_irq_is_enabled() when external interrupt-enable bit, and SOC's IER are both true. Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This commit is contained in:
Dino Li
Carles Cufí
parent
bcf20455ee
commit
29d039335f
5 changed files with 22 additions and 261 deletions
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@ -13,7 +13,6 @@
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#define MAX_REGISR_IRQ_NUM 8
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#define IVECT_OFFSET_WITH_IRQ 0x10
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#define SOFT_INTC_IRQ 161 /* software interrupt */
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/* Interrupt number of INTC module */
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static uint8_t intc_irq;
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@ -56,19 +55,6 @@ static volatile uint8_t *const reg_ipolr[] = {
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&IPOLR20, &IPOLR21, &IPOLR22, &IPOLR23
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};
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inline void set_csr(unsigned long bit)
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{
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unsigned long __tmp;
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if (__builtin_constant_p(bit) && (bit) < 32) {
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__asm__ volatile \
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("csrrs %0, mie, %1" : "=r" (__tmp) : "i" (bit));
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} else {
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__asm__ volatile \
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("csrrs %0, mie, %1" : "=r" (__tmp) : "r" (bit));
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}
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}
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#define IT8XXX2_IER_COUNT ARRAY_SIZE(reg_enable)
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static uint8_t ier_setting[IT8XXX2_IER_COUNT];
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@ -194,21 +180,6 @@ uint8_t ite_intc_get_irq_num(void)
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return intc_irq;
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}
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void ite_intc_irq_handler(const void *arg)
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{
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ARG_UNUSED(arg);
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struct _isr_table_entry *ite;
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/* software interrupt isr*/
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if ((intc_irq < CONFIG_NUM_IRQS) && (intc_irq > 0)) {
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ite = (struct _isr_table_entry *)&_sw_isr_table[intc_irq];
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ite_intc_isr_clear(intc_irq);
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ite->isr(ite->arg);
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} else {
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z_irq_spurious(NULL);
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}
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}
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uint8_t get_irq(void *arg)
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{
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ARG_UNUSED(arg);
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@ -233,16 +204,13 @@ uint8_t get_irq(void *arg)
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static int ite_intc_init(const struct device *dev)
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{
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irq_connect_dynamic(SOFT_INTC_IRQ, 0, &ite_intc_irq_handler, NULL, 0);
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ite_intc_irq_enable(SOFT_INTC_IRQ);
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irq_unlock(0);
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/* Ensure interrupts of soc are disabled at default */
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for (int i = 0; i < ARRAY_SIZE(reg_enable); i++)
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*reg_enable[i] = 0;
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/* GIE enable */
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set_csr(MIP_MEIP);
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/* Enable M-mode external interrupt */
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csr_set(mie, MIP_MEIP);
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return 0;
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}
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@ -1,109 +0,0 @@
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/*
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* Copyright (c) 2020 Michael Schaffner
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* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
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*
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* SPDX-License-Identifier: SHL-0.51
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef RISCV_CSR_ENCODING_H
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#define RISCV_CSR_ENCODING_H
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#define MSTATUS_UIE 0x00000001
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#define MSTATUS_SIE 0x00000002
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#define MSTATUS_HIE 0x00000004
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#define MSTATUS_MIE 0x00000008
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#define MSTATUS_UPIE 0x00000010
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#define MSTATUS_SPIE 0x00000020
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#define MSTATUS_HPIE 0x00000040
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#define MSTATUS_MPIE 0x00000080
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#define MSTATUS_SPP 0x00000100
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#define MSTATUS_HPP 0x00000600
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#define MSTATUS_MPP 0x00001800
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#define MSTATUS_FS 0x00006000
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#define MSTATUS_XS 0x00018000
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#define MSTATUS_MPRV 0x00020000
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#define MSTATUS_PUM 0x00040000
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#define MSTATUS_MXR 0x00080000
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#define MSTATUS_VM 0x1F000000
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#define MSTATUS32_SD 0x80000000
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#define MSTATUS64_SD 0x8000000000000000
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#define MCAUSE32_CAUSE 0x7FFFFFFF
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#define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF
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#define MCAUSE32_INT 0x80000000
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#define MCAUSE64_INT 0x8000000000000000
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#define SSTATUS_UIE 0x00000001
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#define SSTATUS_SIE 0x00000002
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#define SSTATUS_UPIE 0x00000010
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#define SSTATUS_SPIE 0x00000020
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#define SSTATUS_SPP 0x00000100
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#define SSTATUS_FS 0x00006000
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#define SSTATUS_XS 0x00018000
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#define SSTATUS_PUM 0x00040000
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#define SSTATUS32_SD 0x80000000
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#define SSTATUS64_SD 0x8000000000000000
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#define MIP_SSIP (1 << IRQ_S_SOFT)
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#define MIP_HSIP (1 << IRQ_H_SOFT)
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#define MIP_MSIP (1 << IRQ_M_SOFT)
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#define MIP_STIP (1 << IRQ_S_TIMER)
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#define MIP_HTIP (1 << IRQ_H_TIMER)
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#define MIP_MTIP (1 << IRQ_M_TIMER)
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#define MIP_SEIP (1 << IRQ_S_EXT)
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#define MIP_HEIP (1 << IRQ_H_EXT)
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#define MIP_MEIP (1 << IRQ_M_EXT)
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#define SIP_SSIP MIP_SSIP
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#define SIP_STIP MIP_STIP
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#define PRV_U 0
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#define PRV_S 1
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#define PRV_H 2
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#define PRV_M 3
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#define VM_MBARE 0
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#define VM_MBB 1
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#define VM_MBBID 2
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#define VM_SV32 8
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#define VM_SV39 9
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#define VM_SV48 10
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#define IRQ_S_SOFT 1
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#define IRQ_H_SOFT 2
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#define IRQ_M_SOFT 3
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#define IRQ_S_TIMER 5
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#define IRQ_H_TIMER 6
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#define IRQ_M_TIMER 7
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#define IRQ_S_EXT 9
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#define IRQ_H_EXT 10
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#define IRQ_M_EXT 11
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#define IRQ_COP 12
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#define IRQ_HOST 13
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#define DEFAULT_RSTVEC 0x00001000
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#define DEFAULT_NMIVEC 0x00001004
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#define DEFAULT_MTVEC 0x00001010
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#define EXT_IO_BASE 0x40000000
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#define DRAM_BASE 0x80000000
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#ifdef __riscv64
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# define MSTATUS_SD MSTATUS64_SD
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# define SSTATUS_SD SSTATUS64_SD
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# define MCAUSE_INT MCAUSE64_INT
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# define MCAUSE_CAUSE MCAUSE64_CAUSE
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# define RISCV_PGLEVEL_BITS 9
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#else
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# define MSTATUS_SD MSTATUS32_SD
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# define SSTATUS_SD SSTATUS32_SD
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# define RISCV_PGLEVEL_BITS 10
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# define MCAUSE_INT MCAUSE32_INT
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# define MCAUSE_CAUSE MCAUSE32_CAUSE
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#endif /* __riscv64 */
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#define RISCV_PGSHIFT 12
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#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
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#endif
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@ -13,63 +13,23 @@
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#define __SOC_COMMON_H_
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#include "chip_chipregs.h"
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#include "encoding.h"
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/* IRQ numbers */
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#define RISCV_MACHINE_SOFT_IRQ 161 /* Machine Software Interrupt */
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#define RISCV_MACHINE_TIMER_IRQ 157 /* Machine Timer Interrupt */
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#define RISCV_MACHINE_EXT_IRQ 11 /* Machine External Interrupt */
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#define RISCV_MAX_GENERIC_IRQ 191 /* Max Generic Interrupt */
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/* Exception numbers */
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#define RISCV_MACHINE_ECALL_EXP 11 /* Machine ECALL instruction */
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/*
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* SOC-specific MSTATUS related info
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*/
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/* MSTATUS register to save/restore upon interrupt/exception/context switch */
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#define SOC_MSTATUS_REG mstatus
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#define SOC_MSTATUS_IEN (1 << 3) /* Machine Interrupt Enable bit */
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/* Previous Privilege Mode - Machine Mode */
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#define SOC_MSTATUS_MPP_M_MODE (3 << 11)
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/* Interrupt Enable Bit in Previous Privilege Mode */
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#define SOC_MSTATUS_MPIE (1 << 7)
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/*
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* Default MSTATUS register value to restore from stack
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* upon scheduling a thread for the first time
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*/
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#define SOC_MSTATUS_DEF_RESTORE (SOC_MSTATUS_MPP_M_MODE | SOC_MSTATUS_MPIE)
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/* SOC-specific MCAUSE bitfields */
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/* Interrupt Mask */
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#define SOC_MCAUSE_IRQ_MASK (1 << 31)
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/* Interrupt Mask. 1 (interrupt) or 0 (exception) */
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#define SOC_MCAUSE_IRQ_MASK BIT(31)
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/* Exception code Mask */
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#define SOC_MCAUSE_EXP_MASK 0x7FFFFFFF
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/* ECALL exception number */
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#define SOC_MCAUSE_ECALL_EXP RISCV_MACHINE_ECALL_EXP
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/* Exception code of environment call from M-mode */
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#define SOC_MCAUSE_ECALL_EXP 11
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/* SOC-Specific EXIT ISR command */
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#define SOC_ERET mret
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#ifndef _ASMLANGUAGE
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#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
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void soc_interrupt_init(void);
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#endif
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#if defined(CONFIG_RISCV_HAS_PLIC)
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void riscv_plic_irq_enable(u32_t irq);
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void riscv_plic_irq_disable(u32_t irq);
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int riscv_plic_irq_is_enabled(u32_t irq);
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void riscv_plic_set_priority(u32_t irq, u32_t priority);
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int riscv_plic_get_irq(void);
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#endif
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#if CONFIG_ITE_IT8XXX2_INTC
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/*
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* Save current interrupt state of soc-level into ier_setting[] with
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@ -13,81 +13,28 @@
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void arch_irq_enable(unsigned int irq)
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{
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#if CONFIG_ITE_IT8XXX2_INTC
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if (irq > 0) {
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if (IS_ENABLED(CONFIG_ITE_IT8XXX2_INTC)) {
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ite_intc_irq_enable(irq);
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}
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#else
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uint32_t mie;
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#if defined(CONFIG_RISCV_HAS_PLIC)
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if (irq > RISCV_MAX_GENERIC_IRQ) {
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riscv_plic_irq_enable(irq);
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return;
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}
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#endif
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/*
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* CSR mie register is updated using atomic instruction csrrs
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* (atomic read and set bits in CSR register)
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*/
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__asm__ volatile ("csrrs %0, mie, %1\n"
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: "=r" (mie)
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: "r" (1 << irq));
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#endif /* CONFIG_ITE_IT8XXX2_INTC */
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}
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void arch_irq_disable(unsigned int irq)
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{
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#if CONFIG_ITE_IT8XXX2_INTC
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if (irq > 0) {
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if (IS_ENABLED(CONFIG_ITE_IT8XXX2_INTC)) {
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ite_intc_irq_disable(irq);
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}
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#else
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uint32_t mie;
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#if defined(CONFIG_RISCV_HAS_PLIC)
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if (irq > RISCV_MAX_GENERIC_IRQ) {
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riscv_plic_irq_disable(irq);
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return;
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}
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#endif
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/*
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* Use atomic instruction csrrc to disable device interrupt in mie CSR.
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* (atomic read and clear bits in CSR register)
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*/
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__asm__ volatile ("csrrc %0, mie, %1\n"
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: "=r" (mie)
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: "r" (1 << irq));
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#endif /* CONFIG_ITE_IT8XXX2_INTC */
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};
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int arch_irq_is_enabled(unsigned int irq)
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{
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uint32_t mie;
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#if defined(CONFIG_RISCV_HAS_PLIC)
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if (irq > RISCV_MAX_GENERIC_IRQ)
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return riscv_plic_irq_is_enabled(irq);
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#endif
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__asm__ volatile ("csrr %0, mie" : "=r" (mie));
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#if CONFIG_ITE_IT8XXX2_INTC
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return (mie && (ite_intc_irq_is_enable(irq)));
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#else
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return !!(mie & (1 << irq));
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#endif /* CONFIG_ITE_IT8XXX2_INTC */
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/*
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* Return true from arch_irq_is_enabled() when external interrupt-enable
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* bit, and SOC's IER are both true.
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*/
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if (IS_ENABLED(CONFIG_ITE_IT8XXX2_INTC)) {
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return ((csr_read(mie) & BIT(IRQ_M_EXT)) &&
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ite_intc_irq_is_enable(irq));
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} else {
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return 0;
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}
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#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
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void soc_interrupt_init(void)
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{
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/* ensure that all interrupts are disabled */
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(void)irq_lock();
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__asm__ volatile ("csrwi mie, 0\n"
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"csrwi mip, 0\n");
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}
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#endif
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@ -15,9 +15,4 @@
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#define RISCV_RAM_BASE CONFIG_SRAM_BASE_ADDRESS
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#define RISCV_RAM_SIZE KB(CONFIG_SRAM_SIZE)
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#define ite_write(reg, reg_size, val) \
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((*((volatile unsigned char *)(reg))) = val)
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#define ite_read(reg, reg_size) \
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(*((volatile unsigned char *)(reg)))
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#endif /* __RISCV_ITE_SOC_H_ */
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