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cleanup: soc: it8xxx2: remove unnecessary code

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Code removed:
- IT8XXX2 doesn't support soc level software interrupt hence remove
  them.
- To use common macro to access csr (control status register).
- To remove CONFIG_RISCV_HAS_PLIC related code. IT8XXX2 uses its own
  interrupt controller code.
- To remove ite_write and ite_read. We don't use them anymore.

Code changed:
- Return true from arch_irq_is_enabled() when external interrupt-enable
  bit, and SOC's IER are both true.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This commit is contained in:
Dino Li 2021-08-19 11:37:36 +08:00 • committed by Carles Cufí
commit 29d039335f
5 changed files with 22 additions and 261 deletions
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38
drivers/interrupt_controller/intc_ite_it8xxx2.c
View file

@ -13,7 +13,6 @@
#define MAX_REGISR_IRQ_NUM 8 #define MAX_REGISR_IRQ_NUM 8
#define IVECT_OFFSET_WITH_IRQ 0x10 #define IVECT_OFFSET_WITH_IRQ 0x10
#define SOFT_INTC_IRQ 161 /* software interrupt */
/* Interrupt number of INTC module */ /* Interrupt number of INTC module */
static uint8_t intc_irq; static uint8_t intc_irq;
@ -56,19 +55,6 @@ static volatile uint8_t *const reg_ipolr[] = {
&IPOLR20, &IPOLR21, &IPOLR22, &IPOLR23 &IPOLR20, &IPOLR21, &IPOLR22, &IPOLR23
}; };
inline void set_csr(unsigned long bit)
{
unsigned long __tmp;
if (__builtin_constant_p(bit) && (bit) < 32) {
__asm__ volatile \
("csrrs %0, mie, %1" : "=r" (__tmp) : "i" (bit));
} else {
__asm__ volatile \
("csrrs %0, mie, %1" : "=r" (__tmp) : "r" (bit));
}
}
#define IT8XXX2_IER_COUNT ARRAY_SIZE(reg_enable) #define IT8XXX2_IER_COUNT ARRAY_SIZE(reg_enable)
static uint8_t ier_setting[IT8XXX2_IER_COUNT]; static uint8_t ier_setting[IT8XXX2_IER_COUNT];
@ -194,21 +180,6 @@ uint8_t ite_intc_get_irq_num(void)
return intc_irq; return intc_irq;
} }
void ite_intc_irq_handler(const void *arg)
{
ARG_UNUSED(arg);
struct _isr_table_entry *ite;
/* software interrupt isr*/
if ((intc_irq < CONFIG_NUM_IRQS) && (intc_irq > 0)) {
ite = (struct _isr_table_entry *)&_sw_isr_table[intc_irq];
ite_intc_isr_clear(intc_irq);
ite->isr(ite->arg);
} else {
z_irq_spurious(NULL);
}
}
uint8_t get_irq(void *arg) uint8_t get_irq(void *arg)
{ {
ARG_UNUSED(arg); ARG_UNUSED(arg);
@ -233,16 +204,13 @@ uint8_t get_irq(void *arg)
static int ite_intc_init(const struct device *dev) static int ite_intc_init(const struct device *dev)
{ {
irq_connect_dynamic(SOFT_INTC_IRQ, 0, &ite_intc_irq_handler, NULL, 0);
ite_intc_irq_enable(SOFT_INTC_IRQ);
irq_unlock(0);
/* Ensure interrupts of soc are disabled at default */ /* Ensure interrupts of soc are disabled at default */
for (int i = 0; i < ARRAY_SIZE(reg_enable); i++) for (int i = 0; i < ARRAY_SIZE(reg_enable); i++)
*reg_enable[i] = 0; *reg_enable[i] = 0;
/* GIE enable */ /* Enable M-mode external interrupt */
set_csr(MIP_MEIP); csr_set(mie, MIP_MEIP);
return 0; return 0;
} }

109
soc/riscv/riscv-ite/common/encoding.h
View file

@ -1,109 +0,0 @@
/*
* Copyright (c) 2020 Michael Schaffner
* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
*
* SPDX-License-Identifier: SHL-0.51
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef RISCV_CSR_ENCODING_H
#define RISCV_CSR_ENCODING_H
#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
#define MSTATUS_HIE 0x00000004
#define MSTATUS_MIE 0x00000008
#define MSTATUS_UPIE 0x00000010
#define MSTATUS_SPIE 0x00000020
#define MSTATUS_HPIE 0x00000040
#define MSTATUS_MPIE 0x00000080
#define MSTATUS_SPP 0x00000100
#define MSTATUS_HPP 0x00000600
#define MSTATUS_MPP 0x00001800
#define MSTATUS_FS 0x00006000
#define MSTATUS_XS 0x00018000
#define MSTATUS_MPRV 0x00020000
#define MSTATUS_PUM 0x00040000
#define MSTATUS_MXR 0x00080000
#define MSTATUS_VM 0x1F000000
#define MSTATUS32_SD 0x80000000
#define MSTATUS64_SD 0x8000000000000000
#define MCAUSE32_CAUSE 0x7FFFFFFF
#define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF
#define MCAUSE32_INT 0x80000000
#define MCAUSE64_INT 0x8000000000000000
#define SSTATUS_UIE 0x00000001
#define SSTATUS_SIE 0x00000002
#define SSTATUS_UPIE 0x00000010
#define SSTATUS_SPIE 0x00000020
#define SSTATUS_SPP 0x00000100
#define SSTATUS_FS 0x00006000
#define SSTATUS_XS 0x00018000
#define SSTATUS_PUM 0x00040000
#define SSTATUS32_SD 0x80000000
#define SSTATUS64_SD 0x8000000000000000
#define MIP_SSIP (1 << IRQ_S_SOFT)
#define MIP_HSIP (1 << IRQ_H_SOFT)
#define MIP_MSIP (1 << IRQ_M_SOFT)
#define MIP_STIP (1 << IRQ_S_TIMER)
#define MIP_HTIP (1 << IRQ_H_TIMER)
#define MIP_MTIP (1 << IRQ_M_TIMER)
#define MIP_SEIP (1 << IRQ_S_EXT)
#define MIP_HEIP (1 << IRQ_H_EXT)
#define MIP_MEIP (1 << IRQ_M_EXT)
#define SIP_SSIP MIP_SSIP
#define SIP_STIP MIP_STIP
#define PRV_U 0
#define PRV_S 1
#define PRV_H 2
#define PRV_M 3
#define VM_MBARE 0
#define VM_MBB 1
#define VM_MBBID 2
#define VM_SV32 8
#define VM_SV39 9
#define VM_SV48 10
#define IRQ_S_SOFT 1
#define IRQ_H_SOFT 2
#define IRQ_M_SOFT 3
#define IRQ_S_TIMER 5
#define IRQ_H_TIMER 6
#define IRQ_M_TIMER 7
#define IRQ_S_EXT 9
#define IRQ_H_EXT 10
#define IRQ_M_EXT 11
#define IRQ_COP 12
#define IRQ_HOST 13
#define DEFAULT_RSTVEC 0x00001000
#define DEFAULT_NMIVEC 0x00001004
#define DEFAULT_MTVEC 0x00001010
#define EXT_IO_BASE 0x40000000
#define DRAM_BASE 0x80000000
#ifdef __riscv64
# define MSTATUS_SD MSTATUS64_SD
# define SSTATUS_SD SSTATUS64_SD
# define MCAUSE_INT MCAUSE64_INT
# define MCAUSE_CAUSE MCAUSE64_CAUSE
# define RISCV_PGLEVEL_BITS 9
#else
# define MSTATUS_SD MSTATUS32_SD
# define SSTATUS_SD SSTATUS32_SD
# define RISCV_PGLEVEL_BITS 10
# define MCAUSE_INT MCAUSE32_INT
# define MCAUSE_CAUSE MCAUSE32_CAUSE
#endif /* __riscv64 */
#define RISCV_PGSHIFT 12
#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
#endif

54
soc/riscv/riscv-ite/common/soc_common.h
View file

@ -13,63 +13,23 @@
#define __SOC_COMMON_H_ #define __SOC_COMMON_H_
#include "chip_chipregs.h" #include "chip_chipregs.h"
#include "encoding.h"
/* IRQ numbers */
#define RISCV_MACHINE_SOFT_IRQ 161 /* Machine Software Interrupt */
#define RISCV_MACHINE_TIMER_IRQ 157 /* Machine Timer Interrupt */
#define RISCV_MACHINE_EXT_IRQ 11 /* Machine External Interrupt */
#define RISCV_MAX_GENERIC_IRQ 191 /* Max Generic Interrupt */
/* Exception numbers */
#define RISCV_MACHINE_ECALL_EXP 11 /* Machine ECALL instruction */
/*
* SOC-specific MSTATUS related info
*/
/* MSTATUS register to save/restore upon interrupt/exception/context switch */
#define SOC_MSTATUS_REG mstatus
#define SOC_MSTATUS_IEN (1 << 3) /* Machine Interrupt Enable bit */
/* Previous Privilege Mode - Machine Mode */
#define SOC_MSTATUS_MPP_M_MODE (3 << 11)
/* Interrupt Enable Bit in Previous Privilege Mode */
#define SOC_MSTATUS_MPIE (1 << 7)
/*
* Default MSTATUS register value to restore from stack
* upon scheduling a thread for the first time
*/
#define SOC_MSTATUS_DEF_RESTORE (SOC_MSTATUS_MPP_M_MODE | SOC_MSTATUS_MPIE)
/* SOC-specific MCAUSE bitfields */ /* SOC-specific MCAUSE bitfields */
/* Interrupt Mask */
#define SOC_MCAUSE_IRQ_MASK (1 << 31) /* Interrupt Mask. 1 (interrupt) or 0 (exception) */
#define SOC_MCAUSE_IRQ_MASK BIT(31)
/* Exception code Mask */ /* Exception code Mask */
#define SOC_MCAUSE_EXP_MASK 0x7FFFFFFF #define SOC_MCAUSE_EXP_MASK 0x7FFFFFFF
/* ECALL exception number */
#define SOC_MCAUSE_ECALL_EXP RISCV_MACHINE_ECALL_EXP /* Exception code of environment call from M-mode */
#define SOC_MCAUSE_ECALL_EXP 11
/* SOC-Specific EXIT ISR command */ /* SOC-Specific EXIT ISR command */
#define SOC_ERET mret #define SOC_ERET mret
#ifndef _ASMLANGUAGE #ifndef _ASMLANGUAGE
#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
void soc_interrupt_init(void);
#endif
#if defined(CONFIG_RISCV_HAS_PLIC)
void riscv_plic_irq_enable(u32_t irq);
void riscv_plic_irq_disable(u32_t irq);
int riscv_plic_irq_is_enabled(u32_t irq);
void riscv_plic_set_priority(u32_t irq, u32_t priority);
int riscv_plic_get_irq(void);
#endif
#if CONFIG_ITE_IT8XXX2_INTC #if CONFIG_ITE_IT8XXX2_INTC
/* /*
* Save current interrupt state of soc-level into ier_setting[] with * Save current interrupt state of soc-level into ier_setting[] with

77
soc/riscv/riscv-ite/common/soc_common_irq.c
View file

@ -13,81 +13,28 @@
void arch_irq_enable(unsigned int irq) void arch_irq_enable(unsigned int irq)
{ {
#if CONFIG_ITE_IT8XXX2_INTC if (IS_ENABLED(CONFIG_ITE_IT8XXX2_INTC)) {
if (irq > 0) {
ite_intc_irq_enable(irq); ite_intc_irq_enable(irq);
} }
#else
uint32_t mie;
#if defined(CONFIG_RISCV_HAS_PLIC)
if (irq > RISCV_MAX_GENERIC_IRQ) {
riscv_plic_irq_enable(irq);
return;
}
#endif
/*
* CSR mie register is updated using atomic instruction csrrs
* (atomic read and set bits in CSR register)
*/
__asm__ volatile ("csrrs %0, mie, %1\n"
: "=r" (mie)
: "r" (1 << irq));
#endif /* CONFIG_ITE_IT8XXX2_INTC */
} }
void arch_irq_disable(unsigned int irq) void arch_irq_disable(unsigned int irq)
{ {
#if CONFIG_ITE_IT8XXX2_INTC if (IS_ENABLED(CONFIG_ITE_IT8XXX2_INTC)) {
if (irq > 0) {
ite_intc_irq_disable(irq); ite_intc_irq_disable(irq);
} }
#else
uint32_t mie;
#if defined(CONFIG_RISCV_HAS_PLIC)
if (irq > RISCV_MAX_GENERIC_IRQ) {
riscv_plic_irq_disable(irq);
return;
}
#endif
/*
* Use atomic instruction csrrc to disable device interrupt in mie CSR.
* (atomic read and clear bits in CSR register)
*/
__asm__ volatile ("csrrc %0, mie, %1\n"
: "=r" (mie)
: "r" (1 << irq));
#endif /* CONFIG_ITE_IT8XXX2_INTC */
}; };
int arch_irq_is_enabled(unsigned int irq) int arch_irq_is_enabled(unsigned int irq)
{ {
uint32_t mie; /*
* Return true from arch_irq_is_enabled() when external interrupt-enable
#if defined(CONFIG_RISCV_HAS_PLIC) * bit, and SOC's IER are both true.
if (irq > RISCV_MAX_GENERIC_IRQ) */
return riscv_plic_irq_is_enabled(irq); if (IS_ENABLED(CONFIG_ITE_IT8XXX2_INTC)) {
#endif return ((csr_read(mie) & BIT(IRQ_M_EXT)) &&
ite_intc_irq_is_enable(irq));
__asm__ volatile ("csrr %0, mie" : "=r" (mie)); } else {
return 0;
#if CONFIG_ITE_IT8XXX2_INTC }
return (mie && (ite_intc_irq_is_enable(irq)));
#else
return !!(mie & (1 << irq));
#endif /* CONFIG_ITE_IT8XXX2_INTC */
} }
#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
void soc_interrupt_init(void)
{
/* ensure that all interrupts are disabled */
(void)irq_lock();
__asm__ volatile ("csrwi mie, 0\n"
"csrwi mip, 0\n");
}
#endif

5
soc/riscv/riscv-ite/it8xxx2/soc.h
View file

@ -15,9 +15,4 @@
#define RISCV_RAM_BASE CONFIG_SRAM_BASE_ADDRESS #define RISCV_RAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define RISCV_RAM_SIZE KB(CONFIG_SRAM_SIZE) #define RISCV_RAM_SIZE KB(CONFIG_SRAM_SIZE)
#define ite_write(reg, reg_size, val) \
((*((volatile unsigned char *)(reg))) = val)
#define ite_read(reg, reg_size) \
(*((volatile unsigned char *)(reg)))
#endif /* __RISCV_ITE_SOC_H_ */ #endif /* __RISCV_ITE_SOC_H_ */