dts: nios2-qemu: add device tree support

Add device tree support for nios2-qemu

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>

arch/nios2/soc/nios2-qemu/dts.fixup

@@ -0,0 +1,7 @@
+#define _RAM_ADDR				CONFIG_SRAM_BASE_ADDRESS
+
+#define _RAM_SIZE				(CONFIG_SRAM_SIZE * 1024)
+
+#define _ROM_ADDR				CONFIG_FLASH_BASE_ADDRESS
+
+#define _ROM_SIZE				(CONFIG_FLASH_SIZE *1024)

arch/nios2/soc/nios2-qemu/include/layout.h

@@ -10,13 +10,5 @@
  * higher-addressed chunk considered "ROM"
  */
 
-#define HALF_RAM		(ONCHIP_MEMORY2_0_SPAN / 2)
+#define _RESET_VECTOR		_ROM_ADDR
-
-#define _RESET_VECTOR		(ONCHIP_MEMORY2_0_BASE + HALF_RAM)
 #define	_EXC_VECTOR		ALT_CPU_EXCEPTION_ADDR
-
-#define _ROM_ADDR		(ONCHIP_MEMORY2_0_BASE + HALF_RAM)
-#define _ROM_SIZE		HALF_RAM
-
-#define _RAM_ADDR		ONCHIP_MEMORY2_0_BASE
-#define _RAM_SIZE		HALF_RAM

arch/nios2/soc/nios2-qemu/linker.ld

@@ -9,5 +9,5 @@
  */
 
 #include <layout.h>
-
+#include <generated_dts_board.h>
 #include <arch/nios2/linker.ld>

dts/bindings/serial/altera,jtag-uart.yaml

@@ -0,0 +1,30 @@
+---
+title: Altera JTAG UART
+id: altera,jtag-uart
+version: 0.1
+
+description: >
+    This binding gives a base representation of the Altera Jtag UART
+
+inherits:
+    !include uart.yaml
+
+properties:
+    compatible:
+      type: string
+      category: required
+      description: compatible strings
+      constraint: "altera,jtag-uart"
+
+    reg:
+      type: array
+      description: mmio register space
+      generation: define
+      category: required
+
+    interrupts:
+      type: array
+      category: required
+      description: required interrupts
+      generation: define
+...

dts/nios2/nios2-qemu.dtsi

@@ -0,0 +1,43 @@
+#include "skeleton.dtsi"
+
+#define __SIZE_K(x) (x * 1024)
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "qemu,nios2";
+			reg = <0>;
+		};
+
+	};
+
+	flash0: flash@0 {
+		reg = <0x420000 0x20000>;
+	};
+
+	sram0: memory@400000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x400000 0x20000>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		uart0: uart@201000 {
+			compatible = "altera,jtag-uart";
+			reg = <0x201000 0x400>;
+			label = "jtag_uart0";
+
+			status = "disabled";
+		};
+
+	};
+};