drivers: enet: eth_nxp_enet_qos_mac: handle errors in RX queue worker
Handle each error individually. Do not skip RX loop on first error. Revise DMA buf size to CONFIG_NET_BUF_DATA_SIZE. Signed-off-by: Adib Taraben <theadib@gmail.com>
This commit is contained in:
Adib Taraben
Benjamin Cabé
parent
bf111b44ad
commit
293b8d6003
2 changed files with 89 additions and 23 deletions
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@ -6,12 +6,16 @@
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#define DT_DRV_COMPAT nxp_enet_qos_mac
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#include <zephyr/kernel.h>
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#include <zephyr/irq.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(eth_nxp_enet_qos_mac, CONFIG_ETHERNET_LOG_LEVEL);
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#include <zephyr/net/phy.h>
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#include <zephyr/kernel/thread_stack.h>
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#include <zephyr/sys_clock.h>
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#if defined(CONFIG_ETH_NXP_ENET_QOS_MAC_UNIQUE_MAC_ADDRESS)
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#include <zephyr/sys/crc.h>
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#include <zephyr/drivers/hwinfo.h>
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@ -177,6 +181,7 @@ static void eth_nxp_enet_qos_rx(struct k_work *work)
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struct net_buf *buf;
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size_t pkt_len;
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LOG_DBG("iteration work:%p, rx_data:%p, data:%p", work, rx_data, data);
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/* We are going to find all of the descriptors we own and update them */
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for (int i = 0; i < NUM_RX_BUFDESC; i++) {
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desc = &desc_arr[i];
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@ -186,16 +191,27 @@ static void eth_nxp_enet_qos_rx(struct k_work *work)
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continue;
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}
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if ((desc->write.control3 & (FIRST_TX_DESCRIPTOR_FLAG | LAST_TX_DESCRIPTOR_FLAG)) !=
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(FIRST_TX_DESCRIPTOR_FLAG | LAST_TX_DESCRIPTOR_FLAG)) {
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LOG_DBG("receive packet mask %X ", (desc->write.control3 >> 28) & 0x0f);
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LOG_ERR("Rx pkt spans over multiple DMA bufs, not implemented, drop here");
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desc->read.control = rx_desc_refresh_flags;
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continue;
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}
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/* Otherwise, we found a packet that we need to process */
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pkt = net_pkt_rx_alloc(K_NO_WAIT);
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if (!pkt) {
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LOG_ERR("Could not alloc RX pkt");
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goto error;
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LOG_ERR("Could not alloc new RX pkt");
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/* error: no new buffer, reuse previous immediately
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*/
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desc->read.control = rx_desc_refresh_flags;
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eth_stats_update_errors_rx(data->iface);
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continue;
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}
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LOG_DBG("Created RX pkt %p", pkt);
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LOG_DBG("Created new RX pkt %d of %d: %p", i + 1, NUM_RX_BUFDESC, pkt);
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/* We need to know if we can replace the reserved fragment in advance.
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* At no point can we allow the driver to have less the amount of reserved
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* buffers it needs to function, so we will not give up our previous buffer
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@ -206,16 +222,19 @@ static void eth_nxp_enet_qos_rx(struct k_work *work)
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/* We have no choice but to lose the previous packet,
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* as the buffer is more important. If we recv this packet,
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* we don't know what the upper layer will do to our poor buffer.
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* drop this buffer, reuse allocated DMA buffer
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*/
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LOG_ERR("No RX buf available");
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goto error;
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LOG_ERR("No new RX buf available");
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net_pkt_unref(pkt);
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desc->read.control = rx_desc_refresh_flags;
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eth_stats_update_errors_rx(data->iface);
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continue;
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}
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buf = data->rx.reserved_bufs[i];
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pkt_len = desc->write.control3 & DESC_RX_PKT_LEN;
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LOG_DBG("Receiving RX packet");
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/* Finally, we have decided that it is time to wrap the buffer nicely
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* up within a packet, and try to send it. It's only one buffer,
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* thanks to ENET QOS hardware handing the fragmentation,
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@ -226,25 +245,40 @@ static void eth_nxp_enet_qos_rx(struct k_work *work)
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if (net_recv_data(data->iface, pkt)) {
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LOG_ERR("RECV failed");
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/* Quite a shame. */
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goto error;
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/* error during processing, we continue with new allocated */
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net_pkt_unref(pkt);
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eth_stats_update_errors_rx(data->iface);
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}
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LOG_DBG("Recycling RX buf");
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LOG_DBG("Swap RX buf");
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/* Fresh meat */
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data->rx.reserved_bufs[i] = new_buf;
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desc->read.buf1_addr = (uint32_t)new_buf->data;
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desc->read.control |= rx_desc_refresh_flags;
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desc->read.control = rx_desc_refresh_flags;
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/* Record our glorious victory */
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eth_stats_update_pkts_rx(data->iface);
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}
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return;
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/* try to restart if halted */
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const struct device *dev = net_if_get_device(data->iface);
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atomic_val_t rbu_flag = atomic_get(&rx_data->rbu_flag);
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error:
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net_pkt_unref(pkt);
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eth_stats_update_errors_rx(data->iface);
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if (rbu_flag) {
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LOG_DBG("handle RECEIVE BUFFER UNDERRUN in worker");
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atomic_clear(&rx_data->rbu_flag);
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/* When the DMA reaches the tail pointer, it suspends. Set to last descriptor */
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const struct nxp_enet_qos_mac_config *config = dev->config;
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enet_qos_t *const base = config->base;
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base->DMA_CH[0].DMA_CHX_RXDESC_TAIL_PTR = ENET_QOS_REG_PREP(
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DMA_CH_DMA_CHX_RXDESC_TAIL_PTR, RDTP,
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ENET_QOS_ALIGN_ADDR_SHIFT((uint32_t)&rx_data->descriptors[NUM_RX_BUFDESC]));
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}
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LOG_DBG("end loop normally");
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return;
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}
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static void eth_nxp_enet_qos_mac_isr(const struct device *dev)
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@ -254,22 +288,46 @@ static void eth_nxp_enet_qos_mac_isr(const struct device *dev)
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enet_qos_t *base = config->base;
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/* cleared on read */
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volatile uint32_t mac_interrupts = base->MAC_INTERRUPT_STATUS;
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volatile uint32_t mac_rx_tx_status = base->MAC_RX_TX_STATUS;
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volatile uint32_t dma_interrupts = base->DMA_INTERRUPT_STATUS;
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volatile uint32_t dma_ch0_interrupts = base->DMA_CH[0].DMA_CHX_STAT;
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uint32_t mac_interrupts = base->MAC_INTERRUPT_STATUS;
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uint32_t mac_rx_tx_status = base->MAC_RX_TX_STATUS;
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uint32_t dma_interrupts = base->DMA_INTERRUPT_STATUS;
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uint32_t dma_ch0_interrupts = base->DMA_CH[0].DMA_CHX_STAT;
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mac_interrupts; mac_rx_tx_status;
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/* clear pending bits except RBU
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* handle the receive underrun in the worker
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*/
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base->DMA_CH[0].DMA_CHX_STAT = dma_ch0_interrupts;
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base->DMA_CH[0].DMA_CHX_STAT = 0xFFFFFFFF;
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if (dma_ch0_interrupts & ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_STAT, RBU, 0b1)) {
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atomic_set(&data->rx.rbu_flag, 1);
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}
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if (ENET_QOS_REG_GET(DMA_INTERRUPT_STATUS, DC0IS, dma_interrupts)) {
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if (ENET_QOS_REG_GET(DMA_CH_DMA_CHX_STAT, TI, dma_ch0_interrupts)) {
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/* add pending tx to queue */
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k_work_submit(&data->tx.tx_done_work);
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}
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if (ENET_QOS_REG_GET(DMA_CH_DMA_CHX_STAT, RI, dma_ch0_interrupts)) {
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/* add pending rx to queue */
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k_work_submit_to_queue(&rx_work_queue, &data->rx.rx_work);
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}
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if (ENET_QOS_REG_GET(DMA_CH_DMA_CHX_STAT, FBE, dma_ch0_interrupts)) {
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LOG_ERR("fatal bus error: RX:%x, TX:%x", (dma_ch0_interrupts >> 19) & 0x07,
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(dma_ch0_interrupts >> 16) & 0x07);
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}
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if (ENET_QOS_REG_GET(DMA_CH_DMA_CHX_STAT, RBU, dma_ch0_interrupts)) {
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LOG_ERR("RECEIVE BUFFER UNDERRUN in ISR");
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if (!ENET_QOS_REG_GET(DMA_CH_DMA_CHX_STAT, RI, dma_ch0_interrupts)) {
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/* RBU migth happen without RI, schedule worker */
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k_work_submit_to_queue(&rx_work_queue, &data->rx.rx_work);
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}
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}
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if (ENET_QOS_REG_GET(DMA_CH_DMA_CHX_STAT, TBU, dma_ch0_interrupts)) {
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/* actually this is not an error
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* LOG_ERR("TRANSMIT BUFFER UNDERRUN");
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*/
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}
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}
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}
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@ -420,7 +478,13 @@ static inline void enet_qos_start(enet_qos_t *base)
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/* Transmit interrupt */
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ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_INT_EN, TIE, 0b1) |
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/* Receive interrupt */
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ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_INT_EN, RIE, 0b1);
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ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_INT_EN, RIE, 0b1) |
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/* Abnormal interrupts (includes rbu, rs) */
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ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_INT_EN, AIE, 0b1) |
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/* Receive buffer unavailable */
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ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_INT_EN, RBUE, 0b1) |
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/* Receive stopped */
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ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_INT_EN, RSE, 0b1);
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base->MAC_INTERRUPT_ENABLE =
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/* Receive and Transmit IRQs */
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ENET_QOS_REG_PREP(MAC_INTERRUPT_ENABLE, TXSTSIE, 0b1) |
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@ -480,7 +544,7 @@ static inline int enet_qos_rx_desc_init(enet_qos_t *base, struct nxp_enet_qos_rx
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ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_RX_CONTROL2, RDRL, NUM_RX_BUFDESC - 1);
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base->DMA_CH[0].DMA_CHX_RX_CTRL |=
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/* Set DMA receive buffer size. The low 2 bits are not entered to this field. */
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ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_RX_CTRL, RBSZ_13_Y, NET_ETH_MAX_FRAME_SIZE >> 2);
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ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_RX_CTRL, RBSZ_13_Y, CONFIG_NET_BUF_DATA_SIZE >> 2);
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return 0;
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}
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@ -7,6 +7,7 @@
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/sys/atomic.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/net/ethernet.h>
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#include <zephyr/drivers/ethernet/eth_nxp_enet_qos.h>
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@ -111,6 +112,7 @@ struct nxp_enet_qos_tx_data {
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struct nxp_enet_qos_rx_data {
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struct k_work rx_work;
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atomic_t rbu_flag;
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volatile union nxp_enet_qos_rx_desc descriptors[NUM_RX_BUFDESC];
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struct net_buf *reserved_bufs[NUM_RX_BUFDESC];
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};
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