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boards: intel: Updated TSC frequency values

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Updated TSC frequency values of intel boards.

Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
This commit is contained in:
Anisetti Avinash Krishna 2025-03-30 20:32:53 +05:30 • committed by Benjamin Cabé
commit 2933dea4ea
2 changed files with 20 additions and 6 deletions
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6
boards/intel/adl/Kconfig.defconfig
View file

@ -7,10 +7,10 @@ config BUILD_OUTPUT_STRIPPED
config MP_MAX_NUM_CPUS
default 2
# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
# TSC on this board is 1.5 GHz, HPET and APIC are 19.2 MHz
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1900000000 if APIC_TSC_DEADLINE_TIMER
default 1900000000 if APIC_TIMER_TSC
default 1500000000 if APIC_TSC_DEADLINE_TIMER
default 1500000000 if APIC_TIMER_TSC
default 19200000
if APIC_TIMER

20
boards/intel/rpl/Kconfig.defconfig
View file

@ -8,12 +8,26 @@ config BUILD_OUTPUT_STRIPPED
config MP_MAX_NUM_CPUS
default 2
# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
if BOARD_INTEL_RPL_S_CRB
# TSC on this board is 2.4 GHz for RPL-S, HPET and APIC are 19.2 MHz
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1900000000 if APIC_TSC_DEADLINE_TIMER
default 1900000000 if APIC_TIMER_TSC
default 2400000000 if APIC_TSC_DEADLINE_TIMER
default 2400000000 if APIC_TIMER_TSC
default 19200000
endif #BOARD_INTEL_RPL_S_CRB
if BOARD_INTEL_RPL_P_CRB
# TSC on this board is 1.8 GHz for RPL-P, HPET and APIC are 19.2 MHz
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1800000000 if APIC_TSC_DEADLINE_TIMER
default 1800000000 if APIC_TIMER_TSC
default 19200000
endif #BOARD_INTEL_RPL_P_CRB
if APIC_TIMER
config APIC_TIMER_IRQ
default 24