michaelh/zephyr
1
0
Fork 0
Code Releases Activity

ext: stm32cube: update stm32l4xx cube version

Browse source 
Update Cube version for STM32L4XX family
from version: V1.9.0
to version: V1.10.0

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2018-01-16 09:53:28 +01:00 • committed by Kumar Gala
commit 28c2079c63
61 changed files with 3235 additions and 3890 deletions
Download patch file Download diff file Expand all files Collapse all files

2
ext/hal/st/stm32cube/stm32l4xx/README
View file

@ -1,4 +1,4 @@
The current version supported in Zephyr for STM32L4 Cube is V1.9.0
The current version supported in Zephyr for STM32L4 Cube is V1.10.0
Patch List:

444
ext/hal/st/stm32cube/stm32l4xx/drivers/include/Legacy/stm32_hal_legacy.h
View file

File diff suppressed because it is too large Load diff

540
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_adc.h
View file

@ -66,13 +66,13 @@
typedef struct
{
uint32_t Ratio; /*!< Configures the oversampling ratio.
This parameter can be a value of @ref ADC_Oversampling_Ratio */
This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
This parameter can be a value of @ref ADC_Right_Bit_Shift */
This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
This parameter can be a value of @ref ADC_Triggered_Oversampling_Mode */
This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode.
The oversampling is either temporary stopped or reset upon an injected
@ -80,7 +80,7 @@ typedef struct
If oversampling is enabled on both regular and injected groups, this parameter
is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
(the oversampling buffer is zeroed during injection sequence).
This parameter can be a value of @ref ADC_Regular_Oversampling_Mode */
This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
}ADC_OversamplingTypeDef;
@ -103,7 +103,7 @@ typedef struct
typedef struct
{
uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.
This parameter can be a value of @ref ADC_ClockPrescaler.
This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
Note: The ADC clock configuration is common to all ADC instances.
Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
@ -114,11 +114,11 @@ typedef struct
Note: This parameter can be modified only if all ADC instances are disabled. */
uint32_t Resolution; /*!< Configure the ADC resolution.
This parameter can be a value of @ref ADC_Resolution */
This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left).
Refer to reference manual for alignments formats versus resolutions.
This parameter can be a value of @ref ADC_Data_align */
This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected.
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
@ -179,7 +179,7 @@ typedef struct
uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
This parameter applies to ADC group regular only.
This parameter can be a value of @ref ADC_Overrun.
This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
@ -197,7 +197,7 @@ typedef struct
#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
uint32_t DFSDMConfig; /*!< Specify whether ADC conversion data is sent directly to DFSDM.
This parameter can be a value of @ref ADCEx_DFSDM_Mode_Configuration.
This parameter can be a value of @ref ADC_HAL_EC_REG_DFSDM_TRANSFER.
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
#endif
@ -217,11 +217,11 @@ typedef struct
typedef struct
{
uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
This parameter can be a value of @ref ADC_channels
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
uint32_t Rank; /*!< Specify the rank in the regular group sequencer.
This parameter can be a value of @ref ADC_regular_rank
This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
the new channel setting (or parameter number of conversions adjusted) */
@ -239,7 +239,7 @@ typedef struct
uint32_t SingleDiff; /*!< Select single-ended or differential input.
In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
This parameter must be a value of @ref ADCEx_SingleDifferential
This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING
Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
It overwrites the last setting.
Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
@ -249,7 +249,7 @@ typedef struct
of another parameter update on the fly) */
uint32_t OffsetNumber; /*!< Select the offset number
This parameter can be a value of @ref ADCEx_OffsetNumber
This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB
Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data.
@ -272,19 +272,17 @@ typedef struct
uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
This parameter can be a value of @ref ADC_analog_watchdog_number. */
This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected.
For Analog Watchdog 2 and 3: There is no configuration for all channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset
channels group programmed with parameter 'Channel', set any other value to program the channel(s) to be monitored.
For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel.
This parameter can be a value of @ref ADC_analog_watchdog_mode. */
uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
This parameter can be a value of @ref ADC_channels. */
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
uint32_t ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
This parameter can be set to ENABLE or DISABLE */
@ -407,49 +405,49 @@ typedef struct
* @}
*/
/** @defgroup ADC_ClockPrescaler ADC clock source and clock prescaler
/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
* @{
*/
#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided */
#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided a prescaler of 2 */
#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided a prescaler of 4 */
#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */
#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 /*!< Obsolete naming, kept for compatibility with some other devices */
#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /*!< Obsolete naming, kept for compatibility with some other devices */
#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /*!< Obsolete naming, kept for compatibility with some other devices */
#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */
#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */
#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */
#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */
#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */
#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */
#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */
#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */
#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */
#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */
#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */
#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */
#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock not divided */
#define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_PRESC_0) /*!< ADC asynchronous clock divided by 2 */
#define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_PRESC_1) /*!< ADC asynchronous clock divided by 4 */
#define ADC_CLOCK_ASYNC_DIV6 ((uint32_t)(ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 6 */
#define ADC_CLOCK_ASYNC_DIV8 ((uint32_t)(ADC_CCR_PRESC_2)) /*!< ADC asynchronous clock divided by 8 */
#define ADC_CLOCK_ASYNC_DIV10 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 10 */
#define ADC_CLOCK_ASYNC_DIV12 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1)) /*!< ADC asynchronous clock divided by 12 */
#define ADC_CLOCK_ASYNC_DIV16 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 16 */
#define ADC_CLOCK_ASYNC_DIV32 ((uint32_t)(ADC_CCR_PRESC_3)) /*!< ADC asynchronous clock divided by 32 */
#define ADC_CLOCK_ASYNC_DIV64 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 64 */
#define ADC_CLOCK_ASYNC_DIV128 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1)) /*!< ADC asynchronous clock divided by 128 */
#define ADC_CLOCK_ASYNC_DIV256 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 256 */
#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 /*!< Obsolete naming, kept for compatibility with some other devices */
#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /*!< Obsolete naming, kept for compatibility with some other devices */
#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /*!< Obsolete naming, kept for compatibility with some other devices */
/**
* @}
*/
/** @defgroup ADC_Resolution ADC Resolution
/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution
* @{
*/
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR_RES_0) /*!< ADC 10-bit resolution */
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_1) /*!< ADC 8-bit resolution */
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR_RES) /*!< ADC 6-bit resolution */
#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */
#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */
#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */
#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */
/**
* @}
*/
/** @defgroup ADC_Data_align ADC conversion data alignment
/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
* @{
*/
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) /*!< Data right alignment */
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR_ALIGN) /*!< Data left alignment */
#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
/**
* @}
*/
@ -457,8 +455,8 @@ typedef struct
/** @defgroup ADC_Scan_mode ADC sequencer scan mode
* @{
*/
#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) /*!< Scan mode disabled */
#define ADC_SCAN_ENABLE ((uint32_t)0x00000001) /*!< Scan mode enabled */
#define ADC_SCAN_DISABLE (0x00000000U) /*!< Scan mode disabled */
#define ADC_SCAN_ENABLE (0x00000001U) /*!< Scan mode enabled */
/**
* @}
*/
@ -467,23 +465,23 @@ typedef struct
* @{
*/
/* ADC group regular trigger sources for all ADC instances */
#define ADC_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000) /*!< Event 0 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) /*!< Event 1 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) /*!< Event 2 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 3 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2) /*!< Event 4 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) /*!< Event 5 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) /*!< Event 6 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 7 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3) /*!< Event 8 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0)) /*!< Event 9 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1)) /*!< Event 10 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 11 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2)) /*!< Event 12 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) /*!< Event 13 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) /*!< Event 14 triggers regular group conversion start */
#define ADC_EXTERNALTRIG_T3_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 15 triggers regular group conversion start */
#define ADC_SOFTWARE_START ((uint32_t)0x00000001) /*!< Software triggers regular group conversion start */
#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */
#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
/**
* @}
*/
@ -491,10 +489,10 @@ typedef struct
/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
* @{
*/
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) /*!< Regular conversions hardware trigger detection disabled */
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0) /*!< Regular conversions hardware trigger detection on the rising edge */
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1) /*!< Regular conversions hardware trigger detection on the falling edge */
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN) /*!< Regular conversions hardware trigger detection on both the rising and falling edges */
#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000) /*!< Regular conversions hardware trigger detection disabled */
#define ADC_EXTERNALTRIGCONVEDGE_RISING (ADC_CFGR_EXTEN_0) /*!< Regular conversions hardware trigger detection on the rising edge */
#define ADC_EXTERNALTRIGCONVEDGE_FALLING (ADC_CFGR_EXTEN_1) /*!< Regular conversions hardware trigger detection on the falling edge */
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (ADC_CFGR_EXTEN) /*!< Regular conversions hardware trigger detection on both the rising and falling edges */
/**
* @}
*/
@ -502,40 +500,40 @@ typedef struct
/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
* @{
*/
#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) /*!< End of unitary conversion flag */
#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) /*!< End of sequence conversions flag */
#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */
#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */
/**
* @}
*/
/** @defgroup ADC_Overrun ADC overrun
/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
* @{
*/
#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000) /*!< Data preserved in case of overrun */
#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR_OVRMOD) /*!< Data overwritten in case of overrun */
#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */
#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */
/**
* @}
*/
/** @defgroup ADC_regular_rank ADC group regular sequencer rank
/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
* @{
*/
#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /*!< ADC regular conversion rank 1 */
#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /*!< ADC regular conversion rank 2 */
#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /*!< ADC regular conversion rank 3 */
#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /*!< ADC regular conversion rank 4 */
#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /*!< ADC regular conversion rank 5 */
#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /*!< ADC regular conversion rank 6 */
#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /*!< ADC regular conversion rank 7 */
#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /*!< ADC regular conversion rank 8 */
#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /*!< ADC regular conversion rank 9 */
#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /*!< ADC regular conversion rank 10 */
#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /*!< ADC regular conversion rank 11 */
#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /*!< ADC regular conversion rank 12 */
#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /*!< ADC regular conversion rank 13 */
#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /*!< ADC regular conversion rank 14 */
#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /*!< ADC regular conversion rank 15 */
#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /*!< ADC regular conversion rank 16 */
#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */
#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */
#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */
#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */
#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */
#define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */
#define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */
#define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */
#define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */
#define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */
#define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
#define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
#define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
/**
* @}
*/
@ -543,71 +541,69 @@ typedef struct
/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
* @{
*/
#define ADC_SAMPLETIME_2CYCLES_5 (0x00000000U) /*!< Sampling time 2.5 ADC clock cycles */
#define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */
#define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */
#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */
#define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */
#define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */
#define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */
#define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */
#define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */
#if defined(ADC_SMPR1_SMPPLUS)
#define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */
#define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */
#endif
#define ADC_SAMPLETIME_6CYCLES_5 (ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
#define ADC_SAMPLETIME_12CYCLES_5 (ADC_SMPR2_SMP10_1) /*!< Sampling time 12.5 ADC clock cycles */
#define ADC_SAMPLETIME_24CYCLES_5 ((ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 24.5 ADC clock cycles */
#define ADC_SAMPLETIME_47CYCLES_5 (ADC_SMPR2_SMP10_2) /*!< Sampling time 47.5 ADC clock cycles */
#define ADC_SAMPLETIME_92CYCLES_5 ((ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 92.5 ADC clock cycles */
#define ADC_SAMPLETIME_247CYCLES_5 ((ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1)) /*!< Sampling time 247.5 ADC clock cycles */
#define ADC_SAMPLETIME_640CYCLES_5 (ADC_SMPR2_SMP10) /*!< Sampling time 640.5 ADC clock cycles */
/**
* @}
*/
/** @defgroup ADC_channels ADC channels
/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number
* @{
*/
#define ADC_CHANNEL_0 ((uint32_t)(0x00000000)) /*!< ADC channel 0 */
#define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0)) /*!< ADC channel 1 */
#define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1)) /*!< ADC channel 2 */
#define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 3 */
#define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2)) /*!< ADC channel 4 */
#define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0)) /*!< ADC channel 5 */
#define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1)) /*!< ADC channel 6 */
#define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 7 */
#define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3)) /*!< ADC channel 8 */
#define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0)) /*!< ADC channel 9 */
#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1)) /*!< ADC channel 10 */
#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 11 */
#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2)) /*!< ADC channel 12 */
#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0)) /*!< ADC channel 13 */
#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1)) /*!< ADC channel 14 */
#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 15 */
#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4)) /*!< ADC channel 16 */
#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0)) /*!< ADC channel 17 */
#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1)) /*!< ADC channel 18 */
/* Note: VrefInt, TempSensor and Vbat internal channels are not available on */
/* all ADC instances (refer to Reference Manual). */
#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_17 /*!< ADC temperature sensor channel */
#define ADC_CHANNEL_VBAT ADC_CHANNEL_18 /*!< ADC Vbat channel */
#define ADC_CHANNEL_VREFINT ADC_CHANNEL_0 /*!< ADC Vrefint channel */
#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */
#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */
#if defined(ADC1) && !defined(ADC2)
#define ADC_CHANNEL_DAC1CH1 (ADC_CHANNEL_17) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, they cannot be used both simultenaeously. */
#define ADC_CHANNEL_DAC1CH2 (ADC_CHANNEL_18) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, they cannot be used both simultenaeously. */
#define ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_DAC1CH1) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
#define ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_DAC1CH2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
#elif defined(ADC2)
#define ADC_CHANNEL_DAC1CH1_ADC2 (ADC_CHANNEL_17) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
#define ADC_CHANNEL_DAC1CH2_ADC2 (ADC_CHANNEL_18) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
#define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
#define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
#if defined(ADC3)
#define ADC_CHANNEL_DAC1CH1_ADC3 (ADC_CHANNEL_14) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */
#define ADC_CHANNEL_DAC1CH2_ADC3 (ADC_CHANNEL_15) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */
#define ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_DAC1CH1_ADC3) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */
#define ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_DAC1CH2_ADC3) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */
#endif
#endif
/**
* @}
*/
/** @defgroup ADC_analog_watchdog_number ADC Analog Watchdog Selection
/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
* @{
*/
#define ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001) /*!< Analog watchdog 1 selection */
#define ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002) /*!< Analog watchdog 2 selection */
#define ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003) /*!< Analog watchdog 3 selection */
#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
/**
* @}
*/
@ -615,85 +611,85 @@ typedef struct
/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
* @{
*/
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000) /*!< No analog watchdog selected */
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)) /*!< Analog watchdog applied to a regular group single channel */
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to an injected group single channel */
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to a regular and injected groups single channel */
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */
#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to regular and injected groups all channels */
#define ADC_ANALOGWATCHDOG_NONE (0x00000000U) /*!< No analog watchdog selected */
#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */
#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */
#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */
/**
* @}
*/
/** @defgroup ADC_Oversampling_Ratio ADC Oversampling Ratio
/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
* @{
*/
#define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000) /*!< ADC Oversampling ratio 2x */
#define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)ADC_CFGR2_OVSR_0) /*!< ADC Oversampling ratio 4x */
#define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)ADC_CFGR2_OVSR_1) /*!< ADC Oversampling ratio 8x */
#define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)(ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)) /*!< ADC Oversampling ratio 16x */
#define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)ADC_CFGR2_OVSR_2) /*!< ADC Oversampling ratio 32x */
#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)) /*!< ADC Oversampling ratio 64x */
#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1)) /*!< ADC Oversampling ratio 128x */
#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)(ADC_CFGR2_OVSR)) /*!< ADC Oversampling ratio 256x */
#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
/**
* @}
*/
/** @defgroup ADC_Right_Bit_Shift ADC Oversampling Right Shift
/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
* @{
*/
#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */
#define ADC_RIGHTBITSHIFT_1 ((uint32_t)ADC_CFGR2_OVSS_0) /*!< ADC 1 bit shift for oversampling */
#define ADC_RIGHTBITSHIFT_2 ((uint32_t)ADC_CFGR2_OVSS_1) /*!< ADC 2 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)) /*!< ADC 3 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_4 ((uint32_t)ADC_CFGR2_OVSS_2) /*!< ADC 4 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)) /*!< ADC 5 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1)) /*!< ADC 6 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)) /*!< ADC 7 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_8 ((uint32_t)ADC_CFGR2_OVSS_3) /*!< ADC 8 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
/**
* @}
*/
/** @defgroup ADC_Triggered_Oversampling_Mode ADC Triggered Regular Oversampling
/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
* @{
*/
#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000) /*!< A single trigger for all channel oversampled conversions */
#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)ADC_CFGR2_TROVS) /*!< A trigger for each oversampled conversion */
#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
/**
* @}
*/
/** @defgroup ADC_Regular_Oversampling_Mode ADC Regular Oversampling Continued or Resumed Mode
/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular
* @{
*/
#define ADC_REGOVERSAMPLING_CONTINUED_MODE ((uint32_t)0x00000000) /*!< Oversampling buffer maintained during injection sequence */
#define ADC_REGOVERSAMPLING_RESUMED_MODE ((uint32_t)ADC_CFGR2_ROVSM) /*!< Oversampling buffer zeroed during injection sequence */
#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */
#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */
/**
* @}
*/
/** @defgroup ADC_Event_type ADC Event Type
/** @defgroup ADC_Event_type ADC Event type
* @{
*/
#define ADC_EOSMP_EVENT ((uint32_t)ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
#define ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
#define ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
#define ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */
#define ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
/**
* @}
*/
#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
/** @defgroup ADC_interrupts_definition ADC interrupts definition
* @{
*/
#define ADC_IT_RDY ADC_IER_ADRDY /*!< ADC Ready (ADRDY) interrupt source */
#define ADC_IT_RDY ADC_IER_ADRDY /*!< ADC Ready interrupt source */
#define ADC_IT_EOSMP ADC_IER_EOSMP /*!< ADC End of sampling interrupt source */
#define ADC_IT_EOC ADC_IER_EOC /*!< ADC End of regular conversion interrupt source */
#define ADC_IT_EOS ADC_IER_EOS /*!< ADC End of regular sequence of conversions interrupt source */
@ -711,7 +707,7 @@ typedef struct
* @}
*/
/** @defgroup ADC_flags_definition ADC Flags Definition
/** @defgroup ADC_flags_definition ADC flags definition
* @{
*/
#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
@ -759,15 +755,16 @@ typedef struct
* @param __HANDLE__ ADC handle
* @retval SET (software start) or RESET (external trigger)
*/
#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
(((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
(((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
/**
* @brief Return resolution bits in CFGR register RES[1:0] field.
* @param __HANDLE__ ADC handle
* @retval 2-bit field RES of CFGR register.
* @retval Value of bitfield RES in CFGR register.
*/
#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)
#define ADC_GET_RESOLUTION(__HANDLE__) \
(LL_ADC_GetResolution((__HANDLE__)->Instance))
/**
* @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
@ -792,8 +789,7 @@ typedef struct
* @retval SET (conversion is on going) or RESET (no conversion is on going)
*/
#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
(( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
) ? RESET : SET)
(LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance))
/**
* @brief Simultaneously clear and set specific bits of the handle State.
@ -811,17 +807,17 @@ typedef struct
* @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
*/
#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \
(((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \
(((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \
(((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= ((uint32_t)0x003F))) )
((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= (0x0FFF))) || \
(((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= (0x03FF))) || \
(((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= (0x00FF))) || \
(((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= (0x003F))) )
/**
* @brief Verify the length of the scheduled regular conversions group.
* @param __LENGTH__ number of programmed conversions.
* @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
*/
#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (16U)))
/**
@ -829,7 +825,7 @@ typedef struct
* @param NUMBER number of scheduled regular conversions in discontinuous mode.
* @retval SET (NUMBER is within the maximum number of regular conversions in discontinous mode) or RESET (NUMBER is null or too large)
*/
#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))
/**
@ -919,7 +915,6 @@ typedef struct
((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
\
((__REGTRIG__) == ADC_SOFTWARE_START) )
/**
@ -1004,12 +999,12 @@ typedef struct
/* Minimum ADC Clock frequency is 0.14 MHz */
/* Maximum conversion time is */
/* 653 / 0.14 MHz = 4.66 ms */
#define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 5) /*!< ADC stop time-out value */
#define ADC_STOP_CONVERSION_TIMEOUT ( 5U) /*!< ADC stop time-out value */
/* Delay for temperature sensor stabilization time. */
/* Maximum delay is 120us (refer device datasheet, parameter tSTART). */
/* Unit: us */
#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 120)
#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
/**
* @}
@ -1039,17 +1034,17 @@ typedef struct
* @param __HANDLE__ ADC handle
* @param __INTERRUPT__ ADC Interrupt
* This parameter can be one of the following values:
* @arg @ref ADC_IT_RDY, ADC Ready (ADRDY) interrupt source
* @arg @ref ADC_IT_EOSMP, ADC End of Sampling interrupt source
* @arg @ref ADC_IT_EOC, ADC End of Regular Conversion interrupt source
* @arg @ref ADC_IT_EOS, ADC End of Regular sequence of Conversions interrupt source
* @arg @ref ADC_IT_OVR, ADC overrun interrupt source
* @arg @ref ADC_IT_JEOC, ADC End of Injected Conversion interrupt source
* @arg @ref ADC_IT_JEOS, ADC End of Injected sequence of Conversions interrupt source
* @arg @ref ADC_IT_AWD1, ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2, ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3, ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_JQOVF, ADC Injected Context Queue Overflow interrupt source.
* @arg @ref ADC_IT_RDY ADC Ready interrupt source
* @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
* @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
* @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
* @arg @ref ADC_IT_OVR ADC overrun interrupt source
* @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
* @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
* @retval None
*/
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
@ -1060,17 +1055,17 @@ typedef struct
* @param __HANDLE__ ADC handle
* @param __INTERRUPT__ ADC Interrupt
* This parameter can be one of the following values:
* @arg @ref ADC_IT_RDY, ADC Ready (ADRDY) interrupt source
* @arg @ref ADC_IT_EOSMP, ADC End of Sampling interrupt source
* @arg @ref ADC_IT_EOC, ADC End of Regular Conversion interrupt source
* @arg @ref ADC_IT_EOS, ADC End of Regular sequence of Conversions interrupt source
* @arg @ref ADC_IT_OVR, ADC overrun interrupt source
* @arg @ref ADC_IT_JEOC, ADC End of Injected Conversion interrupt source
* @arg @ref ADC_IT_JEOS, ADC End of Injected sequence of Conversions interrupt source
* @arg @ref ADC_IT_AWD1, ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2, ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3, ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_JQOVF, ADC Injected Context Queue Overflow interrupt source.
* @arg @ref ADC_IT_RDY ADC Ready interrupt source
* @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
* @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
* @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
* @arg @ref ADC_IT_OVR ADC overrun interrupt source
* @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
* @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
* @retval None
*/
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
@ -1080,17 +1075,17 @@ typedef struct
* @param __HANDLE__ ADC handle
* @param __INTERRUPT__ ADC interrupt source to check
* This parameter can be one of the following values:
* @arg @ref ADC_IT_RDY, ADC Ready (ADRDY) interrupt source
* @arg @ref ADC_IT_EOSMP, ADC End of Sampling interrupt source
* @arg @ref ADC_IT_EOC, ADC End of Regular Conversion interrupt source
* @arg @ref ADC_IT_EOS, ADC End of Regular sequence of Conversions interrupt source
* @arg @ref ADC_IT_OVR, ADC overrun interrupt source
* @arg @ref ADC_IT_JEOC, ADC End of Injected Conversion interrupt source
* @arg @ref ADC_IT_JEOS, ADC End of Injected sequence of Conversions interrupt source
* @arg @ref ADC_IT_AWD1, ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2, ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3, ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_JQOVF, ADC Injected Context Queue Overflow interrupt source.
* @arg @ref ADC_IT_RDY ADC Ready interrupt source
* @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
* @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
* @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
* @arg @ref ADC_IT_OVR ADC overrun interrupt source
* @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
* @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
* @retval State of interruption (SET or RESET)
*/
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
@ -1101,17 +1096,17 @@ typedef struct
* @param __HANDLE__ ADC handle
* @param __FLAG__ ADC flag
* This parameter can be one of the following values:
* @arg @ref ADC_FLAG_RDY, ADC Ready (ADRDY) flag
* @arg @ref ADC_FLAG_EOSMP, ADC End of Sampling flag
* @arg @ref ADC_FLAG_EOC, ADC End of Regular Conversion flag
* @arg @ref ADC_FLAG_EOS, ADC End of Regular sequence of Conversions flag
* @arg @ref ADC_FLAG_OVR, ADC overrun flag
* @arg @ref ADC_FLAG_JEOC, ADC End of Injected Conversion flag
* @arg @ref ADC_FLAG_JEOS, ADC End of Injected sequence of Conversions flag
* @arg @ref ADC_FLAG_AWD1, ADC Analog watchdog 1 flag (main analog watchdog)
* @arg @ref ADC_FLAG_AWD2, ADC Analog watchdog 2 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_AWD3, ADC Analog watchdog 3 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_JQOVF, ADC Injected Context Queue Overflow flag.
* @arg @ref ADC_FLAG_RDY ADC Ready flag
* @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
* @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
* @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
* @arg @ref ADC_FLAG_OVR ADC overrun flag
* @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
* @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
* @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
* @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
* @retval State of flag (TRUE or FALSE).
*/
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
@ -1122,18 +1117,17 @@ typedef struct
* @param __HANDLE__ ADC handle
* @param __FLAG__ ADC flag
* This parameter can be one of the following values:
* @arg @ref ADC_FLAG_RDY, ADC Ready (ADRDY) flag
* @arg @ref ADC_FLAG_EOSMP, ADC End of Sampling flag
* @arg @ref ADC_FLAG_EOC, ADC End of Regular Conversion flag
* @arg @ref ADC_FLAG_EOS, ADC End of Regular sequence of Conversions flag
* @arg @ref ADC_FLAG_OVR, ADC overrun flag
* @arg @ref ADC_FLAG_JEOC, ADC End of Injected Conversion flag
* @arg @ref ADC_FLAG_JEOS, ADC End of Injected sequence of Conversions flag
* @arg @ref ADC_FLAG_AWD1, ADC Analog watchdog 1 flag (main analog watchdog)
* @arg @ref ADC_FLAG_AWD2, ADC Analog watchdog 2 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_AWD3, ADC Analog watchdog 3 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_JQOVF, ADC Injected Context Queue Overflow flag.
* @note Bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR).
* @arg @ref ADC_FLAG_RDY ADC Ready flag
* @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
* @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
* @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
* @arg @ref ADC_FLAG_OVR ADC overrun flag
* @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
* @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
* @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
* @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
* @retval None
*/
/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
@ -1198,7 +1192,7 @@ typedef struct
* @retval Value between Min_Data=0 and Max_Data=18
*/
#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
__LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)
__LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
/**
* @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x
@ -1250,7 +1244,7 @@ typedef struct
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
__LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
__LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
/**
* @brief Helper macro to determine whether the selected channel
@ -1311,7 +1305,7 @@ typedef struct
* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
*/
#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
__LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)
__LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
/**
* @brief Helper macro to convert a channel defined from parameter
@ -1386,7 +1380,7 @@ typedef struct
* @arg @ref ADC_CHANNEL_18
*/
#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)
__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
/**
* @brief Helper macro to determine whether the internal channel
@ -1423,7 +1417,7 @@ typedef struct
* Value "1" if the internal channel selected is available on the ADC instance selected.
*/
#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
__LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)
__LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
#if defined(ADC_MULTIMODE_SUPPORT)
/**
@ -1440,7 +1434,7 @@ typedef struct
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
__LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)
__LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
#endif
/**
@ -1454,7 +1448,7 @@ typedef struct
* @retval ADC common register instance
*/
#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \
__LL_ADC_COMMON_INSTANCE(__ADCx__)
__LL_ADC_COMMON_INSTANCE((__ADCx__))
/**
* @brief Helper macro to check if all ADC instances sharing the same
@ -1474,7 +1468,7 @@ typedef struct
* is enabled.
*/
#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)
__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
/**
* @brief Helper macro to define the ADC conversion data full-scale digital
@ -1490,7 +1484,7 @@ typedef struct
* @retval ADC conversion data equivalent voltage value (unit: mVolt)
*/
#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
__LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)
__LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
/**
* @brief Helper macro to convert the ADC conversion data from
@ -1513,9 +1507,9 @@ typedef struct
#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
__ADC_RESOLUTION_CURRENT__,\
__ADC_RESOLUTION_TARGET__) \
__LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
__ADC_RESOLUTION_CURRENT__,\
__ADC_RESOLUTION_TARGET__)
__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
(__ADC_RESOLUTION_CURRENT__),\
(__ADC_RESOLUTION_TARGET__))
/**
* @brief Helper macro to calculate the voltage (unit: mVolt)
@ -1536,9 +1530,9 @@ typedef struct
#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
__ADC_DATA__,\
__ADC_RESOLUTION__) \
__LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
__ADC_DATA__,\
__ADC_RESOLUTION__)
__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
(__ADC_DATA__),\
(__ADC_RESOLUTION__))
/**
* @brief Helper macro to calculate analog reference voltage (Vref+)
@ -1567,8 +1561,8 @@ typedef struct
*/
#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
__ADC_RESOLUTION__) \
__LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
__ADC_RESOLUTION__)
__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
(__ADC_RESOLUTION__))
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@ -1618,9 +1612,9 @@ typedef struct
#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
__ADC_RESOLUTION__) \
__LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
__ADC_RESOLUTION__)
__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
(__TEMPSENSOR_ADC_DATA__),\
(__ADC_RESOLUTION__))
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@ -1672,12 +1666,12 @@ typedef struct
__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
__ADC_RESOLUTION__) \
__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
__TEMPSENSOR_TYP_CALX_V__,\
__TEMPSENSOR_CALX_TEMP__,\
__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
__ADC_RESOLUTION__)
__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
(__TEMPSENSOR_TYP_CALX_V__),\
(__TEMPSENSOR_CALX_TEMP__),\
(__VREFANALOG_VOLTAGE__),\
(__TEMPSENSOR_ADC_DATA__),\
(__ADC_RESOLUTION__))
/**
* @}

362
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_adc_ex.h
View file

@ -63,10 +63,10 @@
typedef struct
{
uint32_t Ratio; /*!< Configures the oversampling ratio.
This parameter can be a value of @ref ADC_Oversampling_Ratio */
This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
This parameter can be a value of @ref ADC_Right_Bit_Shift */
This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
}ADC_InjOversamplingTypeDef;
/**
@ -88,11 +88,11 @@ typedef struct
typedef struct
{
uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected.
This parameter can be a value of @ref ADC_channels
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer.
This parameter must be a value of @ref ADCEx_injected_rank.
This parameter must be a value of @ref ADC_LL_EC_INJ_SEQ_RANKS.
Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
the new channel setting (or parameter number of conversions adjusted) */
@ -110,7 +110,7 @@ typedef struct
uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
This parameter must be a value of @ref ADCEx_SingleDifferential.
This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
It overwrites the last setting.
Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
@ -120,7 +120,7 @@ typedef struct
of another parameter update on the fly) */
uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
This parameter can be a value of @ref ADCEx_OffsetNumber.
This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
@ -196,14 +196,14 @@ typedef struct
typedef struct
{
uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode.
This parameter can be a value of @ref ADCEx_Common_mode. */
This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC:
selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multimode. */
This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */
uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases.
This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY.
Delay range depends on selected resolution:
from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits,
from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */
@ -224,23 +224,23 @@ typedef struct
* @{
*/
/* ADC group regular trigger sources for all ADC instances */
#define ADC_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000) /*!< Event 0 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) /*!< Event 1 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) /*!< Event 2 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 3 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) /*!< Event 4 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) /*!< Event 5 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) /*!< Event 6 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 7 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) /*!< Event 8 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0)) /*!< Event 9 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1)) /*!< Event 10 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 11 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2)) /*!< Event 12 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) /*!< Event 13 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) /*!< Event 14 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) /*!< Event 15 triggers injected group conversion start */
#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001) /*!< Software triggers injected group conversion start */
#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
/**
* @}
*/
@ -248,109 +248,99 @@ typedef struct
/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
* @{
*/
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000) /*!< Injected conversions hardware trigger detection disabled */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U) /*!< Injected conversions hardware trigger detection disabled */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */
/**
* @}
*/
/** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode
/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
* @{
*/
#define ADC_SINGLE_ENDED ((uint32_t)0x00000000) /*!< ADC channel set in single-ended input mode */
#define ADC_DIFFERENTIAL_ENDED ((uint32_t)ADC_CR_ADCALDIF) /*!< ADC channel set in differential mode */
#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
/**
* @}
*/
/** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number
/** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number
* @{
*/
#define ADC_OFFSET_NONE ((uint32_t)0x00) /*!< No offset correction */
#define ADC_OFFSET_1 ((uint32_t)0x01) /*!< Offset correction to apply to a first channel */
#define ADC_OFFSET_2 ((uint32_t)0x02) /*!< Offset correction to apply to a second channel */
#define ADC_OFFSET_3 ((uint32_t)0x03) /*!< Offset correction to apply to a third channel */
#define ADC_OFFSET_4 ((uint32_t)0x04) /*!< Offset correction to apply to a fourth channel */
#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */
#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
/**
* @}
*/
/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
* @{
*/
#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) /*!< ADC injected conversion rank 1 */
#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) /*!< ADC injected conversion rank 2 */
#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) /*!< ADC injected conversion rank 3 */
#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) /*!< ADC injected conversion rank 4 */
#define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */
#define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */
#define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */
#define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */
/**
* @}
*/
#if defined(ADC_MULTIMODE_SUPPORT)
/** @defgroup ADCEx_Common_mode ADC Extended multimode dual mode
/** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode
* @{
*/
#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000)) /*!< Independent ADC conversions mode */
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_0)) /*!< Combined regular simultaneous + injected simultaneous mode */
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_1)) /*!< Combined regular simultaneous + alternate trigger mode */
#define ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)) /*!< Combined Interleaved mode + injected simultaneous mode */
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)) /*!< Injected simultaneous mode only */
#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1)) /*!< Regular simultaneous mode only */
#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)) /*!< Interleaved mode only */
#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)) /*!< Alternate trigger mode only */
#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */
#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */
#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */
#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */
#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
/** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution
* @{
*/
#define ADC_DMAACCESSMODE_DISABLED (0x00000000U) /*!< DMA multimode disabled: each ADC uses its own DMA channel */
#define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */
#define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */
/**
* @}
*/
/** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA mode for multimode
/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
* @{
*/
#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA multimode disabled: each ADC uses its own DMA channel */
#define ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */
#define ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */
#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
/**
* @}
*/
/** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended delay between 2 sampling phases
* @{
*/
#define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000)) /*!< 1 ADC clock cycle delay */
#define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC_CCR_DELAY_0)) /*!< 2 ADC clock cycles delay */
#define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC_CCR_DELAY_1)) /*!< 3 ADC clock cycles delay */
#define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 4 ADC clock cycles delay */
#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC_CCR_DELAY_2)) /*!< 5 ADC clock cycles delay */
#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) /*!< 6 ADC clock cycles delay */
#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) /*!< 7 ADC clock cycles delay (lower for non 12-bit resolution) */
#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 8 ADC clock cycles delay (lower for non 12-bit resolution) */
#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC_CCR_DELAY_3)) /*!< 9 ADC clock cycles delay (lower for non 12-bit resolution) */
#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) /*!< 10 ADC clock cycles delay (lower for non 12-bit resolution) */
#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) /*!< 11 ADC clock cycles delay (lower for non 12-bit resolution) */
#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 12 ADC clock cycles delay (lower for non 12-bit resolution) */
/**
* @}
*/
#endif /* ADC_MULTIMODE_SUPPORT */
/** @defgroup ADCEx_conversion_group ADC Extended Conversion Group
/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
* @{
*/
#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS)) /*!< ADC regular group selection */
#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS)) /*!< ADC injected group selection */
#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS)) /*!< ADC regular and injected groups selection */
/**
* @}
*/
/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
* @{
*/
#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) /*!< ADC injected conversion rank 1 */
#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) /*!< ADC injected conversion rank 2 */
#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) /*!< ADC injected conversion rank 3 */
#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) /*!< ADC injected conversion rank 4 */
#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */
#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/
#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
/**
* @}
*/
@ -401,20 +391,20 @@ typedef struct
/* ADC_CFGR fields of parameters that can be updated when no conversion
(neither regular nor injected) is on-going */
#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY | ADC_CFGR_DFSDMCFG))
#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY | ADC_CFGR_DFSDMCFG))
#else
#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
#endif
/**
* @}
*/
#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
/** @defgroup ADCEx_DFSDM_Mode_Configuration ADC Extended DFSDM mode configuration
/** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data
* @{
*/
#define ADC_DFSDM_MODE_DISABLE (0x00000000U) /*!< ADC conversions are not transferred by DFSDM. */
#define ADC_DFSDM_MODE_ENABLE (ADC_CFGR_DFSDMCFG) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */
#define ADC_DFSDM_MODE_DISABLE (0x00000000U) /*!< ADC conversions are not transferred by DFSDM. */
#define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */
/**
* @}
*/
@ -446,7 +436,7 @@ typedef struct
* @retval None
*/
#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \
CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_DUAL)
LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
/**
* @}
@ -467,8 +457,8 @@ typedef struct
* @param __HANDLE__ ADC handle.
* @retval SET (software start) or RESET (external trigger).
*/
#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
(((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
(((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
/**
* @brief Check if conversion is on going on regular or injected groups.
@ -484,9 +474,8 @@ typedef struct
* @param __HANDLE__ ADC handle.
* @retval SET (conversion is on going) or RESET (no conversion is on going).
*/
#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \
(( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET \
) ? RESET : SET)
#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \
(LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance))
/**
* @brief Check whether or not ADC is independent.
@ -506,134 +495,13 @@ typedef struct
#define ADC_IS_INDEPENDENT(__HANDLE__) (SET)
#endif
/**
* @brief Set the sample time for Channels numbers between 0 and 9.
* @param __SAMPLETIME__ Sample time parameter.
* @param __CHANNELNB__ Channel number.
* @retval None
*/
#define ADC_SMPR1(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << (ADC_SMPR1_SMP1_Pos * (__CHANNELNB__)))
/**
* @brief Set the sample time for Channels numbers between 10 and 18.
* @param __SAMPLETIME__ Sample time parameter.
* @param __CHANNELNB__ Channel number.
* @retval None
*/
#define ADC_SMPR2(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << (ADC_SMPR2_SMP11_Pos * ((__CHANNELNB__) - 10)))
/**
* @brief Write SMPR1 register.
* @param __HANDLE__ ADC handle.
* @param __SAMPLETIME__ Sample time parameter.
* @param __CHANNELNB__ Channel number.
* @retval None
*/
#if defined(ADC_SMPR1_SMPPLUS)
#define ADC_SMPR1_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \
do { \
if((__SAMPLETIME__) == ADC_SAMPLETIME_3CYCLES_5) \
{ \
SET_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS); \
} \
else if ((__SAMPLETIME__) == ADC_SAMPLETIME_2CYCLES_5) \
{ \
CLEAR_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS); \
} \
MODIFY_REG((__HANDLE__)->Instance->SMPR1, \
ADC_SMPR1(ADC_SMPR1_SMP0, (__CHANNELNB__)), \
ADC_SMPR1((__SAMPLETIME__) & 0x7FFFFFFF, (__CHANNELNB__))); \
} while(0)
#else
#define ADC_SMPR1_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \
MODIFY_REG((__HANDLE__)->Instance->SMPR1, \
ADC_SMPR1(ADC_SMPR1_SMP0, (__CHANNELNB__)), \
ADC_SMPR1((__SAMPLETIME__), (__CHANNELNB__)))
#endif
/**
* @brief Write SMPR2 register.
* @param __HANDLE__ ADC handle.
* @param __SAMPLETIME__ Sample time parameter.
* @param __CHANNELNB__ Channel number.
* @retval None
*/
#if defined(ADC_SMPR1_SMPPLUS)
#define ADC_SMPR2_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \
do { \
if((__SAMPLETIME__) == ADC_SAMPLETIME_3CYCLES_5) \
{ \
SET_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS); \
} \
else if ((__SAMPLETIME__) == ADC_SAMPLETIME_2CYCLES_5) \
{ \
CLEAR_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS); \
} \
MODIFY_REG((__HANDLE__)->Instance->SMPR2, \
ADC_SMPR2(ADC_SMPR2_SMP10, (__CHANNELNB__)), \
ADC_SMPR2((__SAMPLETIME__) & 0x7FFFFFFF, (__CHANNELNB__))); \
} while(0)
#else
#define ADC_SMPR2_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \
MODIFY_REG((__HANDLE__)->Instance->SMPR2, \
ADC_SMPR2(ADC_SMPR2_SMP10, (__CHANNELNB__)), \
ADC_SMPR2((__SAMPLETIME__), (__CHANNELNB__)))
#endif
/**
* @brief Set the selected regular Channel rank for rank between 1 and 4.
* @param __CHANNELNB__ Channel number.
* @param __RANKNB__ Rank number.
* @retval None
*/
#define ADC_SQR1_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (ADC_SQR1_SQ1_Pos * (__RANKNB__)))
/**
* @brief Set the selected regular Channel rank for rank between 5 and 9.
* @param __CHANNELNB__ Channel number.
* @param __RANKNB__ Rank number.
* @retval None
*/
#define ADC_SQR2_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (ADC_SQR2_SQ6_Pos * ((__RANKNB__) - 5)))
/**
* @brief Set the selected regular Channel rank for rank between 10 and 14.
* @param __CHANNELNB__ Channel number.
* @param __RANKNB__ Rank number.
* @retval None
*/
#define ADC_SQR3_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (ADC_SQR3_SQ11_Pos * ((__RANKNB__) - 10)))
/**
* @brief Set the selected regular Channel rank for rank between 15 and 16.
* @param __CHANNELNB__ Channel number.
* @param __RANKNB__ Rank number.
* @retval None
*/
#define ADC_SQR4_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (ADC_SQR4_SQ16_Pos * ((__RANKNB__) - 15)))
/**
* @brief Set the selected injected Channel rank.
* @param __CHANNELNB__ Channel number.
* @param __RANKNB__ Rank number.
* @retval None
*/
#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << ((ADC_JSQR_JSQ1_Pos-2) * (__RANKNB__) +2))
/**
* @brief Set the Analog Watchdog 1 channel.
* @param __CHANNEL__ channel to be monitored by Analog Watchdog 1.
* @retval None
*/
#define ADC_CFGR_SET_AWD1CH(__CHANNEL__) ((__CHANNEL__) << ADC_CFGR_AWD1CH_Pos)
/**
* @brief Configure the channel number in Analog Watchdog 2 or 3.
* @param __CHANNEL__ ADC Channel
* @retval None
*/
#define ADC_CFGR_SET_AWD23CR(__CHANNEL__) (1U << (__CHANNEL__))
#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
/**
* @brief Configure ADC injected context queue
@ -814,17 +682,6 @@ typedef struct
((__THRESHOLD__) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \
(__THRESHOLD__) << 2 )
/**
* @brief Report ADC common register.
* @param __HANDLE__ ADC handle.
* @retval Common control register
*/
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
#define ADC_COMMON_REGISTER(__HANDLE__) (ADC123_COMMON)
#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define ADC_COMMON_REGISTER(__HANDLE__) (ADC1_COMMON)
#endif
/**
* @brief Report Master Instance.
* @param __HANDLE__ ADC handle.
@ -850,7 +707,7 @@ typedef struct
* @retval None
*/
#if defined(ADC_MULTIMODE_SUPPORT)
#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE | \
#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \
ADC_CCR_PRESC | \
ADC_CCR_VBATEN | \
ADC_CCR_TSEN | \
@ -860,11 +717,12 @@ typedef struct
ADC_CCR_DELAY | \
ADC_CCR_DUAL )
#else
#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE | \
#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \
ADC_CCR_PRESC | \
ADC_CCR_VBATEN | \
ADC_CCR_TSEN | \
ADC_CCR_VREFEN )
#endif /* ADC_MULTIMODE_SUPPORT */
/**
@ -895,9 +753,9 @@ typedef struct
#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \
( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
)? \
( (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \
(((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \
(((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \
( (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \
(((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \
(((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \
: \
RESET \
)
@ -1057,15 +915,14 @@ typedef struct
* @param __LENGTH__ number of programmed conversions.
* @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
*/
#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
/**
* @brief Calibration factor size verification (7 bits maximum).
* @param __CALIBRATION_FACTOR__ Calibration factor value.
* @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
*/
#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= ((uint32_t)0x7F))
#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
/**
@ -1076,8 +933,7 @@ typedef struct
*/
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \
(((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \
((__CHANNEL__) == ADC_CHANNEL_1) || \
(((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
@ -1095,12 +951,14 @@ typedef struct
((__CHANNEL__) == ADC_CHANNEL_16) || \
((__CHANNEL__) == ADC_CHANNEL_17) || \
((__CHANNEL__) == ADC_CHANNEL_18) || \
((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \
((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
((__CHANNEL__) == ADC_CHANNEL_VBAT)))
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == ADC_CHANNEL_DAC1CH1) || \
((__CHANNEL__) == ADC_CHANNEL_DAC1CH2)))
#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \
(((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \
((__CHANNEL__) == ADC_CHANNEL_1) || \
(((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
@ -1116,6 +974,7 @@ typedef struct
((__CHANNEL__) == ADC_CHANNEL_14) || \
((__CHANNEL__) == ADC_CHANNEL_15) || \
((__CHANNEL__) == ADC_CHANNEL_16) || \
((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \
((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \
((((__HANDLE__)->Instance) == ADC2) && \
@ -1136,7 +995,9 @@ typedef struct
((__CHANNEL__) == ADC_CHANNEL_15) || \
((__CHANNEL__) == ADC_CHANNEL_16) || \
((__CHANNEL__) == ADC_CHANNEL_17) || \
((__CHANNEL__) == ADC_CHANNEL_18))) || \
((__CHANNEL__) == ADC_CHANNEL_18) || \
((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2) || \
((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2))) || \
((((__HANDLE__)->Instance) == ADC3) && \
(((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
@ -1153,7 +1014,9 @@ typedef struct
((__CHANNEL__) == ADC_CHANNEL_14) || \
((__CHANNEL__) == ADC_CHANNEL_15) || \
((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
((__CHANNEL__) == ADC_CHANNEL_VBAT) )))
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC3) || \
((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC3) )))
#endif
/**
@ -1264,8 +1127,8 @@ typedef struct
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
\
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
/**
* @brief Verify the ADC edge trigger setting for injected group.
* @param __EDGE__ programmed ADC edge trigger setting.
@ -1395,7 +1258,7 @@ typedef struct
* @brief Verify the ADC oversampling triggered mode.
* @param __MODE__ programmed ADC oversampling triggered mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
*/
#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
@ -1403,11 +1266,10 @@ typedef struct
* @brief Verify the ADC oversampling regular conversion resumed or continued mode.
* @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
*/
#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
/**
* @brief Verify the DFSDM mode configuration.
* @param __HANDLE__ ADC handle.

22
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_def.h
View file

@ -83,14 +83,14 @@ typedef enum
} while(0)
#define UNUSED(x) ((void)(x))
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function
* Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
@ -123,7 +123,7 @@ typedef enum
}while (0)
#endif /* USE_RTOS */
#if defined ( __GNUC__ )
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
@ -134,7 +134,7 @@ typedef enum
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__GNUC__) /* GNU Compiler */
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
@ -186,14 +186,14 @@ typedef enum
#endif
/**
/**
* @brief __NOINLINE definition
*/
*/
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
/* ARM & GNUCompiler
----------------
/* ARM & GNUCompiler
----------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler

4
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_dfsdm.h
View file

@ -501,13 +501,13 @@ typedef struct
*/
/** @brief Reset DFSDM channel handle state.
* @param __HANDLE__: DFSDM channel handle.
* @param __HANDLE__ DFSDM channel handle.
* @retval None
*/
#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
/** @brief Reset DFSDM filter handle state.
* @param __HANDLE__: DFSDM filter handle.
* @param __HANDLE__ DFSDM filter handle.
* @retval None
*/
#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)

715
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_dsi.h
View file

File diff suppressed because it is too large Load diff

5
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_gfxmmu.h
View file

@ -41,10 +41,11 @@
extern "C" {
#endif
#if defined(GFXMMU)
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
#if defined(GFXMMU)
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
@ -195,7 +196,7 @@ typedef struct
*/
/** @brief Reset GFXMMU handle state.
* @param __HANDLE__: GFXMMU handle.
* @param __HANDLE__ GFXMMU handle.
* @retval None
*/
#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXMMU_STATE_RESET)

6
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_i2c.h
View file

@ -335,9 +335,9 @@ typedef struct __I2C_HandleTypeDef
* @{
*/
#define I2C_NO_STARTSTOP (0x00000000U)
#define I2C_GENERATE_STOP I2C_CR2_STOP
#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE I2C_CR2_START
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/

6
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_ospi.h
View file

@ -41,11 +41,11 @@
extern "C" {
#endif
#if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2)
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
#if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2)
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
@ -697,7 +697,7 @@ typedef struct
* @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag
* @retval None
*/
#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) ? SET : RESET)
/** @brief Clears the specified OSPI's flag status.
* @param __HANDLE__: specifies the OSPI Handle.

22
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_qspi.h
View file

@ -41,11 +41,11 @@
extern "C" {
#endif
#if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2)
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
#if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2)
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
@ -204,10 +204,10 @@ typedef struct
/** @defgroup QSPI_ErrorCode QSPI Error Code
* @{
*/
#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */
#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */
#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */
#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */
#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */
#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */
#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008) /*!< Invalid parameters error */
/**
* @}
@ -324,7 +324,7 @@ typedef struct
/** @defgroup QSPI_DataMode QSPI Data Mode
* @{
*/
#define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/
#define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/
#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
@ -431,19 +431,19 @@ typedef struct
* @{
*/
/** @brief Reset QSPI handle state.
* @param __HANDLE__: QSPI handle.
* @param __HANDLE__ : QSPI handle.
* @retval None
*/
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
/** @brief Enable the QSPI peripheral.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __HANDLE__ : specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Disable the QSPI peripheral.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __HANDLE__ : specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
@ -501,7 +501,7 @@ typedef struct
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
* @retval None
*/
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) ? SET : RESET)
/** @brief Clears the specified QSPI's flag status.
* @param __HANDLE__: specifies the QSPI Handle.

2
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_rcc.h
View file

@ -1642,7 +1642,7 @@ typedef struct
#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET)
#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != RESET)
#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)

106
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_rcc_ex.h
View file

@ -52,7 +52,7 @@
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
* @{
@ -119,7 +119,7 @@ typedef struct
#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
uint32_t PLLSAI2Q; /*!< PLLSAI2Q: specifies the division factor for DSI clock.
This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
#endif
#endif
uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock.
This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
@ -190,7 +190,7 @@ typedef struct
uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source.
This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
#if defined(I2C4)
uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source.
@ -281,8 +281,8 @@ typedef struct
#if defined(CRS)
/**
* @brief RCC_CRS Init structure definition
/**
* @brief RCC_CRS Init structure definition
*/
typedef struct
{
@ -307,8 +307,8 @@ typedef struct
}RCC_CRSInitTypeDef;
/**
* @brief RCC_CRS Synchronization structure definition
/**
* @brief RCC_CRS Synchronization structure definition
*/
typedef struct
{
@ -318,12 +318,12 @@ typedef struct
uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
This parameter must be a number between 0 and 0x3F */
uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
value latched in the time of the last SYNC event.
This parameter must be a number between 0 and 0xFFFF */
uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
frequency error counter latched in the time of the last SYNC event.
uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
frequency error counter latched in the time of the last SYNC event.
It shows whether the actual frequency is below or above the target.
This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
@ -512,7 +512,7 @@ typedef struct
/**
* @}
*/
#if defined(I2C4)
/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source
* @{
@ -523,7 +523,7 @@ typedef struct
/**
* @}
*/
#endif /* I2C4 */
#endif /* I2C4 */
/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
* @{
@ -555,7 +555,7 @@ typedef struct
#define RCC_SAI2CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U)
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0
#define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1
#define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1
#define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0)
#define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2
#else
@ -595,13 +595,16 @@ typedef struct
* @{
*/
#if defined(RCC_HSI48_SUPPORT)
#define RCC_SDMMC1CLKSOURCE_HSI48 ((uint32_t)0x00000000U)
#define RCC_SDMMC1CLKSOURCE_HSI48 ((uint32_t)0x00000000U) /*!< HSI48 clock selected as SDMMC1 clock */
#else
#define RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000U)
#define RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000U) /*!< No clock selected as SDMMC1 clock */
#endif /* RCC_HSI48_SUPPORT */
#define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
#define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL
#define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 "Q" clock selected as SDMMC1 clock */
#define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL "Q" clock selected as SDMMC1 clock */
#define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock selected as SDMMC1 clock */
#if defined(RCC_CCIPR2_SDMMCSEL)
#define RCC_SDMMC1CLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLL "P" clock selected as SDMMC1 kernel clock */
#endif /* RCC_CCIPR2_SDMMCSEL */
/**
* @}
*/
@ -787,12 +790,12 @@ typedef struct
/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
* @{
*/
#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
/**
* @}
*/
/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
* @{
*/
@ -804,9 +807,9 @@ typedef struct
/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
* @{
*/
#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
corresponds to a higher output frequency */
corresponds to a higher output frequency */
/**
* @}
*/
@ -834,7 +837,7 @@ typedef struct
/**
* @}
*/
/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
* @{
*/
@ -914,7 +917,7 @@ typedef struct
((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \
((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \
(((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos))
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
#else
@ -934,7 +937,7 @@ typedef struct
(((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \
((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \
((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos))
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
@ -993,7 +996,7 @@ typedef struct
#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
#else
#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
@ -1119,7 +1122,7 @@ typedef struct
((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | \
(((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos))
# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
@ -1147,7 +1150,7 @@ typedef struct
((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \
((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
@ -1160,7 +1163,7 @@ typedef struct
WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
(((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \
((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos))
# endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */
#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
@ -1353,7 +1356,7 @@ typedef struct
* @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
* @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
*
* @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1
* @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1
* clock source when PLLs are disabled for devices without PLLSAI2.
*
*/
@ -1697,33 +1700,34 @@ typedef struct
@if STM32L486xx
* @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
* @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
* @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
* @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock
@endif
@if STM32L443xx
* @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
* @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
* @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
* @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock
@endif
@if STM32L4S9xx
* @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
* @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
* @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
* @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock
* @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" Clock selected as SDMMC1 clock
@endif
* @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock
* @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" Clock selected as SDMMC1 clock
* @retval None
*/
#if defined(RCC_CCIPR2_SDMMCSEL)
#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
do \
{ \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)); \
if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) \
if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \
{ \
SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \
} \
else \
{ \
CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)); \
} \
} while(0)
#else
@ -1747,12 +1751,13 @@ typedef struct
* @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
* @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
* @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
* @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 kernel clock
@endif
* @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
*/
#if defined(RCC_CCIPR2_SDMMCSEL)
#define __HAL_RCC_GET_SDMMC1_SOURCE() \
((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != RESET) ? RCC_SDMMC1CLKSOURCE_PLL : ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))))
((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != RESET) ? RCC_SDMMC1CLKSOURCE_PLLP : ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))))
#else
#define __HAL_RCC_GET_SDMMC1_SOURCE() \
((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
@ -2118,8 +2123,8 @@ typedef struct
do { \
__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
} while(0)
/**
* @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
* @retval None.
@ -2128,7 +2133,7 @@ typedef struct
do { \
__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
} while(0)
/**
* @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
@ -2265,7 +2270,7 @@ typedef struct
/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
* @{
*/
*/
/**
* @brief Enable the oscillator clock for frequency error counter.
* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
@ -2294,8 +2299,8 @@ typedef struct
/**
* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
* of the synchronization source after prescaling. It is then decreased by one in order to
* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
* of the synchronization source after prescaling. It is then decreased by one in order to
* reach the expected synchronization on the zero value. The formula is the following:
* RELOAD = (fTARGET / fSYNC) -1
* @param __FTARGET__ Target frequency (value in Hz)
@ -2715,7 +2720,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
(((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
#if defined(I2C4)
#define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \
@ -2783,7 +2788,16 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
#if defined(SDMMC1)
#if defined(RCC_HSI48_SUPPORT)
#if defined(RCC_HSI48_SUPPORT) && defined(RCC_CCIPR2_SDMMCSEL)
#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) || \
((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \
((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
#elif defined(RCC_HSI48_SUPPORT)
#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \
@ -2971,7 +2985,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))

48
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_rng.h
View file

@ -57,20 +57,15 @@
* @{
*/
#if defined(RNG_CR_CED) || defined(RNG_CR_BYP)
#if defined(RNG_CR_CED)
/**
* @brief RNG Configuration Structure definition
*/
typedef struct
{
#if defined(RNG_CR_CED)
uint32_t ClockErrorDetection; /*!< Clock error detection */
#endif /* defined(RNG_CR_CED) */
#if defined(RNG_CR_BYP)
uint32_t BypassMode; /*!< Bypass mode */
#endif /* defined(RNG_CR_BYP) */
}RNG_InitTypeDef;
#endif /* defined(RNG_CR_CED) || defined(RNG_CR_BYP) */
#endif /* defined(RNG_CR_CED) */
/**
* @brief RNG HAL State Structure definition
@ -82,7 +77,7 @@ typedef enum
HAL_RNG_STATE_BUSY = 0x02, /*!< RNG internal process is ongoing */
HAL_RNG_STATE_TIMEOUT = 0x03, /*!< RNG timeout state */
HAL_RNG_STATE_ERROR = 0x04 /*!< RNG error state */
}HAL_RNG_StateTypeDef;
/**
@ -91,17 +86,17 @@ typedef enum
typedef struct
{
RNG_TypeDef *Instance; /*!< Register base address */
#if defined(RNG_CR_CED) || defined(RNG_CR_BYP)
#if defined(RNG_CR_CED)
RNG_InitTypeDef Init; /*!< RNG configuration parameters */
#endif /* defined(RNG_CR_CED) || defined(RNG_CR_BYP) */
#endif /* defined(RNG_CR_CED) */
HAL_LockTypeDef Lock; /*!< RNG locking object */
__IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
uint32_t RandomNumber; /*!< Last Generated RNG Data */
}RNG_HandleTypeDef;
/**
@ -144,17 +139,6 @@ typedef struct
*/
#endif /* defined(RNG_CR_CED) */
#if defined(RNG_CR_BYP)
/** @defgroup RNG_Bypass_Mode RNG Bypass Mode
* @{
*/
#define RNG_BYP_DISABLE ((uint32_t)0x00000000) /*!< Bypass mode disabled */
#define RNG_BYP_ENABLE RNG_CR_BYP /*!< Bypass mode enabled */
/**
* @}
*/
#endif /* defined(RNG_CR_BYP) */
/**
* @}
*/
@ -215,7 +199,7 @@ typedef struct
* @retval None
*/
#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
/**
* @brief Disable the RNG interrupt.
* @param __HANDLE__: RNG Handle
@ -318,17 +302,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
#define IS_RNG_CED(__MODE__) (((__MODE__) == RNG_CED_ENABLE) || \
((__MODE__) == RNG_CED_DISABLE))
#endif /* defined(RNG_CR_CED) */
#if defined(RNG_CR_BYP)
/**
* @brief Verify the RNG Bypass mode.
* @param __MODE__: RNG Bypass mode
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_RNG_BYPASS(__MODE__) (((__MODE__) == RNG_BYP_ENABLE) || \
((__MODE__) == RNG_BYP_DISABLE))
#endif /* defined(RNG_CR_BYP) */
/**
* @}
*/

6
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_smbus.h
View file

@ -279,9 +279,9 @@ typedef struct
*/
#define SMBUS_NO_STARTSTOP (0x00000000U)
#define SMBUS_GENERATE_STOP I2C_CR2_STOP
#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define SMBUS_GENERATE_START_WRITE I2C_CR2_START
#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/

31
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_dac.h
View file

@ -267,14 +267,29 @@ typedef struct
/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
* @{
*/
#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
#if defined (DAC_CR_TSEL1_3)
#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM1 TRGO. */
#define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
#define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
#define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
#define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */
#define LL_DAC_TRIG_EXT_LPTIM1_OUT_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: LPTIM1 OUT TRGO. */
#define LL_DAC_TRIG_EXT_LPTIM2_OUT_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: LPTIM2 OUT TRGO. */
#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
#define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */
#else
#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
#endif
/**
* @}

22
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_i2c.h
View file

@ -281,14 +281,14 @@ typedef struct
/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
* @{
*/
#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
#define LL_I2C_GENERATE_STOP I2C_CR2_STOP /*!< Generate Stop condition (Size should be set to 0). */
#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */
#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /*!< Generate Start for write request. */
#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 7Bit address. */
#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 10Bit address.*/
#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */
#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */
#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */
#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */
#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/
/**
* @}
*/
@ -1097,7 +1097,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
* @retval None
*/
__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
uint32_t TimeoutB)
uint32_t TimeoutB)
{
MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
@ -2104,9 +2104,9 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
* @retval None
*/
__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
{
MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request);
}

110
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_rcc.h
View file

@ -128,7 +128,7 @@ typedef struct
/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
* @brief Defines used to adapt values of different oscillators
* @note These values could be modified in the user environment according to
* @note These values could be modified in the user environment according to
* HW set-up.
* @{
*/
@ -522,13 +522,20 @@ typedef struct
* @}
*/
#if defined(RCC_CCIPR2_SDMMCSEL)
/** @defgroup RCC_LL_EC_SDMMC1_KERNELCLKSOURCE Peripheral SDMMC kernel clock source selection
* @{
*/
#define LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK 0x00000000U /*!< 48MHz clock from internal multiplexor used as SDMMC1 clock source */
#define LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLLSAI3CLK clock used as SDMMC1 clock source */
/**
* @}
*/
#endif /* RCC_CCIPR2_SDMMCSEL */
/** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection
* @{
*/
#if defined(RCC_CCIPR2_SDMMCSEL)
#define LL_RCC_SDMMC1_CLKSOURCE_48CLK 0x00000000U /*!< 48MHz clock used as SDMMC1 clock source */
#define LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR2_SDMMCSEL /*!< PLL clock used as SDMMC1 clock source */
#else
#if defined(RCC_HSI48_SUPPORT)
#define LL_RCC_SDMMC1_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as SDMMC1 clock source */
#else
@ -537,7 +544,6 @@ typedef struct
#define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as SDMMC1 clock source */
#define LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as SDMMC1 clock source */
#define LL_RCC_SDMMC1_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as SDMMC1 clock source */
#endif /* RCC_CCIPR2_SDMMCSEL */
/**
* @}
*/
@ -739,14 +745,20 @@ typedef struct
* @}
*/
#if defined(RCC_CCIPR2_SDMMCSEL)
/** @defgroup RCC_LL_EC_SDMMC1_KERNEL Peripheral SDMMC get kernel clock source
* @{
*/
#define LL_RCC_SDMMC1_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /*!< SDMMC1 Kernel Clock source selection */
/**
* @}
*/
#endif /* RCC_CCIPR2_SDMMCSEL */
/** @defgroup RCC_LL_EC_SDMMC1 Peripheral SDMMC get clock source
* @{
*/
#if defined(RCC_CCIPR2_SDMMCSEL)
#define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR2_SDMMCSEL /*!< SDMMC1 Clock source selection */
#else
#define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< SDMMC1 Clock source selection */
#endif /* RCC_CCIPR2_SDMMCSEL */
/**
* @}
*/
@ -2195,7 +2207,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
/**
* @brief Get HSI48 Calibration value
* @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
* @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
*/
__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
{
@ -2900,7 +2912,7 @@ __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
*/
__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
{
__IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
__IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
MODIFY_REG(*reg, 3U << ((I2CxSource & 0x00FF0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x00FF0000U) >> 16U)));
}
@ -2952,31 +2964,39 @@ __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
#endif /* RCC_CCIPR2_SAI1SEL */
}
#if defined(RCC_CCIPR2_SDMMCSEL)
/**
* @brief Configure SDMMC1 kernel clock source
* @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource
* @param SDMMCxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*)
* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource)
{
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource);
}
#endif /* RCC_CCIPR2_SDMMCSEL */
/**
* @brief Configure SDMMC1 clock source
@if STM32L4S9xx
* @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCClockSource
@else
* @rmtoll CCIPR CLK48SEL LL_RCC_SetSDMMCClockSource
@endif
* @param SDMMCxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*)
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_48CLK (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
{
#if defined(RCC_CCIPR2_SDMMCSEL)
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource);
#else
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource);
#endif /* RCC_CCIPR2_SDMMCSEL */
}
/**
@ -3233,7 +3253,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
*/
__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
{
__IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
__IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
return (uint32_t)((READ_BIT(*reg, 3U << ((I2Cx & 0x00FF0000U) >> 16U)) >> ((I2Cx & 0x00FF0000U) >> 16U)) | (I2Cx & 0xFFFF0000U));
}
@ -3260,7 +3280,11 @@ __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
/**
* @brief Get SAIx clock source
@if STM32L4S9xx
* @rmtoll CCIPR2 SAIxSEL LL_RCC_GetSAIClockSource
@else
* @rmtoll CCIPR SAIxSEL LL_RCC_GetSAIClockSource
@endif
* @param SAIx This parameter can be one of the following values:
* @arg @ref LL_RCC_SAI1_CLKSOURCE
* @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
@ -3287,13 +3311,27 @@ __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
#endif /* RCC_CCIPR2_SAI1SEL */
}
#if defined(RCC_CCIPR2_SDMMCSEL)
/**
* @brief Get SDMMCx kernel clock source
* @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource
* @param SDMMCx This parameter can be one of the following values:
* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*)
* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLL (*)
*
* (*) value not defined in all devices.
*/
__STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx));
}
#endif /* RCC_CCIPR2_SDMMCSEL */
/**
* @brief Get SDMMCx clock source
@if STM32L4S9xx
* @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCClockSource
@else
* @rmtoll CCIPR CLK48SEL LL_RCC_GetSDMMCClockSource
@endif
* @param SDMMCx This parameter can be one of the following values:
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE
* @retval Returned value can be one of the following values:
@ -3302,17 +3340,12 @@ __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*)
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_48CLK (*)
*
* (*) value not defined in all devices.
*/
__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
{
#if defined(RCC_CCIPR2_SDMMCSEL)
return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx));
#else
return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx));
#endif /* RCC_CCIPR2_SDMMCSEL */
}
/**
@ -4108,7 +4141,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
{
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q,
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q,
PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ);
}
#else
@ -4220,9 +4253,9 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t P
__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
{
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);
}
}
#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
/**
* @brief Configure PLLSAI1 used for SAI domain clock
@ -4369,7 +4402,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t P
__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
{
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R,
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R,
PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR);
}
#else
@ -4710,9 +4743,9 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void)
__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
{
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
PLLM | PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP);
}
}
#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
/**
* @brief Configure PLLSAI2 used for SAI domain clock
@ -5863,6 +5896,9 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
#if defined(RCC_CCIPR2_SDMMCSEL)
uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource);
#endif
uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
#if defined(USB_OTG_FS) || defined(USB)

63
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_rng.h
View file

@ -66,26 +66,18 @@ extern "C" {
*/
#if defined(RNG_CR_CED) || defined(RNG_CR_BYP)
#if defined(RNG_CR_CED)
/**
* @brief LL RNG Init Structure Definition
*/
typedef struct
{
#if defined(RNG_CR_CED)
uint32_t ClockErrorDetection; /*!< Clock error detection.
This parameter can be one value of @ref RNG_LL_CED.
This parameter can be modified using unitary functions @ref LL_RNG_EnableClkErrorDetect(). */
#endif /* defined(RNG_CR_CED) */
#if defined(RNG_CR_BYP)
uint32_t BypassMode; /*!< Bypass mode.
This parameter can be one value of @ref RNG_LL_Bypass.
This parameter can be modified using unitary functions @ref LL_RNG_EnableBypassMode(). */
#endif /* defined(RNG_CR_BYP) */
}LL_RNG_InitTypeDef;
#endif /* defined(RNG_CR_CED) || defined(RNG_CR_BYP) */
#endif /* defined(RNG_CR_CED) */
/**
* @}
@ -107,17 +99,7 @@ typedef struct
* @}
*/
#endif /* defined(RNG_CR_CED) */
#if defined(RNG_CR_BYP)
/** @defgroup RNG_LL_Bypass Bypass Mode
* @{
*/
#define LL_RNG_BYP_DISABLE ((uint32_t)0x00000000) /*!< Bypass mode disabled */
#define LL_RNG_BYP_ENABLE RNG_CR_BYP /*!< Bypass mode enabled */
/**
* @}
*/
#endif /* defined(RNG_CR_BYP) */
/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_RNG_ReadReg function
@ -255,40 +237,6 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx)
}
#endif /* defined(RNG_CR_CED) */
#if defined(RNG_CR_BYP)
/**
* @brief Enable RNG Bypass mode
* @rmtoll CR BYP LL_RNG_EnableBypassMode
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_EnableBypassMode(RNG_TypeDef *RNGx)
{
SET_BIT(RNGx->CR, RNG_CR_BYP);
}
/**
* @brief Disable RNG Clock Error Detection
* @rmtoll CR BYP LL_RNG_DisableBypassMode
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_DisableBypassMode(RNG_TypeDef *RNGx)
{
CLEAR_BIT(RNGx->CR, RNG_CR_BYP);
}
/**
* @brief Check if RNG Clock Error Detection is enabled
* @rmtoll CR BYP LL_RNG_IsEnabledBypassMode
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsEnabledBypassMode(RNG_TypeDef *RNGx)
{
return (READ_BIT(RNGx->CR, RNG_CR_BYP) == (RNG_CR_BYP));
}
#endif /* defined(RNG_CR_BYP) */
/**
* @}
@ -446,9 +394,10 @@ __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
* @{
*/
#if defined(RNG_CR_CED) || defined(RNG_CR_BYP)
#if defined(RNG_CR_CED)
ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
#endif /* defined(RNG_CR_CED) || defined(RNG_CR_BYP) */
void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
#endif /* defined(RNG_CR_CED) */
ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
/**

81
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_sdmmc.h
View file

@ -623,42 +623,38 @@ typedef struct
/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
* @{
*/
#define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL
#define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL
#define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT
#define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT
#define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR
#define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR
#define SDMMC_IT_CMDREND SDMMC_STA_CMDREND
#define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT
#define SDMMC_IT_DATAEND SDMMC_STA_DATAEND
#define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND
#define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE
#define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF
#define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF
#define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF
#define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE
#define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE
#define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT
#define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE
#define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE
#define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE
#define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE
#define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE
#define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE
#define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE
#define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE
#define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE
#define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE
#define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE
#define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE
#define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE
#define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE
#define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define SDMMC_IT_DHOLD SDMMC_STA_DHOLD
#define SDMMC_IT_DABORT SDMMC_STA_DABORT
#define SDMMC_IT_DPSMACT SDMMC_STA_DPSMACT
#define SDMMC_IT_CMDACT SDMMC_STA_CPSMACT
#define SDMMC_IT_BUSYD0 SDMMC_STA_BUSYD0
#define SDMMC_IT_BUSYD0END SDMMC_STA_BUSYD0END
#define SDMMC_IT_ACKFAIL SDMMC_STA_ACKFAIL
#define SDMMC_IT_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT
#define SDMMC_IT_VSWEND SDMMC_STA_VSWEND
#define SDMMC_IT_CKSTOP SDMMC_STA_CKSTOP
#define SDMMC_IT_IDMATE SDMMC_STA_IDMATE
#define SDMMC_IT_IDMABTC SDMMC_STA_IDMABTC
#define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE
#define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE
#define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE
#define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE
#define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE
#define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE
#define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE
#define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE
#else
#define SDMMC_IT_CMDACT SDMMC_STA_CMDACT
#define SDMMC_IT_TXACT SDMMC_STA_TXACT
#define SDMMC_IT_RXACT SDMMC_STA_RXACT
#define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL
#define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL
#define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE
#define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE
#define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE
#define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE
#define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE
#define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE
#define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/**
* @}
@ -713,11 +709,26 @@ typedef struct
SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\
SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\
SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC))
#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\
SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END))
#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\
SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\
SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\
SDMMC_FLAG_IDMABTC))
#else
#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
SDMMC_FLAG_DBCKEND))
SDMMC_FLAG_DBCKEND | SDMMC_FLAG_SDIOIT))
#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\
SDMMC_FLAG_CMDSENT))
#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\
SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DBCKEND))
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/**

34
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_tim.h
View file

@ -3647,11 +3647,11 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
* @rmtoll OR2 BKINE LL_TIM_EnableBreakInputSource\n
* OR2 BKCMP1E LL_TIM_EnableBreakInputSource\n
* OR2 BKCMP2E LL_TIM_EnableBreakInputSource\n
* OR2 BKDFBK0E LL_TIM_EnableBreakInputSource\n
* OR3 BKINE LL_TIM_EnableBreakInputSource\n
* OR3 BKCMP1E LL_TIM_EnableBreakInputSource\n
* OR3 BKCMP2E LL_TIM_EnableBreakInputSource\n
* OR3 BKDFBK0E LL_TIM_EnableBreakInputSource
* OR2 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
* OR3 BK2INE LL_TIM_EnableBreakInputSource\n
* OR3 BK2CMP1E LL_TIM_EnableBreakInputSource\n
* OR3 BK2CMP2E LL_TIM_EnableBreakInputSource\n
* OR3 BK2DF1BK0E LL_TIM_EnableBreakInputSource
* @param TIMx Timer instance
* @param BreakInput This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK_INPUT_BKIN
@ -3676,11 +3676,11 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B
* @rmtoll OR2 BKINE LL_TIM_DisableBreakInputSource\n
* OR2 BKCMP1E LL_TIM_DisableBreakInputSource\n
* OR2 BKCMP2E LL_TIM_DisableBreakInputSource\n
* OR2 BKDFBK0E LL_TIM_DisableBreakInputSource\n
* OR3 BKINE LL_TIM_DisableBreakInputSource\n
* OR3 BKCMP1E LL_TIM_DisableBreakInputSource\n
* OR3 BKCMP2E LL_TIM_DisableBreakInputSource\n
* OR3 BKDFBK0E LL_TIM_DisableBreakInputSource
* OR2 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
* OR3 BK2INE LL_TIM_DisableBreakInputSource\n
* OR3 BK2CMP1E LL_TIM_DisableBreakInputSource\n
* OR3 BK2CMP2E LL_TIM_DisableBreakInputSource\n
* OR3 BK2DF1BK0E LL_TIM_DisableBreakInputSource
* @param TIMx Timer instance
* @param BreakInput This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK_INPUT_BKIN
@ -3702,14 +3702,12 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t
* @brief Set the polarity of the break signal for the timer break input.
* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll OR2 BKINE LL_TIM_SetBreakInputSourcePolarity\n
* OR2 BKCMP1E LL_TIM_SetBreakInputSourcePolarity\n
* OR2 BKCMP2E LL_TIM_SetBreakInputSourcePolarity\n
* OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n
* OR3 BKINE LL_TIM_SetBreakInputSourcePolarity\n
* OR3 BKCMP1E LL_TIM_SetBreakInputSourcePolarity\n
* OR3 BKCMP2E LL_TIM_SetBreakInputSourcePolarity\n
* OR3 BKINP LL_TIM_SetBreakInputSourcePolarity
* @rmtoll OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n
* OR2 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
* OR2 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
* OR3 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
* OR3 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
* OR3 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
* @param TIMx Timer instance
* @param BreakInput This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK_INPUT_BKIN

2
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal.c
View file

@ -69,7 +69,7 @@
*/
#define __STM32L4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L4xx_HAL_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */
#define __STM32L4xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L4xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32L4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L4xx_HAL_VERSION ((__STM32L4xx_HAL_VERSION_MAIN << 24)\
|(__STM32L4xx_HAL_VERSION_SUB1 << 16)\

576
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_adc.c
View file

@ -274,13 +274,6 @@
ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
(neither regular nor injected) is on-going */
#define ADC_CFGR_WD_FIELDS ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN | \
ADC_CFGR_AWD1EN | ADC_CFGR_AWD1CH)) /*!< ADC_CFGR fields of Analog Watchdog parameters that can be updated when no
conversion (neither regular nor injected) is on-going */
#define ADC_OFR_FIELDS ((uint32_t)(ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN)) /*!< ADC_OFR fields of parameters that can be updated when no conversion
(neither regular nor injected) is on-going */
/* Delay to wait before setting ADEN once ADCAL has been reset
must be at least 4 ADC clock cycles.
@ -294,11 +287,6 @@
#define ADC_DISABLE_TIMEOUT ((uint32_t) 2) /*!< ADC disable time-out value */
/* Delay for ADC voltage regulator startup time */
/* Maximum delay is 10 microseconds */
/* (refer device RM, parameter Tadcvreg_stup). */
#define ADC_STAB_DELAY_US ((uint32_t) 10) /*!< ADC voltage regulator startup time */
/* Timeout to wait for current conversion on going to be completed. */
/* Timeout fixed to longest ADC conversion possible, for 1 channel: */
@ -372,9 +360,7 @@
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
ADC_Common_TypeDef *tmpADC_Common;
uint32_t tmpCFGR = 0;
uint32_t tmpCFGR = 0U;
__IO uint32_t wait_loop_index = 0;
/* Check ADC handle */
@ -428,27 +414,26 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
}
/* - Exit from deep-power-down mode and ADC voltage regulator enable */
/* Exit deep power down mode if still in that state */
if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
if(LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0U)
{
/* Exit deep power down mode */
CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
/* Disable ADC deep power down mode */
LL_ADC_DisableDeepPowerDown(hadc->Instance);
/* System was in deep power down mode, calibration must
be relaunched or a previously saved calibration factor
re-applied once the ADC voltage regulator is enabled */
}
if(HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0U)
{
/* Enable ADC internal voltage regulator */
SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
LL_ADC_EnableInternalRegulator(hadc->Instance);
/* Delay for ADC stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */
wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000 * 2)));
wait_loop_index = (LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (1000000 * 2)));
while(wait_loop_index != 0)
{
wait_loop_index--;
@ -458,7 +443,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
/* Verification that ADC voltage regulator is correctly enabled, whether */
/* or not ADC is coming from state reset (if any potential problem of */
/* clocking, voltage regulator would not be enabled). */
if(HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0U)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
@ -484,10 +469,6 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
/* Configuration of common ADC parameters */
/* Pointer to the common control register */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - clock configuration */
@ -511,8 +492,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
/* - internal measurement paths: Vbat, temperature sensor, Vref */
/* (set into HAL_ADC_ConfigChannel() or */
/* HAL_ADCEx_InjectedConfigChannel() ) */
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_PRESC|ADC_CCR_CKMODE, hadc->Init.ClockPrescaler);
LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
}
/* Configuration of ADC: */
@ -537,19 +517,19 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* - external trigger to start conversion Init.ExternalTrigConv */
/* - external trigger polarity Init.ExternalTrigConvEdge */
/* Note: parameter ExternalTrigConvEdge set to "trigger edge none" is */
/* equivalent to software start. */
if ((hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
&& (hadc->Init.ExternalTrigConvEdge != ADC_EXTERNALTRIGCONVEDGE_NONE))
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
{
tmpCFGR |= ( hadc->Init.ExternalTrigConv | hadc->Init.ExternalTrigConvEdge);
tmpCFGR |= ( (hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
| hadc->Init.ExternalTrigConvEdge
);
}
/* Update Configuration Register CFGR */
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
/* Update Configuration Register CFGR */
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular and injected groups: */
@ -561,9 +541,9 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
tmpCFGR = ( ADC_CFGR_DFSDM(hadc) |
ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait) |
ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
if (hadc->Init.OversamplingMode == ENABLE)
{
assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
@ -571,36 +551,31 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
|| (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
{
/* Multi trigger is not applicable to software-triggered conversions */
assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
}
/* Configuration of Oversampler: */
/* - Oversampling Ratio */
/* - Right bit shift */
/* - Triggered mode */
/* - Oversampling mode (continued/resumed) */
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
ADC_CFGR2_ROVSE |
hadc->Init.Oversampling.Ratio |
hadc->Init.Oversampling.RightBitShift |
hadc->Init.Oversampling.TriggeredMode |
hadc->Init.Oversampling.OversamplingStopReset);
/* Configuration of Oversampler: */
/* - Oversampling Ratio */
/* - Right bit shift */
/* - Triggered mode */
/* - Oversampling mode (continued/resumed) */
MODIFY_REG(hadc->Instance->CFGR2,
ADC_CFGR2_OVSR |
ADC_CFGR2_OVSS |
ADC_CFGR2_TROVS |
ADC_CFGR2_ROVSM,
ADC_CFGR2_ROVSE |
hadc->Init.Oversampling.Ratio |
hadc->Init.Oversampling.RightBitShift |
hadc->Init.Oversampling.TriggeredMode |
hadc->Init.Oversampling.OversamplingStopReset
);
}
else
{
/* Disable Regular OverSampling */
CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
/* Disable ADC oversampling scope on ADC group regular */
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
}
} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
/* Configuration of regular group sequencer: */
/* - if scan mode is disabled, regular channels sequence length is set to */
/* 0x00: 1 channel converted (channel on regular rank 1) */
@ -608,12 +583,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
/* Note: Scan mode is not present by hardware on this device, but */
/* emulated by software for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion" */
/* parameter "NbrOfConversion". */
if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
{
/* Set number of ranks in regular group sequencer */
MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
}
else
{
@ -971,7 +946,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
}
/* Start ADC group regular conversion */
SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
LL_ADC_REG_StartConversion(hadc->Instance);
}
else
{
@ -1475,7 +1450,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
}
/* Start ADC group regular conversion */
SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
LL_ADC_REG_StartConversion(hadc->Instance);
}
else
{
@ -1671,7 +1646,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
/* Start ADC group regular conversion */
SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
LL_ADC_REG_StartConversion(hadc->Instance);
}
else
{
@ -2218,7 +2193,6 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
ADC_Common_TypeDef *tmpADC_Common;
uint32_t tmpOffsetShifted;
__IO uint32_t wait_loop_index = 0;
@ -2254,121 +2228,93 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
/* - Channel rank */
if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
{
#if !defined (USE_FULL_ASSERT)
/* Correspondance for compatibility with legacy definition of */
/* sequencer ranks in direct number format. This correspondance can */
/* be done only on ranks 1 to 5 due to literal values. */
/* Note: Sequencer ranks in direct number format are no more used */
/* and are detected by activating USE_FULL_ASSERT feature. */
if (sConfig->Rank <= 5U)
{
switch (sConfig->Rank)
{
case 2U: sConfig->Rank = ADC_REGULAR_RANK_2; break;
case 3U: sConfig->Rank = ADC_REGULAR_RANK_3; break;
case 4U: sConfig->Rank = ADC_REGULAR_RANK_4; break;
case 5U: sConfig->Rank = ADC_REGULAR_RANK_5; break;
/* case 1U */
default: sConfig->Rank = ADC_REGULAR_RANK_1;
}
}
#endif
/* Regular sequence configuration */
/* Clear the old SQx bits then set the new ones for the selected rank */
/* For Rank 1 to 4 */
if (sConfig->Rank < 5)
{
MODIFY_REG(hadc->Instance->SQR1,
ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank),
ADC_SQR1_RK(sConfig->Channel, sConfig->Rank));
}
/* For Rank 5 to 9 */
else if (sConfig->Rank < 10)
/* Set ADC group regular sequence: channel on the selected scan sequence rank */
LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel sampling time */
/* - Channel offset */
if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
{
#if defined(ADC_SMPR1_SMPPLUS)
/* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
if(sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
{
MODIFY_REG(hadc->Instance->SQR2,
ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank),
ADC_SQR2_RK(sConfig->Channel, sConfig->Rank));
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
}
/* For Rank 10 to 14 */
else if (sConfig->Rank < 15)
{
MODIFY_REG(hadc->Instance->SQR3,
ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank),
ADC_SQR3_RK(sConfig->Channel, sConfig->Rank));
}
/* For Rank 15 to 16 */
else
{
MODIFY_REG(hadc->Instance->SQR4,
ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank),
ADC_SQR4_RK(sConfig->Channel, sConfig->Rank));
}
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel sampling time */
/* - Channel offset */
if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
{
/* Channel sampling time configuration */
/* Clear the old sample time then set the new one for the selected channel */
/* For channels 10 to 18 */
if (sConfig->Channel >= ADC_CHANNEL_10)
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
}
#else
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
#endif
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset with respect to the selected ADC resolution. */
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
if(sConfig->OffsetNumber != ADC_OFFSET_NONE)
{
/* Set ADC selected offset number */
LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
}
else
{
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
{
ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel);
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
}
else /* For channels 0 to 9 */
if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
{
ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel);
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
}
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset with respect to the selected ADC resolution. */
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
switch (sConfig->OffsetNumber)
{
/* Configure offset register i when applicable: */
/* - Enable offset */
/* - Set channel number */
/* - Set offset value */
case ADC_OFFSET_1:
MODIFY_REG(hadc->Instance->OFR1,
ADC_OFR_FIELDS,
ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);
break;
case ADC_OFFSET_2:
MODIFY_REG(hadc->Instance->OFR2,
ADC_OFR_FIELDS,
ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);
break;
case ADC_OFFSET_3:
MODIFY_REG(hadc->Instance->OFR3,
ADC_OFR_FIELDS,
ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);
break;
case ADC_OFFSET_4:
MODIFY_REG(hadc->Instance->OFR4,
ADC_OFR_FIELDS,
ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);
break;
/* Case ADC_OFFSET_NONE */
default :
/* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled.
If this is the case, offset OFRx is disabled since
sConfig->OffsetNumber = ADC_OFFSET_NONE. */
if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
{
CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
}
if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
{
CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
}
if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
{
CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
}
if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
{
CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
}
break;
} /* switch (sConfig->OffsetNumber) */
} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
}
if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
}
}
}
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
@ -2376,51 +2322,31 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
/* - Internal measurement channels: Vbat/VrefInt/TempSensor */
if (ADC_IS_ENABLE(hadc) == RESET)
{
/* Set mode single-ended or differential input of the selected ADC channel */
LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
/* Configuration of differential mode */
if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
{
/* Disable differential mode (default mode: single-ended) */
CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) + 1), sConfig->SamplingTime);
}
else
{
/* Enable differential mode */
SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
/* Sampling time configuration of channel ADC_IN+1 (negative input) */
/* Clear the old sample time then set the new one for the selected */
/* channel. */
/* Starting from channel 9, SMPR2 register must be configured */
if (sConfig->Channel >= ADC_CHANNEL_9)
{
ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1);
}
else /* For channels 0 to 8, SMPR1 must be configured */
{
ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1);
}
}
/* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
/* If internal channel selected, enable dedicated internal buffers and */
/* paths. */
/* paths. */
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
/* Configuration of common ADC parameters */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) ||
( (sConfig->Channel == ADC_CHANNEL_VBAT) &&
(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U)) ||
( (sConfig->Channel == ADC_CHANNEL_VREFINT) &&
(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U))
)
{
/* Configuration of common ADC parameters (continuation) */
@ -2434,13 +2360,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
{
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
{
SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)));
/* Delay for temperature sensor stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / (1000000 * 2)));
wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / (1000000 * 2)));
while(wait_loop_index != 0)
{
wait_loop_index--;
@ -2451,14 +2377,14 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
{
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
{
SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)));
}
}
else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
{
if (ADC_VREFINT_INSTANCE(hadc))
{
SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)));
}
}
}
@ -2513,12 +2439,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpAWDHighThresholdShifted;
uint32_t tmpAWDLowThresholdShifted;
uint32_t tmpADCFlagAWD2orAWD3;
uint32_t tmpADCITAWD2orAWD3;
uint32_t tmpAWDHighThresholdShifted = 0U;
uint32_t tmpAWDLowThresholdShifted = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -2553,117 +2475,146 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
/* Configuration of analog watchdog: */
/* - Set the analog watchdog enable mode: one or overall group of */
/* channels, on groups regular and-or injected. */
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_WD_FIELDS,
AnalogWDGConfig->WatchdogMode | ADC_CFGR_SET_AWD1CH(AnalogWDGConfig->Channel) );
switch(AnalogWDGConfig->WatchdogMode)
{
case ADC_ANALOGWATCHDOG_SINGLE_REG:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR));
break;
case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_INJECTED));
break;
case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR_INJECTED));
break;
case ADC_ANALOGWATCHDOG_ALL_REG:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
break;
case ADC_ANALOGWATCHDOG_ALL_INJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
break;
case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
break;
default: /* ADC_ANALOGWATCHDOG_NONE */
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
break;
}
/* Shift the offset with respect to the selected ADC resolution: */
/* Shift the offset in function of the selected ADC resolution: */
/* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
/* are set to 0 */
tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
/* Set the high and low thresholds */
MODIFY_REG(hadc->Instance->TR1,
ADC_TR1_HT1 | ADC_TR1_LT1,
ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted );
/* Clear the ADC Analog watchdog flag (in case of left enabled by */
/* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
/* or HAL_ADC_PollForEvent(). */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1);
/* Configure ADC Analog watchdog interrupt */
if(AnalogWDGConfig->ITMode == ENABLE)
{
/* Enable the ADC Analog watchdog interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1);
}
else
{
/* Disable the ADC Analog watchdog interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1);
}
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted);
/* Update state, clear previous result related to AWD1 */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
/* Clear flag ADC analog watchdog */
/* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
/* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
/* (in case left enabled by previous ADC operations). */
LL_ADC_ClearFlag_AWD1(hadc->Instance);
/* Configure ADC analog watchdog interrupt */
if(AnalogWDGConfig->ITMode == ENABLE)
{
LL_ADC_EnableIT_AWD1(hadc->Instance);
}
else
{
LL_ADC_DisableIT_AWD1(hadc->Instance);
}
}
/* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
/* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
else
{
/* Shift the threshold with respect to the selected ADC resolution */
switch(AnalogWDGConfig->WatchdogMode)
{
case ADC_ANALOGWATCHDOG_SINGLE_REG:
case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
/* Update AWD by bitfield to keep the possibility to monitor */
/* several channels by successive calls of this function. */
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
{
SET_BIT(hadc->Instance->AWD2CR, (1U << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel)));
}
else
{
SET_BIT(hadc->Instance->AWD3CR, (1U << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel)));
}
break;
case ADC_ANALOGWATCHDOG_ALL_REG:
case ADC_ANALOGWATCHDOG_ALL_INJEC:
case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
break;
default: /* ADC_ANALOGWATCHDOG_NONE */
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
break;
}
/* Shift the thresholds in function of the selected ADC resolution */
/* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */
tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted);
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
{
/* Set the Analog watchdog channel or group of channels. This also */
/* enables the watchdog. */
/* Note: Conditional register reset, because several channels can be */
/* set by successive calls of this function. */
if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
/* Update state, clear previous result related to AWD2 */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
/* Clear flag ADC analog watchdog */
/* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
/* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
/* (in case left enabled by previous ADC operations). */
LL_ADC_ClearFlag_AWD2(hadc->Instance);
/* Configure ADC analog watchdog interrupt */
if(AnalogWDGConfig->ITMode == ENABLE)
{
SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
LL_ADC_EnableIT_AWD2(hadc->Instance);
}
else
{
CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
LL_ADC_DisableIT_AWD2(hadc->Instance);
}
/* Set the high and low thresholds */
MODIFY_REG(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2,
ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted );
/* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
/* settings. */
tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2;
tmpADCITAWD2orAWD3 = ADC_IT_AWD2;
/* Update state, clear previous result related to AWD2 */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
}
/* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
else
{
/* Set the Analog watchdog channel or group of channels. This also */
/* enables the watchdog. */
/* Note: Conditional register reset, because several channels can be */
/* set by successive calls of this function. */
if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
/* Update state, clear previous result related to AWD3 */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
/* Clear flag ADC analog watchdog */
/* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
/* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
/* (in case left enabled by previous ADC operations). */
LL_ADC_ClearFlag_AWD3(hadc->Instance);
/* Configure ADC analog watchdog interrupt */
if(AnalogWDGConfig->ITMode == ENABLE)
{
SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
LL_ADC_EnableIT_AWD3(hadc->Instance);
}
else
{
CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
LL_ADC_DisableIT_AWD3(hadc->Instance);
}
/* Set the high and low thresholds */
MODIFY_REG(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3,
ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted );
/* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
/* settings. */
tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3;
tmpADCITAWD2orAWD3 = ADC_IT_AWD3;
/* Update state, clear previous result related to AWD3 */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
}
/* Clear the ADC Analog watchdog flag (in case left enabled by */
/* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
/* or HAL_ADC_PollForEvent(). */
__HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3);
/* Configure ADC Analog watchdog interrupt */
if(AnalogWDGConfig->ITMode == ENABLE)
{
__HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3);
}
else
{
__HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3);
}
}
@ -2677,7 +2628,6 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
tmp_hal_status = HAL_ERROR;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
@ -2816,7 +2766,7 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio
HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
{
/* Stop conversions on regular group */
SET_BIT(hadc->Instance->CR, ADC_CR_ADSTP);
LL_ADC_REG_StopConversion(hadc->Instance);
}
}
@ -2884,6 +2834,7 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
{
uint32_t tickstart = 0;
__IO uint32_t wait_loop_index = 0;
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
@ -2904,11 +2855,20 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
}
/* Enable the ADC peripheral */
ADC_ENABLE(hadc);
LL_ADC_Enable(hadc->Instance);
/* Delay for ADC stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */
wait_loop_index = (LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (1000000 * 2)));
while(wait_loop_index != 0)
{
wait_loop_index--;
}
/* Wait for ADC effectively enabled */
tickstart = HAL_GetTick();
tickstart = HAL_GetTick();
while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
{
@ -2918,9 +2878,14 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
The workaround is to continue setting ADEN until ADRDY is becomes 1.
Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
4 ADC clock cycle duration */
ADC_ENABLE(hadc);
if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT)
/* Note: Test of ADC enabled required due to hardware constraint to */
/* not enable ADC if already enabled. */
if(LL_ADC_IsEnabled(hadc->Instance) == 0)
{
LL_ADC_Enable(hadc->Instance);
}
if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
@ -2957,7 +2922,8 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
{
/* Disable the ADC peripheral */
ADC_DISABLE(hadc);
LL_ADC_Disable(hadc->Instance);
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
}
else
{

251
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_adc_ex.c
View file

@ -96,7 +96,7 @@
/* 112 / 140,000 = 0.8 ms */
/* At maximum CPU speed (80 MHz), this means */
/* 0.8 ms * 80 MHz = 64000 CPU cycles */
#define ADC_CALIBRATION_TIMEOUT ((uint32_t) 64000) /*!< ADC calibration time-out value */
#define ADC_CALIBRATION_TIMEOUT (64000U) /*!< ADC calibration time-out value */
/**
* @}
@ -158,7 +158,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
/* Process locked */
__HAL_LOCK(hadc);
@ -225,7 +225,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t
* @brief Get the calibration factor.
* @param hadc ADC handle.
* @param SingleDiff This parameter can be only:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
* @retval Calibration value.
*/
@ -251,7 +251,7 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t Single
* ADC must be enabled and no conversion is ongoing.
* @param hadc ADC handle
* @param SingleDiff This parameter can be only:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
* @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
* @retval HAL state
@ -903,7 +903,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
/* Pointer to the common control register */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
/* start (in case of SW start): */
@ -927,8 +927,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
}
else
{
@ -1068,7 +1068,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
/* Pointer to the common control register */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
/* Return the multi mode conversion value */
return tmpADC_Common->CDR;
@ -1213,7 +1213,6 @@ __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc)
*/
}
/**
* @brief Stop ADC conversion of regular group (and injected channels in
* case of auto_injection mode), disable ADC peripheral if no
@ -1598,11 +1597,10 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
ADC_Common_TypeDef *tmpADC_Common;
uint32_t tmpOffsetShifted;
uint32_t wait_loop_index = 0;
uint32_t wait_loop_index = 0U;
uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0;
uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -1667,9 +1665,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* injected ranks have been set. */
/* Note: Scan mode is not present by hardware on this device, but used */
/* by software for alignment over all STM32 devices. */
if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
(sConfigInjected->InjectedNbrOfConversion == 1) )
(sConfigInjected->InjectedNbrOfConversion == 1U) )
{
/* Configuration of context register JSQR: */
/* - number of ranks in injected group sequencer: fixed to 1st rank */
@ -1685,19 +1683,18 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
/* software start. */
if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
&& (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) |
sConfigInjected->ExternalTrigInjecConv |
sConfigInjected->ExternalTrigInjecConvEdge );
tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
| (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
| sConfigInjected->ExternalTrigInjecConvEdge
);
}
else
{
tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) );
tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) );
}
MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt);
/* For debug and informative reasons, hadc handle saves JSQR setting */
hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
@ -1716,7 +1713,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
/* call of the context under setting */
if (hadc->InjectionConfig.ChannelCount == 0)
if (hadc->InjectionConfig.ChannelCount == 0U)
{
/* Initialize number of channels that will be configured on the context */
/* being built */
@ -1724,7 +1721,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
call, this context will be written in JSQR register at the last call.
At this point, the context is merely reset */
hadc->InjectionConfig.ContextQueue = (uint32_t)0x00000000;
hadc->InjectionConfig.ContextQueue = 0x00000000U;
/* Configuration of context register JSQR: */
/* - number of ranks in injected group sequencer */
@ -1736,21 +1733,20 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
/* software start. */
if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
&& (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) |
sConfigInjected->ExternalTrigInjecConv |
sConfigInjected->ExternalTrigInjecConvEdge );
tmp_JSQR_ContextQueueBeingBuilt = ( (sConfigInjected->InjectedNbrOfConversion - 1U)
| (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
| sConfigInjected->ExternalTrigInjecConvEdge
);
}
else
{
tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) );
tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U) );
}
}
/* 2. Continue setting of context under definition with parameter */
/* related to each channel: channel rank sequence */
/* Clear the old JSQx bits for the selected rank */
@ -1758,7 +1754,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* Set the JSQx bits for the selected rank */
tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
/* Decrease channel count */
hadc->InjectionConfig.ChannelCount--;
@ -1769,7 +1765,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* 4. End of context setting: if this is the last channel set, then write context
into register JSQR and make it enter into queue */
if (hadc->InjectionConfig.ChannelCount == 0)
if (hadc->InjectionConfig.ChannelCount == 0U)
{
MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
}
@ -1791,7 +1787,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) |
ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) );
}
/* If auto-injected mode is enabled: Injected discontinuous setting is */
/* If auto-injected mode is enabled: Injected discontinuous setting is */
/* discarded. */
else
{
@ -1854,11 +1850,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* - Right bit shift */
/* Enable OverSampling mode */
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_INJ_FIELDS,
ADC_CFGR2_JOVSE |
sConfigInjected->InjecOversampling.Ratio |
sConfigInjected->InjecOversampling.RightBitShift );
MODIFY_REG(hadc->Instance->CFGR2,
ADC_CFGR2_JOVSE |
ADC_CFGR2_OVSR |
ADC_CFGR2_OVSS,
ADC_CFGR2_JOVSE |
sConfigInjected->InjecOversampling.Ratio |
sConfigInjected->InjecOversampling.RightBitShift
);
}
else
{
@ -1866,18 +1865,28 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
}
/* Sampling time configuration of the selected channel */
/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
{
/* Clear the old sample time and set the new one */
ADC_SMPR2_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
}
else /* if ADC_Channel_0 ... ADC_Channel_9 is selected */
{
/* Clear the old sample time and set the new one */
ADC_SMPR1_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
}
#if defined(ADC_SMPR1_SMPPLUS)
/* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
if(sConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5)
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
}
else
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime);
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
}
#else
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime);
#endif
/* Configure the offset: offset enable/disable, channel, offset value */
@ -1885,72 +1894,32 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
switch (sConfigInjected->InjectedOffsetNumber)
if(sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
{
case ADC_OFFSET_1:
/* Configure offset register 1: */
/* - Enable offset */
/* - Set channel number */
/* - Set offset value */
MODIFY_REG(hadc->Instance->OFR1,
ADC_OFR_INJ_FIELDS,
ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
break;
case ADC_OFFSET_2:
/* Configure offset register 2: */
/* - Enable offset */
/* - Set channel number */
/* - Set offset value */
MODIFY_REG(hadc->Instance->OFR2,
ADC_OFR_INJ_FIELDS,
ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
break;
case ADC_OFFSET_3:
/* Configure offset register 3: */
/* - Enable offset */
/* - Set channel number */
/* - Set offset value */
MODIFY_REG(hadc->Instance->OFR3,
ADC_OFR_INJ_FIELDS,
ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
break;
case ADC_OFFSET_4:
/* Configure offset register 1: */
/* - Enable offset */
/* - Set channel number */
/* - Set offset value */
MODIFY_REG(hadc->Instance->OFR4,
ADC_OFR_INJ_FIELDS,
ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
break;
/* Case ADC_OFFSET_NONE */
default :
/* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. If this is the case, offset OFRx is disabled. */
if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
/* Set ADC selected offset number */
LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, tmpOffsetShifted);
}
else
{
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
/* Disable offset OFR1*/
CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
}
if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
/* Disable offset OFR2*/
CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
}
if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
/* Disable offset OFR3*/
CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
}
if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
/* Disable offset OFR4*/
CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
}
break;
}
}
@ -1961,32 +1930,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* - Internal measurement channels: Vbat/VrefInt/TempSensor */
if (ADC_IS_ENABLE(hadc) == RESET)
{
/* Set mode single-ended or differential input of the selected ADC channel */
LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff);
/* Configuration of differential mode */
if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
{
/* Disable differential mode (default mode: single-ended) */
CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
}
else
{
/* Enable differential mode */
SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
/* Sampling time configuration of channel ADC_IN+1 (negative input).
Starting from channel 9, SMPR2 register must be configured. */
if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_9)
{
/* Clear the old sample time and set the new one */
ADC_SMPR2_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel+1);
}
else /* For channels 0 to 8 */
{
/* Clear the old sample time and set the new one */
ADC_SMPR1_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel+1);
}
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) + 1), sConfigInjected->InjectedSamplingTime);
}
/* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
/* internal measurement paths enable: If internal channel selected, */
/* enable dedicated internal buffers and path. */
@ -1994,18 +1947,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* HAL_ADC_DeInit(). */
/* Configuration of common ADC parameters */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) &&
(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) &&
(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
)
if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) ||
( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) &&
((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U)) ||
( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) &&
((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U))
)
{
/* Configuration of common ADC parameters (continuation) */
/* Software is allowed to change common parameters only when all ADCs */
@ -2017,11 +1967,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
{
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
{
SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)));
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / 1000000));
while(wait_loop_index != 0)
{
wait_loop_index--;
@ -2032,16 +1982,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
{
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
{
SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)));
}
}
else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
{
if (ADC_VREFINT_INSTANCE(hadc))
{
SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
}
}
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)));
}
}
}
/* If the requested internal measurement path has already been enabled */
/* and other ADC of the common group are enabled, internal */
@ -2121,7 +2071,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
&& (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) == RESET) )
{
/* Pointer to the common control register */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
/* If multimode is selected, configure all multimode paramaters. */
/* Otherwise, reset multimode parameters (can be used in case of */
@ -2145,8 +2095,12 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
if ((ADC_IS_ENABLE(hadc) == RESET) &&
(ADC_IS_ENABLE(&tmphadcSlave) == RESET) )
{
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY,
multimode->Mode | multimode->TwoSamplingDelay );
MODIFY_REG(tmpADC_Common->CCR,
ADC_CCR_DUAL |
ADC_CCR_DELAY,
multimode->Mode |
multimode->TwoSamplingDelay
);
}
}
else /* ADC_MODE_INDEPENDENT */
@ -2173,7 +2127,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
tmp_hal_status = HAL_ERROR;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);

4
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_comp.c
View file

@ -665,8 +665,8 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
* voltage than the input minus
* @param hcomp COMP handle
* @retval Returns the selected comparator output level:
* @arg @ref COMP_OUTPUT_LEVEL_LOW
* @arg @ref COMP_OUTPUT_LEVEL_HIGH
* @arg COMP_OUTPUT_LEVEL_LOW
* @arg COMP_OUTPUT_LEVEL_HIGH
*
*/
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)

196
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dfsdm.c
View file

@ -274,7 +274,7 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma);
/**
* @brief Initialize the DFSDM channel according to the specified parameters
* in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
* @param hdfsdm_channel : DFSDM channel handle.
* @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@ -368,7 +368,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan
/**
* @brief De-initialize the DFSDM channel.
* @param hdfsdm_channel : DFSDM channel handle.
* @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@ -414,7 +414,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch
/**
* @brief Initialize the DFSDM channel MSP.
* @param hdfsdm_channel : DFSDM channel handle.
* @param hdfsdm_channel DFSDM channel handle.
* @retval None
*/
__weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@ -429,7 +429,7 @@ __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel
/**
* @brief De-initialize the DFSDM channel MSP.
* @param hdfsdm_channel : DFSDM channel handle.
* @param hdfsdm_channel DFSDM channel handle.
* @retval None
*/
__weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@ -468,7 +468,7 @@ __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chann
* @note If clock is not available on this channel during 5 seconds,
* clock absence detection will not be activated and function
* will return HAL_TIMEOUT error.
* @param hdfsdm_channel : DFSDM channel handle.
* @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@ -520,8 +520,8 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm
/**
* @brief This function allows to poll for the clock absence detection.
* @param hdfsdm_channel : DFSDM channel handle.
* @param Timeout : Timeout value in milliseconds.
* @param hdfsdm_channel DFSDM channel handle.
* @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
@ -571,7 +571,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs
/**
* @brief This function allows to stop clock absence detection in polling mode.
* @param hdfsdm_channel : DFSDM channel handle.
* @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@ -607,7 +607,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_
* @note If clock is not available on this channel during 5 seconds,
* clock absence detection will not be activated and function
* will return HAL_TIMEOUT error.
* @param hdfsdm_channel : DFSDM channel handle.
* @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@ -662,7 +662,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf
/**
* @brief Clock absence detection callback.
* @param hdfsdm_channel : DFSDM channel handle.
* @param hdfsdm_channel DFSDM channel handle.
* @retval None
*/
__weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@ -678,7 +678,7 @@ __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_ch
/**
* @brief This function allows to stop clock absence detection in interrupt mode.
* @note Interrupt will be disabled for all channels
* @param hdfsdm_channel : DFSDM channel handle.
* @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@ -714,10 +714,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs
/**
* @brief This function allows to start short circuit detection in polling mode.
* @note Same mode has to be used for all channels
* @param hdfsdm_channel : DFSDM channel handle.
* @param Threshold : Short circuit detector threshold.
* @param hdfsdm_channel DFSDM channel handle.
* @param Threshold Short circuit detector threshold.
* This parameter must be a number between Min_Data = 0 and Max_Data = 255.
* @param BreakSignal : Break signals assigned to short circuit event.
* @param BreakSignal Break signals assigned to short circuit event.
* This parameter can be a values combination of @ref DFSDM_BreakSignals.
* @retval HAL status
*/
@ -754,8 +754,8 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_
/**
* @brief This function allows to poll for the short circuit detection.
* @param hdfsdm_channel : DFSDM channel handle.
* @param Timeout : Timeout value in milliseconds.
* @param hdfsdm_channel DFSDM channel handle.
* @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
@ -805,7 +805,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd
/**
* @brief This function allows to stop short circuit detection in polling mode.
* @param hdfsdm_channel : DFSDM channel handle.
* @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@ -838,10 +838,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_c
/**
* @brief This function allows to start short circuit detection in interrupt mode.
* @note Same mode has to be used for all channels
* @param hdfsdm_channel : DFSDM channel handle.
* @param Threshold : Short circuit detector threshold.
* @param hdfsdm_channel DFSDM channel handle.
* @param Threshold Short circuit detector threshold.
* This parameter must be a number between Min_Data = 0 and Max_Data = 255.
* @param BreakSignal : Break signals assigned to short circuit event.
* @param BreakSignal Break signals assigned to short circuit event.
* This parameter can be a values combination of @ref DFSDM_BreakSignals.
* @retval HAL status
*/
@ -881,7 +881,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs
/**
* @brief Short circuit detection callback.
* @param hdfsdm_channel : DFSDM channel handle.
* @param hdfsdm_channel DFSDM channel handle.
* @retval None
*/
__weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@ -897,7 +897,7 @@ __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_cha
/**
* @brief This function allows to stop short circuit detection in interrupt mode.
* @note Interrupt will be disabled for all channels
* @param hdfsdm_channel : DFSDM channel handle.
* @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@ -932,7 +932,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd
/**
* @brief This function allows to get channel analog watchdog value.
* @param hdfsdm_channel : DFSDM channel handle.
* @param hdfsdm_channel DFSDM channel handle.
* @retval Channel analog watchdog value.
*/
int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@ -942,8 +942,8 @@ int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel
/**
* @brief This function allows to modify channel offset value.
* @param hdfsdm_channel : DFSDM channel handle.
* @param Offset : DFSDM channel offset.
* @param hdfsdm_channel DFSDM channel handle.
* @param Offset DFSDM channel offset.
* This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.
* @retval HAL status.
*/
@ -991,7 +991,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf
/**
* @brief This function allows to get the current DFSDM channel handle state.
* @param hdfsdm_channel : DFSDM channel handle.
* @param hdfsdm_channel DFSDM channel handle.
* @retval DFSDM channel state.
*/
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@ -1021,7 +1021,7 @@ HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTyp
/**
* @brief Initialize the DFSDM filter according to the specified parameters
* in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -1131,7 +1131,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
/**
* @brief De-initializes the DFSDM filter.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -1159,7 +1159,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filt
/**
* @brief Initializes the DFSDM filter MSP.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -1174,7 +1174,7 @@ __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
/**
* @brief De-initializes the DFSDM filter MSP.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -1208,10 +1208,10 @@ __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
/**
* @brief This function allows to select channel and to enable/disable
* continuous mode for regular conversion.
* @param hdfsdm_filter : DFSDM filter handle.
* @param Channel : Channel for regular conversion.
* @param hdfsdm_filter DFSDM filter handle.
* @param Channel Channel for regular conversion.
* This parameter can be a value of @ref DFSDM_Channel_Selection.
* @param ContinuousMode : Enable/disable continuous mode for regular conversion.
* @param ContinuousMode Enable/disable continuous mode for regular conversion.
* This parameter can be a value of @ref DFSDM_ContinuousMode.
* @retval HAL status
*/
@ -1255,8 +1255,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *h
/**
* @brief This function allows to select channels for injected conversion.
* @param hdfsdm_filter : DFSDM filter handle.
* @param Channel : Channels for injected conversion.
* @param hdfsdm_filter DFSDM filter handle.
* @param Channel Channels for injected conversion.
* This parameter can be a values combination of @ref DFSDM_Channel_Selection.
* @retval HAL status
*/
@ -1327,7 +1327,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *h
* @brief This function allows to start regular conversion in polling mode.
* @note This function should be called only when DFSDM filter instance is
* in idle state or if injected conversion is ongoing.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -1355,8 +1355,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsd
/**
* @brief This function allows to poll for the end of regular conversion.
* @note This function should be called only if regular conversion is ongoing.
* @param hdfsdm_filter : DFSDM filter handle.
* @param Timeout : Timeout value in milliseconds.
* @param hdfsdm_filter DFSDM filter handle.
* @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@ -1417,7 +1417,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDe
/**
* @brief This function allows to stop regular conversion in polling mode.
* @note This function should be called only if regular conversion is ongoing.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -1447,7 +1447,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm
* @brief This function allows to start regular conversion in interrupt mode.
* @note This function should be called only when DFSDM filter instance is
* in idle state or if injected conversion is ongoing.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -1478,7 +1478,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hd
/**
* @brief This function allows to stop regular conversion in interrupt mode.
* @note This function should be called only if regular conversion is ongoing.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -1514,9 +1514,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdf
* Please note that data on buffer will contain signed regular conversion
* value on 24 most significant bits and corresponding channel on 3 least
* significant bits.
* @param hdfsdm_filter : DFSDM filter handle.
* @param pData : The destination buffer address.
* @param Length : The length of data to be transferred from DFSDM filter to memory.
* @param hdfsdm_filter DFSDM filter handle.
* @param pData The destination buffer address.
* @param Length The length of data to be transferred from DFSDM filter to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@ -1591,9 +1591,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *h
* in idle state or if injected conversion is ongoing.
* Please note that data on buffer will contain signed 16 most significant
* bits of regular conversion.
* @param hdfsdm_filter : DFSDM filter handle.
* @param pData : The destination buffer address.
* @param Length : The length of data to be transferred from DFSDM filter to memory.
* @param hdfsdm_filter DFSDM filter handle.
* @param pData The destination buffer address.
* @param Length The length of data to be transferred from DFSDM filter to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@ -1664,7 +1664,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef
/**
* @brief This function allows to stop regular conversion in DMA mode.
* @note This function should be called only if regular conversion is ongoing.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -1702,8 +1702,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hd
/**
* @brief This function allows to get regular conversion value.
* @param hdfsdm_filter : DFSDM filter handle.
* @param Channel : Corresponding channel of regular conversion.
* @param hdfsdm_filter DFSDM filter handle.
* @param Channel Corresponding channel of regular conversion.
* @retval Regular conversion value
*/
int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@ -1731,7 +1731,7 @@ int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filte
* @brief This function allows to start injected conversion in polling mode.
* @note This function should be called only when DFSDM filter instance is
* in idle state or if regular conversion is ongoing.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -1759,8 +1759,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfs
/**
* @brief This function allows to poll for the end of injected conversion.
* @note This function should be called only if injected conversion is ongoing.
* @param hdfsdm_filter : DFSDM filter handle.
* @param Timeout : Timeout value in milliseconds.
* @param hdfsdm_filter DFSDM filter handle.
* @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@ -1831,7 +1831,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe
/**
* @brief This function allows to stop injected conversion in polling mode.
* @note This function should be called only if injected conversion is ongoing.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -1861,7 +1861,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd
* @brief This function allows to start injected conversion in interrupt mode.
* @note This function should be called only when DFSDM filter instance is
* in idle state or if regular conversion is ongoing.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -1892,7 +1892,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *h
/**
* @brief This function allows to stop injected conversion in interrupt mode.
* @note This function should be called only if injected conversion is ongoing.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -1928,9 +1928,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hd
* Please note that data on buffer will contain signed injected conversion
* value on 24 most significant bits and corresponding channel on 3 least
* significant bits.
* @param hdfsdm_filter : DFSDM filter handle.
* @param pData : The destination buffer address.
* @param Length : The length of data to be transferred from DFSDM filter to memory.
* @param hdfsdm_filter DFSDM filter handle.
* @param pData The destination buffer address.
* @param Length The length of data to be transferred from DFSDM filter to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@ -2003,9 +2003,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *
* in idle state or if regular conversion is ongoing.
* Please note that data on buffer will contain signed 16 most significant
* bits of injected conversion.
* @param hdfsdm_filter : DFSDM filter handle.
* @param pData : The destination buffer address.
* @param Length : The length of data to be transferred from DFSDM filter to memory.
* @param hdfsdm_filter DFSDM filter handle.
* @param pData The destination buffer address.
* @param Length The length of data to be transferred from DFSDM filter to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@ -2074,7 +2074,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDe
/**
* @brief This function allows to stop injected conversion in DMA mode.
* @note This function should be called only if injected conversion is ongoing.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -2112,8 +2112,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *h
/**
* @brief This function allows to get injected conversion value.
* @param hdfsdm_filter : DFSDM filter handle.
* @param Channel : Corresponding channel of injected conversion.
* @param hdfsdm_filter DFSDM filter handle.
* @param Channel Corresponding channel of injected conversion.
* @retval Injected conversion value
*/
int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@ -2139,8 +2139,8 @@ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filt
/**
* @brief This function allows to start filter analog watchdog in interrupt mode.
* @param hdfsdm_filter : DFSDM filter handle.
* @param awdParam : DFSDM filter analog watchdog parameters.
* @param hdfsdm_filter DFSDM filter handle.
* @param awdParam DFSDM filter analog watchdog parameters.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@ -2189,7 +2189,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfs
/**
* @brief This function allows to stop filter analog watchdog in interrupt mode.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -2227,8 +2227,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_
/**
* @brief This function allows to start extreme detector feature.
* @param hdfsdm_filter : DFSDM filter handle.
* @param Channel : Channels where extreme detector is enabled.
* @param hdfsdm_filter DFSDM filter handle.
* @param Channel Channels where extreme detector is enabled.
* This parameter can be a values combination of @ref DFSDM_Channel_Selection.
* @retval HAL status
*/
@ -2260,7 +2260,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_fi
/**
* @brief This function allows to stop extreme detector feature.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -2296,8 +2296,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil
/**
* @brief This function allows to get extreme detector maximum value.
* @param hdfsdm_filter : DFSDM filter handle.
* @param Channel : Corresponding channel.
* @param hdfsdm_filter DFSDM filter handle.
* @param Channel Corresponding channel.
* @retval Extreme detector maximum value
* This value is between Min_Data = -8388608 and Max_Data = 8388607.
*/
@ -2324,8 +2324,8 @@ int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
/**
* @brief This function allows to get extreme detector minimum value.
* @param hdfsdm_filter : DFSDM filter handle.
* @param Channel : Corresponding channel.
* @param hdfsdm_filter DFSDM filter handle.
* @param Channel Corresponding channel.
* @retval Extreme detector minimum value
* This value is between Min_Data = -8388608 and Max_Data = 8388607.
*/
@ -2352,7 +2352,7 @@ int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
/**
* @brief This function allows to get conversion time value.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval Conversion time value
* @note To get time in second, this value has to be divided by DFSDM clock frequency.
*/
@ -2376,7 +2376,7 @@ uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_fil
/**
* @brief This function handles the DFSDM interrupts.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -2537,7 +2537,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
* @brief Regular conversion complete callback.
* @note In interrupt mode, user has to read conversion value in this function
* using HAL_DFSDM_FilterGetRegularValue.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -2552,7 +2552,7 @@ __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfs
/**
* @brief Half regular conversion complete callback.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -2569,7 +2569,7 @@ __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *
* @brief Injected conversion complete callback.
* @note In interrupt mode, user has to read conversion value in this function
* using HAL_DFSDM_FilterGetInjectedValue.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -2584,7 +2584,7 @@ __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfs
/**
* @brief Half injected conversion complete callback.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -2599,9 +2599,9 @@ __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *
/**
* @brief Filter analog watchdog callback.
* @param hdfsdm_filter : DFSDM filter handle.
* @param Channel : Corresponding channel.
* @param Threshold : Low or high threshold has been reached.
* @param hdfsdm_filter DFSDM filter handle.
* @param Channel Corresponding channel.
* @param Threshold Low or high threshold has been reached.
* @retval None
*/
__weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@ -2619,7 +2619,7 @@ __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filte
/**
* @brief Error callback.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -2652,7 +2652,7 @@ __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_fil
/**
* @brief This function allows to get the current DFSDM filter handle state.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval DFSDM filter state.
*/
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -2663,7 +2663,7 @@ HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDe
/**
* @brief This function allows to get the current DFSDM filter error.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval DFSDM filter error code.
*/
uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@ -2687,7 +2687,7 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
/**
* @brief DMA half transfer complete callback for regular conversion.
* @param hdma : DMA handle.
* @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
@ -2701,7 +2701,7 @@ static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA transfer complete callback for regular conversion.
* @param hdma : DMA handle.
* @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
@ -2715,7 +2715,7 @@ static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA half transfer complete callback for injected conversion.
* @param hdma : DMA handle.
* @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
@ -2729,7 +2729,7 @@ static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA transfer complete callback for injected conversion.
* @param hdma : DMA handle.
* @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
@ -2743,7 +2743,7 @@ static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA error callback.
* @param hdma : DMA handle.
* @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
@ -2760,7 +2760,7 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
/**
* @brief This function allows to get the number of injected channels.
* @param Channels : bitfield of injected channels.
* @param Channels bitfield of injected channels.
* @retval Number of injected channels.
*/
static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
@ -2783,7 +2783,7 @@ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
/**
* @brief This function allows to get the channel number from channel instance.
* @param Instance : DFSDM channel instance.
* @param Instance DFSDM channel instance.
* @retval Channel number.
*/
static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
@ -2833,7 +2833,7 @@ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
/**
* @brief This function allows to really start regular conversion.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
@ -2874,7 +2874,7 @@ static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
/**
* @brief This function allows to really stop regular conversion.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
@ -2910,7 +2910,7 @@ static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
/**
* @brief This function allows to really start injected conversion.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
@ -2954,7 +2954,7 @@ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
/**
* @brief This function allows to really stop injected conversion.
* @param hdfsdm_filter : DFSDM filter handle.
* @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)

8
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dfsdm_ex.c
View file

@ -80,8 +80,8 @@
/**
* @brief Set value of pulses skipping.
* @param hdfsdm_channel : DFSDM channel handle.
* @param PulsesValue: Value of pulses to be skipped.
* @param hdfsdm_channel DFSDM channel handle.
* @param PulsesValue Value of pulses to be skipped.
* This parameter must be a number between Min_Data = 0 and Max_Data = 63.
* @retval HAL status.
*/
@ -107,8 +107,8 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeD
/**
* @brief Get value of pulses skipping.
* @param hdfsdm_channel : DFSDM channel handle.
* @param PulsesValue: Value of pulses to be skipped.
* @param hdfsdm_channel DFSDM channel handle.
* @param PulsesValue Value of pulses to be skipped.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue)

16
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dma.c
View file

@ -18,17 +18,15 @@
necessary). Please refer to the Reference manual for connection between peripherals
and DMA requests.
__HAL_RCC_DMAMUX1_CLK_ENABLE
(#) For a given Channel, program the required configuration through the following parameters:
Channel request, Transfer Direction, Source and Destination data formats,
Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
using HAL_DMA_Init() function.
Prior to HAL_DMA_Init the CLK shall be enabled for both DMA & DMAMUX
Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX
thanks to:
DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() ;
DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE();
(##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() ;
(##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE();
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
detection.
@ -36,6 +34,7 @@
(#) Use HAL_DMA_Abort() function to abort the current transfer
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
*** Polling mode IO operation ***
=================================
[..]
@ -54,13 +53,12 @@
In this case the DMA interrupt is configured
(+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
add his own function by customization of function pointer XferCpltCallback and
XferErrorCallback (i.e. a member of DMA handle structure).
add his own function to register callbacks with HAL_DMA_RegisterCallback().
*** DMA HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in DMA HAL driver.
Below the list of macros in DMA HAL driver.
(+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
(+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
@ -68,7 +66,7 @@
(+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
(+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
(+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not.
[..]
(@) You can refer to the DMA HAL driver header file for more useful macros

6
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dma2d.c
View file

@ -596,7 +596,7 @@ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
/* Abort the DMA2D transfer */
/* START bit is reset to make sure not to set it again, in the event the HW clears it
between the register read and the register write by the CPU (writing ‘0’ has no
between the register read and the register write by the CPU (writing 0 has no
effect on START bitvalue). */
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
@ -645,7 +645,7 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
/* Suspend the DMA2D transfer */
/* START bit is reset to make sure not to set it again, in the event the HW clears it
between the register read and the register write by the CPU (writing ‘0’ has no
between the register read and the register write by the CPU (writing 0 has no
effect on START bitvalue). */
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
@ -700,7 +700,7 @@ HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
/* Resume the DMA2D transfer */
/* START bit is reset to make sure not to set it again, in the event the HW clears it
between the register read and the register write by the CPU (writing ‘0’ has no
between the register read and the register write by the CPU (writing 0 has no
effect on START bitvalue). */
CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));

4
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dma_ex.c
View file

@ -94,8 +94,8 @@
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
(+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
(+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
(+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
to respectively enable/disable the request generator.

1184
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dsi.c
View file

File diff suppressed because it is too large Load diff

135
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_firewall.c
View file

@ -9,19 +9,19 @@
*
@verbatim
===============================================================================
##### How to use this driver #####
##### How to use this driver #####
===============================================================================
[..]
The FIREWALL HAL driver can be used as follows:
(#) Declare a FIREWALL_InitTypeDef initialization structure.
(#) Resort to HAL_FIREWALL_Config() API to initialize the Firewall
(#) Enable the FIREWALL in calling HAL_FIREWALL_EnableFirewall() API
(#) To ensure that any code executed outside the protected segment closes the
FIREWALL, the user must set the flag FIREWALL_PRE_ARM_SET in calling
FIREWALL, the user must set the flag FIREWALL_PRE_ARM_SET in calling
__HAL_FIREWALL_PREARM_ENABLE() macro if called within a protected code segment
or
HAL_FIREWALL_EnablePreArmFlag() API if called outside of protected code segment
@ -56,7 +56,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@ -66,12 +66,12 @@
* @{
*/
/** @defgroup FIREWALL FIREWALL
/** @defgroup FIREWALL FIREWALL
* @brief HAL FIREWALL module driver
* @{
*/
#ifdef HAL_FIREWALL_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@ -84,27 +84,27 @@
* @{
*/
/** @defgroup FIREWALL_Exported_Functions_Group1 Initialization Functions
* @brief Initialization and Configuration Functions
/** @defgroup FIREWALL_Exported_Functions_Group1 Initialization Functions
* @brief Initialization and Configuration Functions
*
@verbatim
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..]
This subsection provides the functions allowing to initialize the Firewall.
Initialization is done by HAL_FIREWALL_Config():
Initialization is done by HAL_FIREWALL_Config():
(+) Enable the Firewall clock thru __HAL_RCC_FIREWALL_CLK_ENABLE() macro.
(+) Set the protected code segment address start and length.
(+) Set the protected non-volatile and/or volatile data segments
address starts and lengths if applicable.
(+) Set the protected non-volatile and/or volatile data segments
address starts and lengths if applicable.
(+) Set the volatile data segment execution and sharing status.
(+) Length must be set to 0 for an unprotected segment.
(+) Length must be set to 0 for an unprotected segment.
@endverbatim
* @{
@ -113,7 +113,7 @@
/**
* @brief Initialize the Firewall according to the FIREWALL_InitTypeDef structure parameters.
* @param fw_init: Firewall initialization structure
* @note The API returns HAL_ERROR if the Firewall is already enabled.
* @note The API returns HAL_ERROR if the Firewall is already enabled.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init)
@ -123,7 +123,7 @@ HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init)
{
return HAL_ERROR;
}
/* Enable Firewall clock */
__HAL_RCC_FIREWALL_CLK_ENABLE();
@ -132,53 +132,58 @@ HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init)
{
return HAL_ERROR;
}
/* Check Firewall configuration addresses and lengths when segment is protected */
/* Code segment */
if (fw_init->CodeSegmentLength != 0)
{
assert_param(IS_FIREWALL_CODE_SEGMENT_ADDRESS(fw_init->CodeSegmentStartAddress));
assert_param(IS_FIREWALL_CODE_SEGMENT_LENGTH(fw_init->CodeSegmentStartAddress, fw_init->CodeSegmentLength));
assert_param(IS_FIREWALL_CODE_SEGMENT_LENGTH(fw_init->CodeSegmentStartAddress, fw_init->CodeSegmentLength));
/* Make sure that NonVDataSegmentLength is properly set to prevent code segment access */
if (fw_init->NonVDataSegmentLength < 0x100)
{
return HAL_ERROR;
}
}
/* Non volatile data segment */
if (fw_init->NonVDataSegmentLength != 0)
{
assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(fw_init->NonVDataSegmentStartAddress));
assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(fw_init->NonVDataSegmentStartAddress, fw_init->NonVDataSegmentLength));
assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(fw_init->NonVDataSegmentStartAddress, fw_init->NonVDataSegmentLength));
}
/* Volatile data segment */
if (fw_init->VDataSegmentLength != 0)
{
assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(fw_init->VDataSegmentStartAddress));
assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(fw_init->VDataSegmentStartAddress, fw_init->VDataSegmentLength));
assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(fw_init->VDataSegmentStartAddress, fw_init->VDataSegmentLength));
}
/* Check Firewall Configuration Register parameters */
assert_param(IS_FIREWALL_VOLATILEDATA_EXECUTE(fw_init->VolatileDataExecution));
assert_param(IS_FIREWALL_VOLATILEDATA_SHARE(fw_init->VolatileDataShared));
/* Configuration */
/* Protected code segment start address configuration */
WRITE_REG(FIREWALL->CSSA, (FW_CSSA_ADD & fw_init->CodeSegmentStartAddress));
/* Protected code segment length configuration */
WRITE_REG(FIREWALL->CSL, (FW_CSL_LENG & fw_init->CodeSegmentLength));
/* Protected non volatile data segment start address configuration */
WRITE_REG(FIREWALL->NVDSSA, (FW_NVDSSA_ADD & fw_init->NonVDataSegmentStartAddress));
/* Protected non volatile data segment length configuration */
WRITE_REG(FIREWALL->NVDSL, (FW_NVDSL_LENG & fw_init->NonVDataSegmentLength));
/* Protected volatile data segment start address configuration */
WRITE_REG(FIREWALL->VDSSA, (FW_VDSSA_ADD & fw_init->VDataSegmentStartAddress));
/* Protected volatile data segment length configuration */
WRITE_REG(FIREWALL->VDSL, (FW_VDSL_LENG & fw_init->VDataSegmentLength));
WRITE_REG(FIREWALL->VDSL, (FW_VDSL_LENG & fw_init->VDataSegmentLength));
/* Set Firewall Configuration Register VDE and VDS bits
(volatile data execution and shared configuration) */
(volatile data execution and shared configuration) */
MODIFY_REG(FIREWALL->CR, FW_CR_VDS|FW_CR_VDE, fw_init->VolatileDataExecution|fw_init->VolatileDataShared);
return HAL_OK;
}
@ -187,71 +192,71 @@ HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init)
* @param fw_config: Firewall configuration, type is same as initialization structure
* @note This API can't be executed inside a code area protected by the Firewall
* when the Firewall is enabled
* @note If NVDSL register is different from 0, that is, if the non volatile data segment
* is defined, this API can't be executed when the Firewall is enabled.
* @note User should resort to __HAL_FIREWALL_GET_PREARM() macro to retrieve FPA bit status
* @note If NVDSL register is different from 0, that is, if the non volatile data segment
* is defined, this API can't be executed when the Firewall is enabled.
* @note User should resort to __HAL_FIREWALL_GET_PREARM() macro to retrieve FPA bit status
* @retval None
*/
void HAL_FIREWALL_GetConfig(FIREWALL_InitTypeDef * fw_config)
{
/* Enable Firewall clock, in case no Firewall configuration has been carried
/* Enable Firewall clock, in case no Firewall configuration has been carried
out up to this point */
__HAL_RCC_FIREWALL_CLK_ENABLE();
/* Retrieve code segment protection setting */
fw_config->CodeSegmentStartAddress = (READ_REG(FIREWALL->CSSA) & FW_CSSA_ADD);
fw_config->CodeSegmentLength = (READ_REG(FIREWALL->CSL) & FW_CSL_LENG);
/* Retrieve non volatile data segment protection setting */
fw_config->NonVDataSegmentStartAddress = (READ_REG(FIREWALL->NVDSSA) & FW_NVDSSA_ADD);
fw_config->NonVDataSegmentLength = (READ_REG(FIREWALL->NVDSL) & FW_NVDSL_LENG);
/* Retrieve volatile data segment protection setting */
fw_config->VDataSegmentStartAddress = (READ_REG(FIREWALL->VDSSA) & FW_VDSSA_ADD);
fw_config->VDataSegmentLength = (READ_REG(FIREWALL->VDSL) & FW_VDSL_LENG);
fw_config->VDataSegmentLength = (READ_REG(FIREWALL->VDSL) & FW_VDSL_LENG);
/* Retrieve volatile data execution setting */
fw_config->VolatileDataExecution = (READ_REG(FIREWALL->CR) & FW_CR_VDE);
/* Retrieve volatile data shared setting */
fw_config->VolatileDataShared = (READ_REG(FIREWALL->CR) & FW_CR_VDS);
return;
}
/**
* @brief Enable FIREWALL.
* @brief Enable FIREWALL.
* @note Firewall is enabled in clearing FWDIS bit of SYSCFG CFGR1 register.
* Once enabled, the Firewall cannot be disabled by software. Only a
* system reset can set again FWDIS bit.
* Once enabled, the Firewall cannot be disabled by software. Only a
* system reset can set again FWDIS bit.
* @retval None
*/
void HAL_FIREWALL_EnableFirewall(void)
{
/* Clears FWDIS bit of SYSCFG CFGR1 register */
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS);
}
/**
* @brief Enable FIREWALL pre arm.
* @note When FPA bit is set, any code executed outside the protected segment
* will close the Firewall.
* @brief Enable FIREWALL pre arm.
* @note When FPA bit is set, any code executed outside the protected segment
* will close the Firewall.
* @note This API provides the same service as __HAL_FIREWALL_PREARM_ENABLE() macro
* but can't be executed inside a code area protected by the Firewall.
* @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time.
* @note When the Firewall is enabled and NVDSL register is equal to 0 (that is,
* but can't be executed inside a code area protected by the Firewall.
* @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time.
* @note When the Firewall is enabled and NVDSL register is equal to 0 (that is,
* when the non volatile data segment is not defined),
* ** this API can be executed when the Firewall is closed
* ** when the Firewall is opened, user should resort to
* ** when the Firewall is opened, user should resort to
* __HAL_FIREWALL_PREARM_ENABLE() macro instead
* @note When the Firewall is enabled and NVDSL register is different from 0
* (that is, when the non volatile data segment is defined)
* ** FW_CR register can be accessed only when the Firewall is opened:
* user should resort to __HAL_FIREWALL_PREARM_ENABLE() macro instead.
* ** FW_CR register can be accessed only when the Firewall is opened:
* user should resort to __HAL_FIREWALL_PREARM_ENABLE() macro instead.
* @retval None
*/
void HAL_FIREWALL_EnablePreArmFlag(void)
@ -263,21 +268,21 @@ void HAL_FIREWALL_EnablePreArmFlag(void)
/**
* @brief Disable FIREWALL pre arm.
* @note When FPA bit is reset, any code executed outside the protected segment
* @note When FPA bit is reset, any code executed outside the protected segment
* when the Firewall is opened will generate a system reset.
* @note This API provides the same service as __HAL_FIREWALL_PREARM_DISABLE() macro
* but can't be executed inside a code area protected by the Firewall.
* @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time.
* @note When the Firewall is enabled and NVDSL register is equal to 0 (that is,
* @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time.
* @note When the Firewall is enabled and NVDSL register is equal to 0 (that is,
* when the non volatile data segment is not defined),
* ** this API can be executed when the Firewall is closed
* ** when the Firewall is opened, user should resort to
* ** when the Firewall is opened, user should resort to
* __HAL_FIREWALL_PREARM_DISABLE() macro instead
* @note When the Firewall is enabled and NVDSL register is different from 0
* (that is, when the non volatile data segment is defined)
* ** FW_CR register can be accessed only when the Firewall is opened:
* user should resort to __HAL_FIREWALL_PREARM_DISABLE() macro instead.
* ** FW_CR register can be accessed only when the Firewall is opened:
* user should resort to __HAL_FIREWALL_PREARM_DISABLE() macro instead.
* @retval None
*/
void HAL_FIREWALL_DisablePreArmFlag(void)

2
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_flash_ex.c
View file

@ -122,7 +122,7 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PC
*/
/* Exported functions -------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions
/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
* @{
*/

38
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_gfxmmu.c
View file

@ -127,7 +127,7 @@
/**
* @brief Initialize the GFXMMU according to the specified parameters in the
* GFXMMU_InitTypeDef structure and initialize the associated handle.
* @param hgfxmmu : GFXMMU handle.
* @param hgfxmmu GFXMMU handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu)
@ -184,7 +184,7 @@ HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu)
/**
* @brief De-initialize the GFXMMU.
* @param hgfxmmu : GFXMMU handle.
* @param hgfxmmu GFXMMU handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu)
@ -217,7 +217,7 @@ HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu)
/**
* @brief Initialize the GFXMMU MSP.
* @param hgfxmmu : GFXMMU handle.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
__weak void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu)
@ -232,7 +232,7 @@ __weak void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu)
/**
* @brief De-initialize the GFXMMU MSP.
* @param hgfxmmu : GFXMMU handle.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
__weak void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu)
@ -266,12 +266,12 @@ __weak void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu)
/**
* @brief This function allows to copy LUT from flash to look up RAM.
* @param hgfxmmu : GFXMMU handle.
* @param FirstLine : First line enabled on LUT.
* @param hgfxmmu GFXMMU handle.
* @param FirstLine First line enabled on LUT.
* This parameter must be a number between Min_Data = 0 and Max_Data = 1023.
* @param LinesNumber : Number of lines enabled on LUT.
* @param LinesNumber Number of lines enabled on LUT.
* This parameter must be a number between Min_Data = 1 and Max_Data = 1024.
* @param Address : Start address of LUT in flash.
* @param Address Start address of LUT in flash.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu,
@ -319,10 +319,10 @@ HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu,
/**
* @brief This function allows to disable a range of LUT lines.
* @param hgfxmmu : GFXMMU handle.
* @param FirstLine : First line to disable on LUT.
* @param hgfxmmu GFXMMU handle.
* @param FirstLine First line to disable on LUT.
* This parameter must be a number between Min_Data = 0 and Max_Data = 1023.
* @param LinesNumber : Number of lines to disable on LUT.
* @param LinesNumber Number of lines to disable on LUT.
* This parameter must be a number between Min_Data = 1 and Max_Data = 1024.
* @retval HAL status.
*/
@ -367,8 +367,8 @@ HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu,
/**
* @brief This function allows to configure one line of LUT.
* @param hgfxmmu : GFXMMU handle.
* @param lutLine : LUT line parameters.
* @param hgfxmmu GFXMMU handle.
* @param lutLine LUT line parameters.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine)
@ -418,8 +418,8 @@ HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU
/**
* @brief This function allows to modify physical buffer addresses.
* @param hgfxmmu : GFXMMU handle.
* @param Buffers : Buffers parameters.
* @param hgfxmmu GFXMMU handle.
* @param Buffers Buffers parameters.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers)
@ -452,7 +452,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU
/**
* @brief This function handles the GFXMMU interrupts.
* @param hgfxmmu : GFXMMU handle.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu)
@ -479,7 +479,7 @@ void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu)
/**
* @brief Error callback.
* @param hgfxmmu : GFXMMU handle.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
__weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu)
@ -512,7 +512,7 @@ __weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu)
/**
* @brief This function allows to get the current GFXMMU handle state.
* @param hgfxmmu : GFXMMU handle.
* @param hgfxmmu GFXMMU handle.
* @retval GFXMMU state.
*/
HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu)
@ -523,7 +523,7 @@ HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu)
/**
* @brief This function allows to get the current GFXMMU error code.
* @param hgfxmmu : GFXMMU handle.
* @param hgfxmmu GFXMMU handle.
* @retval GFXMMU error code.
*/
uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu)

50
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_i2c.c
View file

@ -301,8 +301,8 @@
/* Private macro -------------------------------------------------------------*/
#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \
((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \
((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR)))
((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmatx->Instance)->CNDTR)) : \
((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmarx->Instance)->CNDTR)))
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@ -4584,20 +4584,31 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/* Check if a STOPF is detected */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
{
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Check if an RXNE is pending */
/* Store Last receive data if any */
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
{
/* Return HAL_OK */
/* The Reading of data from RXDR will be done in caller function */
return HAL_OK;
}
else
{
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
return HAL_ERROR;
}
}
/* Check for the Timeout */
@ -4691,25 +4702,14 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
*/
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
/* Get the CR2 register value */
tmpreg = hi2c->Instance->CR2;
/* clear tmpreg specific bits */
tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
/* update tmpreg */
tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16) & I2C_CR2_NBYTES) | \
(uint32_t)Mode | (uint32_t)Request);
/* update CR2 register */
hi2c->Instance->CR2 = tmpreg;
MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
(uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
}
/**

8
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_i2c_ex.c
View file

@ -17,7 +17,8 @@
(+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter
(+) Disable or enable wakeup from Stop modes
(+) Disable or enable wakeup from Stop mode(s)
(+) Disable or enable Fast Mode Plus
##### How to use this driver #####
==============================================================================
@ -96,6 +97,7 @@
[..] This section provides functions allowing to:
(+) Configure Noise Filters
(+) Configure Wake Up Feature
(+) Configure Fast Mode Plus
@endverbatim
* @{
@ -198,7 +200,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
}
/**
* @brief Enable I2C wakeup from stop mode.
* @brief Enable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
@ -237,7 +239,7 @@ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
}
/**
* @brief Disable I2C wakeup from stop mode.
* @brief Disable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status

19
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_ltdc.c
View file

@ -40,21 +40,20 @@
value, the window size, the window position and the layer start address
for foreground or/and background layer using respectively the following
functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.
HAL_LTDC_SetWindowPosition() and HAL_LTDC_SetAddress().
(#) Variant functions with “_NoReload” post fix allows to set the LTDC configuration/settings without immediate reload.
(#) Variant functions with _NoReload suffix allows to set the LTDC configuration/settings without immediate reload.
This is useful in case when the program requires to modify serval LTDC settings (on one or both layers)
then applying(reload) these settings in one shot by calling the function “HAL_LTDC_Reload”
then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload().
After calling the “_NoReload” functions to set different color/format/layer settings,
the program can call the function “HAL_LTDC_Reload” To apply(Reload) these settings.
Function “HAL_LTDC_Reload” can be called with the parameter “ReloadType”
set to LTDC_RELOAD_IMMEDIATE if an immediate reload is required.
Function “HAL_LTDC_Reload” can be called with the parameter “ReloadType”
set to LTDC_RELOAD_VERTICAL_BLANKING if the reload should be done in the next vertical blanking period,
After calling the _NoReload functions to set different color/format/layer settings,
the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings.
Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if
an immediate reload is required.
Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_VERTICAL_BLANKING if
the reload should be done in the next vertical blanking period,
this option allows to avoid display flicker by applying the new settings during the vertical blanking period.
(#) To control LTDC state you can use the following function: HAL_LTDC_GetState()
*** LTDC HAL driver macros list ***

2
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_ospi.c
View file

@ -1447,6 +1447,7 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData
* @param cfg : structure that contains the polling configuration information.
* @param Timeout : Timeout duration
* @note This function is used only in Automatic Polling Mode
* @note This function should not be used when the memory is in octal mode (see Errata Sheet)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
@ -1522,6 +1523,7 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPolli
* @param hospi : OSPI handle
* @param cfg : structure that contains the polling configuration information.
* @note This function is used only in Automatic Polling Mode
* @note This function should not be used when the memory is in octal mode (see Errata Sheet)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg)

266
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_qspi.c
View file

@ -241,7 +241,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
/**
* @brief Initialize the QSPI mode according to the specified parameters
* in the QSPI_InitTypeDef and initialize the associated handle.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
@ -331,7 +331,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
/**
* @brief De-Initialize the QSPI peripheral.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
@ -365,10 +365,10 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
/**
* @brief Initialize the QSPI MSP.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
@ -380,10 +380,10 @@ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
/**
* @brief DeInitialize the QSPI MSP.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
@ -419,7 +419,7 @@ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
/**
* @brief Handle QSPI interrupt request.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
@ -429,7 +429,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
uint32_t itsource = READ_REG(hqspi->Instance->CR);
/* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
if((flag & QSPI_FLAG_FT) && (itsource & QSPI_IT_FT))
if(((flag & QSPI_FLAG_FT) != 0) && ((itsource & QSPI_IT_FT) !=0 ))
{
data_reg = &hqspi->Instance->DR;
@ -441,7 +441,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
if (hqspi->TxXferCount > 0)
{
/* Fill the FIFO until the threshold is reached */
*(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
*(__IO uint8_t *)((__IO void *)data_reg) = *hqspi->pTxBuffPtr++;
hqspi->TxXferCount--;
}
else
@ -461,7 +461,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
if (hqspi->RxXferCount > 0)
{
/* Read the FIFO until the threshold is reached */
*hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
*hqspi->pRxBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg);
hqspi->RxXferCount--;
}
else
@ -479,7 +479,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* QSPI Transfer Complete interrupt occurred -------------------------------*/
else if((flag & QSPI_FLAG_TC) && (itsource & QSPI_IT_TC))
else if(((flag & QSPI_FLAG_TC) != 0) && ((itsource & QSPI_IT_TC) != 0))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
@ -490,7 +490,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
/* Transfer complete callback */
if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
{
if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@ -512,7 +512,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
{
if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@ -528,7 +528,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
if (hqspi->RxXferCount > 0)
{
/* Read the last data received in the FIFO until it is empty */
*hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
*hqspi->pRxBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg);
hqspi->RxXferCount--;
}
else
@ -581,7 +581,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* QSPI Status Match interrupt occurred ------------------------------------*/
else if((flag & QSPI_FLAG_SM) && (itsource & QSPI_IT_SM))
else if(((flag & QSPI_FLAG_SM) != 0) && ((itsource & QSPI_IT_SM) != 0))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
@ -601,7 +601,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* QSPI Transfer Error interrupt occurred ----------------------------------*/
else if((flag & QSPI_FLAG_TE) && (itsource & QSPI_IT_TE))
else if(((flag & QSPI_FLAG_TE) != 0) && ((itsource & QSPI_IT_TE) != 0))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
@ -612,7 +612,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
/* Set error code */
hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@ -625,14 +625,14 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
{
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
/* Error callback */
HAL_QSPI_ErrorCallback(hqspi);
}
}
/* QSPI Timeout interrupt occurred -----------------------------------------*/
else if((flag & QSPI_FLAG_TO) && (itsource & QSPI_IT_TO))
else if(((flag & QSPI_FLAG_TO) != 0) && ((itsource & QSPI_IT_TO) != 0))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
@ -644,7 +644,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
/**
* @brief Set the command configuration.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information
* @param Timeout : Timeout duration
* @note This function is used only in Indirect Read or Write Modes
@ -734,7 +734,7 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe
/**
* @brief Set the command configuration in interrupt mode.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information
* @note This function is used only in Indirect Read or Write Modes
* @retval HAL status
@ -822,19 +822,19 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp
else
{
status = HAL_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
/* Return function status */
return status;
}
/**
* @brief Transmit an amount of data in blocking mode.
* @param hqspi: QSPI handle
* @param pData: pointer to data buffer
* @param hqspi : QSPI handle
* @param pData : pointer to data buffer
* @param Timeout : Timeout duration
* @note This function is used only in Indirect Write Mode
* @retval HAL status
@ -851,7 +851,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u
if(hqspi->State == HAL_QSPI_STATE_READY)
{
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
if(pData != NULL )
{
/* Update state */
@ -875,7 +875,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u
break;
}
*(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
*(__IO uint8_t *)((__IO void *)data_reg) = *hqspi->pTxBuffPtr++;
hqspi->TxXferCount--;
}
@ -919,8 +919,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u
/**
* @brief Receive an amount of data in blocking mode.
* @param hqspi: QSPI handle
* @param pData: pointer to data buffer
* @param hqspi : QSPI handle
* @param pData : pointer to data buffer
* @param Timeout : Timeout duration
* @note This function is used only in Indirect Read Mode
* @retval HAL status
@ -965,7 +965,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
break;
}
*hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
*hqspi->pRxBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg);
hqspi->RxXferCount--;
}
@ -975,7 +975,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
if (status == HAL_OK)
{
{
/* Clear Transfer Complete bit */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
@ -1008,8 +1008,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
/**
* @brief Send an amount of data in non-blocking mode with interrupt.
* @param hqspi: QSPI handle
* @param pData: pointer to data buffer
* @param hqspi : QSPI handle
* @param pData : pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
@ -1068,8 +1068,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData
/**
* @brief Receive an amount of data in non-blocking mode with interrupt.
* @param hqspi: QSPI handle
* @param pData: pointer to data buffer
* @param hqspi : QSPI handle
* @param pData : pointer to data buffer
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@ -1132,8 +1132,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
/**
* @brief Send an amount of data in non-blocking mode with DMA.
* @param hqspi: QSPI handle
* @param pData: pointer to data buffer
* @param hqspi : QSPI handle
* @param pData : pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @note If DMA peripheral access is configured as halfword, the number
* of data and the fifo threshold should be aligned on halfword
@ -1170,7 +1170,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat
=> no transfer possible with DMA peripheral access configured as halfword */
hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
@ -1201,43 +1201,43 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat
{
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
/* Configure size and pointer of the handle */
hqspi->TxXferSize = hqspi->TxXferCount;
hqspi->pTxBuffPtr = pData;
/* Configure QSPI: CCR register with functional mode as indirect write */
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
/* Set the QSPI DMA transfer complete callback */
hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
/* Set the QSPI DMA Half transfer complete callback */
hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
/* Set the DMA error callback */
hqspi->hdma->XferErrorCallback = QSPI_DMAError;
/* Clear the DMA abort callback */
hqspi->hdma->XferAbortCallback = NULL;
/* Configure the direction of the DMA */
hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);
/* Enable the QSPI transmit DMA Channel */
tmp = (uint32_t*)&pData;
tmp = (uint32_t*)((void*)&pData);
HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
/* Process unlocked */
__HAL_UNLOCK(hqspi);
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
}
@ -1246,7 +1246,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat
{
hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
@ -1254,18 +1254,18 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat
else
{
status = HAL_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
return status;
}
/**
* @brief Receive an amount of data in non-blocking mode with DMA.
* @param hqspi: QSPI handle
* @param pData: pointer to data buffer.
* @param hqspi : QSPI handle
* @param pData : pointer to data buffer.
* @note This function is used only in Indirect Read Mode
* @note If DMA peripheral access is configured as halfword, the number
* of data and the fifo threshold should be aligned on halfword
@ -1288,7 +1288,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
/* Clear the error code */
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
if(pData != NULL)
if(pData != NULL )
{
/* Configure counters of the handle */
if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
@ -1320,7 +1320,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
=> no transfer possible with DMA peripheral access configured as word */
hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
@ -1334,46 +1334,46 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
{
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
/* Configure size and pointer of the handle */
hqspi->RxXferSize = hqspi->RxXferCount;
hqspi->pRxBuffPtr = pData;
/* Set the QSPI DMA transfer complete callback */
hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
/* Set the QSPI DMA Half transfer complete callback */
hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
/* Set the DMA error callback */
hqspi->hdma->XferErrorCallback = QSPI_DMAError;
/* Clear the DMA abort callback */
hqspi->hdma->XferAbortCallback = NULL;
/* Configure the direction of the DMA */
hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);
/* Enable the DMA Channel */
tmp = (uint32_t*)&pData;
tmp = (uint32_t*)((void*)&pData);
HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
/* Configure QSPI: CCR register with functional as indirect read */
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
/* Start the transfer by re-writing the address in AR register */
WRITE_REG(hqspi->Instance->AR, addr_reg);
/* Process unlocked */
__HAL_UNLOCK(hqspi);
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
}
@ -1400,9 +1400,9 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
/**
* @brief Configure the QSPI Automatic Polling Mode in blocking mode.
* @param hqspi: QSPI handle
* @param cmd: structure that contains the command configuration information.
* @param cfg: structure that contains the polling configuration information.
* @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information.
* @param cfg : structure that contains the polling configuration information.
* @param Timeout : Timeout duration
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
@ -1501,9 +1501,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy
/**
* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
* @param hqspi: QSPI handle
* @param cmd: structure that contains the command configuration information.
* @param cfg: structure that contains the polling configuration information.
* @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information.
* @param cfg : structure that contains the polling configuration information.
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
@ -1594,7 +1594,7 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman
else
{
status = HAL_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
@ -1605,9 +1605,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman
/**
* @brief Configure the Memory Mapped mode.
* @param hqspi: QSPI handle
* @param cmd: structure that contains the command configuration information.
* @param cfg: structure that contains the memory mapped configuration information.
* @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information.
* @param cfg : structure that contains the memory mapped configuration information.
* @note This function is used only in Memory mapped Mode
* @retval HAL status
*/
@ -1660,9 +1660,9 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT
if (status == HAL_OK)
{
/* Configure QSPI: CR register with timeout counter enable */
MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
{
assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
@ -1694,7 +1694,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT
/**
* @brief Transfer Error callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
@ -1709,7 +1709,7 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Abort completed callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
@ -1724,7 +1724,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Command completed callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
@ -1739,7 +1739,7 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Rx Transfer completed callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
@ -1754,7 +1754,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Tx Transfer completed callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
@ -1769,7 +1769,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Rx Half Transfer completed callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
@ -1784,10 +1784,10 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Tx Half Transfer completed callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
@ -1799,7 +1799,7 @@ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief FIFO Threshold callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
@ -1814,7 +1814,7 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Status Match callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
@ -1829,7 +1829,7 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Timeout callback.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
@ -1866,7 +1866,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Return the QSPI handle state.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval HAL state
*/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
@ -1877,7 +1877,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
/**
* @brief Return the QSPI error code.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval QSPI Error Code
*/
uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
@ -1887,7 +1887,7 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
/**
* @brief Abort the current transmission.
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
@ -1901,11 +1901,11 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
/* Process unlocked */
__HAL_UNLOCK(hqspi);
if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
/* Abort DMA channel */
status = HAL_DMA_Abort(hqspi->hdma);
if(status != HAL_OK)
@ -1913,21 +1913,21 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
}
}
/* Configure QSPI: CR register with Abort request */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
/* Wait until TC flag is set to go back in idle state */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
if(status == HAL_OK)
{
if (status == HAL_OK)
{
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
/* Wait until BUSY flag is reset */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
}
if (status == HAL_OK)
{
/* Update state */
@ -1940,7 +1940,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
/**
* @brief Abort the current transmission (non-blocking function)
* @param hqspi: QSPI handle
* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
@ -1952,18 +1952,18 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
{
/* Process unlocked */
__HAL_UNLOCK(hqspi);
/* Update QSPI state */
hqspi->State = HAL_QSPI_STATE_ABORT;
/* Disable all interrupts */
__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
/* Abort DMA channel */
hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
HAL_DMA_Abort_IT(hqspi->hdma);
@ -1972,10 +1972,10 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
{
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
/* Enable the QSPI Transfer Complete Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
/* Configure QSPI: CR register with Abort request */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
}
@ -1984,8 +1984,8 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
}
/** @brief Set QSPI timeout.
* @param hqspi: QSPI handle.
* @param Timeout: Timeout for the QSPI memory access.
* @param hqspi : QSPI handle.
* @param Timeout : Timeout for the QSPI memory access.
* @retval None
*/
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
@ -1994,8 +1994,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
}
/** @brief Set QSPI Fifo threshold.
* @param hqspi: QSPI handle.
* @param Threshold: Threshold of the Fifo (value between 1 and 16).
* @param hqspi : QSPI handle.
* @param Threshold : Threshold of the Fifo (value between 1 and 16).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
@ -2027,7 +2027,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t
}
/** @brief Get QSPI Fifo threshold.
* @param hqspi: QSPI handle.
* @param hqspi : QSPI handle.
* @retval Fifo threshold (value between 1 and 16)
*/
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
@ -2041,7 +2041,7 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
/**
* @brief DMA QSPI receive process complete callback.
* @param hdma: DMA handle
* @param hdma : DMA handle
* @retval None
*/
static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
@ -2055,7 +2055,7 @@ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA QSPI transmit process complete callback.
* @param hdma: DMA handle
* @param hdma : DMA handle
* @retval None
*/
static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
@ -2093,7 +2093,7 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA QSPI communication error callback.
* @param hdma: DMA handle
* @param hdma : DMA handle
* @retval None
*/
static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
@ -2113,7 +2113,7 @@ static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
/**
* @brief DMA QSPI abort complete callback.
* @param hdma: DMA handle
* @param hdma : DMA handle
* @retval None
*/
static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
@ -2140,7 +2140,7 @@ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
/* DMA Abort called due to a transfer error interrupt */
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
/* Error callback */
HAL_QSPI_ErrorCallback(hqspi);
}
@ -2148,18 +2148,18 @@ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
/**
* @brief Wait for a flag state until timeout.
* @param hqspi: QSPI handle
* @param Flag: Flag checked
* @param State: Value of the flag expected
* @param Timeout: Duration of the timeout
* @param hqspi : QSPI handle
* @param Flag : Flag checked
* @param State : Value of the flag expected
* @param Timeout : Duration of the timeout
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is in expected state */
while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
@ -2178,9 +2178,9 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp
/**
* @brief Configure the communication registers.
* @param hqspi: QSPI handle
* @param cmd: structure that contains the command configuration information
* @param FunctionalMode: functional mode to configured
* @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information
* @param FunctionalMode : functional mode to configured
* This parameter can be one of the following values:
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode

413
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rcc_ex.c
View file

File diff suppressed because it is too large Load diff

31
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rng.c
View file

@ -120,17 +120,14 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
{
return HAL_ERROR;
}
assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
#if defined(RNG_CR_CED)
assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection));
#endif /* defined(RNG_CR_CED) */
#if defined(RNG_CR_BYP)
assert_param(IS_RNG_BYPASS(hrng->Init.BypassMode));
#endif /* defined(RNG_CR_BYP) */
__HAL_LOCK(hrng);
if(hrng->State == HAL_RNG_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@ -139,7 +136,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
/* Init the low level hardware */
HAL_RNG_MspInit(hrng);
}
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
@ -147,11 +144,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
/* Clock Error Detection configuration */
MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection);
#endif /* defined(RNG_CR_CED) */
#if defined(RNG_CR_BYP)
/* Bypass mode configuration */
MODIFY_REG(hrng->Instance->CR, RNG_CR_BYP, hrng->Init.BypassMode);
#endif /* defined(RNG_CR_BYP) */
/* Enable the RNG Peripheral */
__HAL_RNG_ENABLE(hrng);
@ -181,26 +174,22 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
/* Clear Clock Error Detection bit */
CLEAR_BIT(hrng->Instance->CR, RNG_CR_CED);
#endif /* defined(RNG_CR_CED) */
#if defined(RNG_CR_BYP)
/* Clear Bypass mode bit */
CLEAR_BIT(hrng->Instance->CR, RNG_CR_BYP);
#endif /* defined(RNG_CR_BYP) */
/* Disable the RNG Peripheral */
CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
/* Clear RNG interrupt status flags */
CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
/* DeInit the low level hardware */
HAL_RNG_MspDeInit(hrng);
/* Update the RNG state */
hrng->State = HAL_RNG_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hrng);
/* Return the function status */
return HAL_OK;
}

3
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_sai.c
View file

@ -734,17 +734,14 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
(+) Blocking mode functions are :
(++) HAL_SAI_Transmit()
(++) HAL_SAI_Receive()
(++) HAL_SAI_TransmitReceive()
(+) Non Blocking mode functions with Interrupt are :
(++) HAL_SAI_Transmit_IT()
(++) HAL_SAI_Receive_IT()
(++) HAL_SAI_TransmitReceive_IT()
(+) Non Blocking mode functions with DMA are :
(++) HAL_SAI_Transmit_DMA()
(++) HAL_SAI_Receive_DMA()
(++) HAL_SAI_TransmitReceive_DMA()
(+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_SAI_TxCpltCallback()

85
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_sd.c
View file

@ -716,7 +716,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
hsd->State = HAL_SD_STATE_READY;
@ -897,7 +897,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
}
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
hsd->State = HAL_SD_STATE_READY;
@ -1529,11 +1529,12 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND);
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\
SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\
SDMMC_IT_RXFIFOHF);
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
__HAL_SD_DISABLE_IT(hsd, SDMMC_FLAG_IDMATE | SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_RXFIFOHF);
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
__SDMMC_CMDTRANS_DISABLE( hsd->Instance);
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
@ -1550,7 +1551,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
}
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
hsd->State = HAL_SD_STATE_READY;
if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
@ -1615,15 +1616,11 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXFIFOHE) != RESET)
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_TXFIFOHE);
SD_Write_IT(hsd);
}
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXFIFOHF) != RESET)
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXFIFOHF);
SD_Read_IT(hsd);
}
@ -1648,7 +1645,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
}
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
/* Disable all interrupts */
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
@ -1666,6 +1663,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
/* Disable Internal DMA */
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
/* Set the SD state to ready to be able to start again the process */
@ -1705,16 +1703,6 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
}
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_IDMATE) != RESET)
{
__SDMMC_CMDTRANS_DISABLE( hsd->Instance);
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMATE);
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMATE);
HAL_SD_ErrorCallback(hsd);
}
else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_IDMABTC) != RESET)
{
if(READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == SD_DMA_BUFFER0)
@ -1741,7 +1729,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(hsd);
}
}
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_IT_IDMABTC);
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC);
}
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
}
@ -2310,11 +2298,6 @@ HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
cardstate = (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F);
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/* Clear all the static flags */
__SDMMC_CLEAR_FLAG(hsd->Instance, SDMMC_STATIC_FLAGS);
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
return cardstate;
}
@ -2380,14 +2363,17 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
{
HAL_SD_CardStateTypedef CardState;
/* DIsable All interrupts */
/* Disable All interrupts */
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/* If IDMA Context, disable Internal DMA */
hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
CardState = HAL_SD_GetCardState(hsd);
hsd->State = HAL_SD_STATE_READY;
@ -2433,6 +2419,9 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
/* No transfer ongoing on both DMA channels*/
if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL))
{
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
CardState = HAL_SD_GetCardState(hsd);
hsd->State = HAL_SD_STATE_READY;
if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
@ -2506,7 +2495,7 @@ static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
hsd->State = HAL_SD_STATE_READY;
@ -2563,14 +2552,16 @@ static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
/* All DMA channels are aborted */
if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL))
{
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
CardState = HAL_SD_GetCardState(hsd);
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_READY;
if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
if(hsd->ErrorCode == HAL_SD_ERROR_NONE)
{
HAL_SD_AbortCallback(hsd);
}
@ -2600,14 +2591,16 @@ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
/* All DMA channels are aborted */
if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL))
{
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
CardState = HAL_SD_GetCardState(hsd);
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_READY;
if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
if(hsd->ErrorCode == HAL_SD_ERROR_NONE)
{
HAL_SD_AbortCallback(hsd);
}
@ -2874,8 +2867,13 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
return errorstate;
}
/* Check to BusyD0 and CKSTOP */
/* Check to CKSTOP */
while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP);
/* Clear CKSTOP Flag */
hsd->Instance->ICR = SDMMC_FLAG_CKSTOP;
/* Check to BusyD0 */
if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0)
{
/* Error when activate Voltage Switch in SDMMC IP */
@ -2891,6 +2889,10 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
/* Check VSWEND Flag */
while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND);
/* Clear VSWEND Flag */
hsd->Instance->ICR = SDMMC_FLAG_VSWEND;
/* Check BusyD0 status */
if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0)
{
@ -3016,7 +3018,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
}
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)))
while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DPSMACT)))
#else
while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)))
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
@ -3031,7 +3033,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
}
/* Clear all the static status flags*/
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
return HAL_SD_ERROR_NONE;
}
@ -3211,7 +3213,6 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
tempscr[0] = SDMMC_ReadFIFO(hsd->Instance);
tempscr[1] = SDMMC_ReadFIFO(hsd->Instance);
index++;
break;
}
@ -3258,8 +3259,8 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
{
/* No error flag set */
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
*(pSCR + 1) = ((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24);

6
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_sd_ex.c
View file

@ -188,7 +188,7 @@ uint32_t HAL_SDEx_HighSpeed(SD_HandleTypeDef *hsd)
}
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
/* Test if the switch mode HS is ok */
if ((SD_hs[13]& 2) != 2)
@ -333,7 +333,7 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3
hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
__HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
__HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC));
/* Read Blocks in DMA mode */
hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
@ -417,7 +417,7 @@ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint
hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
__HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
__HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC));
/* Write Blocks in DMA mode */
hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);

2
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_smartcard.c
View file

@ -1487,7 +1487,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
#if defined(USART_CR1_FIFOEN)
if( (errorflags != RESET)
&& ( (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET)
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) )
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) )
#else
if( (errorflags != RESET)
&& ( ((cr3its & USART_CR3_EIE) != RESET)

17
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_smbus.c
View file

@ -1683,7 +1683,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
/* or only the last Byte of Transfer */
/* So reset the RELOAD bit mode */
hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
SMBUS_TransferConfig(hsmbus, 0U , 1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
else if (hsmbus->XferCount == 0U)
{
@ -2097,25 +2097,14 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu
*/
static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
/* Get the CR2 register value */
tmpreg = hsmbus->Instance->CR2;
/* clear tmpreg specific bits */
tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE));
/* update tmpreg */
tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U) & I2C_CR2_NBYTES) | \
(uint32_t)Mode | (uint32_t)Request);
/* update CR2 register */
hsmbus->Instance->CR2 = tmpreg;
MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
(uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
}
/**

12
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_tim_ex.c
View file

@ -480,7 +480,6 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -510,7 +509,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -540,7 +538,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -607,7 +604,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -680,7 +676,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @param pData: The source Buffer address.
* @param Length: The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
@ -797,7 +792,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -897,7 +891,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -926,7 +919,6 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -956,7 +948,6 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@ -1023,7 +1014,6 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
@ -1097,7 +1087,6 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @param pData: The source Buffer address.
* @param Length: The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
@ -1214,7 +1203,6 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)

2
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_uart.c
View file

@ -1764,7 +1764,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
#if defined(USART_CR1_FIFOEN)
if( (errorflags != RESET)
&& ( (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET)
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) )
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) )
#else
if( (errorflags != RESET)
&& ( ((cr3its & USART_CR3_EIE) != RESET)

29
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_comp.c
View file

@ -131,14 +131,25 @@
|| ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \
)
#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__) \
( ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \
|| ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) \
|| ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) \
|| ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) \
|| ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2) \
|| ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2) \
|| ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2) \
#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
(((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \
? ( \
(1U) \
) \
: \
(((__COMP_INSTANCE__) == COMP1) \
? ( \
((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) \
|| ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) \
|| ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) \
) \
: \
( \
((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2) \
|| ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2) \
|| ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2) \
) \
) \
)
/**
@ -216,7 +227,7 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru
assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMP_InitStruct->OutputBlankingSource));
assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMPx, COMP_InitStruct->OutputBlankingSource));
/* Note: Hardware constraint (refer to description of this function) */
/* COMP instance must not be locked. */

17
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_dac.c
View file

@ -76,6 +76,22 @@
)
#endif /* DAC_CHANNEL2_SUPPORT */
#if defined (DAC_CR_TSEL1_3)
#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_OUT_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_OUT_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
)
#else
#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
@ -86,6 +102,7 @@
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
)
#endif /* DAC_CR_TSEL1_3 */
#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \

11
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_dma2d.c
View file

@ -71,10 +71,19 @@
/** @addtogroup DMA2D_LL_Private_Macros
* @{
*/
#if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
#define IS_LL_DMA2D_MODE(MODE) (((MODE) == LL_DMA2D_MODE_M2M) || \
((MODE) == LL_DMA2D_MODE_M2M_PFC) || \
((MODE) == LL_DMA2D_MODE_M2M_BLEND) || \
((MODE) == LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG) || \
((MODE) == LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG) || \
((MODE) == LL_DMA2D_MODE_R2M))
#else
#define IS_LL_DMA2D_MODE(MODE) (((MODE) == LL_DMA2D_MODE_M2M) || \
((MODE) == LL_DMA2D_MODE_M2M_PFC) || \
((MODE) == LL_DMA2D_MODE_M2M_BLEND) || \
((MODE) == LL_DMA2D_MODE_R2M))
#endif
#define IS_LL_DMA2D_OCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB8888) || \
((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB888) || \
@ -271,7 +280,7 @@ void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
DMA2D_InitStruct->NbrOfLines = 0x0U;
DMA2D_InitStruct->NbrOfPixelsPerLines = 0x0U;
#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
DMA2D_InitStruct->LineOffset = LL_DMA2D_LINE_OFFSET_PIXELS;
DMA2D_InitStruct->LineOffsetMode = LL_DMA2D_LINE_OFFSET_PIXELS;
#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
DMA2D_InitStruct->LineOffset = 0x0U;
DMA2D_InitStruct->OutputBlue = 0x0U;

81
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_rcc.c
View file

@ -101,6 +101,10 @@
#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
#endif /* RCC_CCIPR_SAI2SEL */
#if defined(RCC_CCIPR2_SDMMCSEL)
#define IS_LL_RCC_SDMMC_KERNELCLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_KERNELCLKSOURCE))
#endif /* RCC_CCIPR2_SDMMCSEL */
#define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
@ -850,6 +854,45 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
return sai_frequency;
}
#if defined(RCC_CCIPR2_SDMMCSEL)
/**
* @brief Return SDMMCx kernel clock frequency
* @param SDMMCxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE
* @retval SDMMC clock frequency (in Hz)
* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
* - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
*/
uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource)
{
uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
/* Check parameter */
assert_param(IS_LL_RCC_SDMMC_KERNELCLKSOURCE(SDMMCxSource));
/* SDMMC1CLK kernel clock frequency */
switch (LL_RCC_GetSDMMCKernelClockSource(SDMMCxSource))
{
case LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK: /* 48MHz clock from internal multiplexor used as SDMMC1 clock source */
sdmmc_frequency = LL_RCC_GetSDMMCClockFreq(LL_RCC_SDMMC1_CLKSOURCE);
break;
case LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP: /* PLL "P" output (PLLSAI3CLK) clock used as SDMMC1 clock source */
if (LL_RCC_PLL_IsReady())
{
sdmmc_frequency = RCC_PLL_GetFreqDomain_SAI();
}
break;
default:
sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
break;
}
return sdmmc_frequency;
}
#endif
/**
* @brief Return SDMMCx clock frequency
* @param SDMMCxSource This parameter can be one of the following values:
@ -896,35 +939,7 @@ uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
break;
#endif
#if defined(LL_RCC_SDMMC1_CLKSOURCE_48CLK)
case LL_RCC_SDMMC1_CLKSOURCE_48CLK: /* 48CLK used as SDMMC1 clock source */
{
if (LL_RCC_HSI48_IsReady())
{
sdmmc_frequency = HSI48_VALUE;
}
else if (LL_RCC_PLL_IsReady())
{
sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
}
else if (LL_RCC_PLLSAI1_IsReady())
{
sdmmc_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
}
else if (LL_RCC_MSI_IsReady())
{
sdmmc_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
(LL_RCC_MSI_IsEnabledRangeSelect() ?
LL_RCC_MSI_GetRange() :
LL_RCC_MSI_GetRangeAfterStandby()));
}
else
{
/* do nothing */
}
}
break;
#elif defined(RCC_HSI48_SUPPORT)
#if defined(RCC_HSI48_SUPPORT)
case LL_RCC_SDMMC1_CLKSOURCE_HSI48: /* HSI48 used as SDMMC1 clock source */
if (LL_RCC_HSI48_IsReady())
{
@ -1216,7 +1231,7 @@ uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
{
dfsdm_frequency = HSI_VALUE;
}
break;
break;
}
return dfsdm_frequency;
@ -1327,7 +1342,7 @@ uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)
octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
break;
}
return octospi_frequency;
}
#endif /* OCTOSPI1 */
@ -1576,7 +1591,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void)
LL_RCC_MSI_GetRangeAfterStandby()));
break;
}
return __LL_RCC_CALC_PLLSAI2_DSI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),
LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR());
}
@ -1801,7 +1816,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void)
LL_RCC_MSI_GetRangeAfterStandby()));
break;
}
return __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),
LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR(), LL_RCC_PLLSAI2_GetDIVR());
}

35
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_rng.c
View file

@ -65,11 +65,7 @@
#define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \
((__MODE__) == LL_RNG_CED_DISABLE))
#endif /* defined(RNG_CR_CED) */
#if defined(RNG_CR_BYP)
#define IS_LL_RNG_BYPASS(__MODE__) (((__MODE__) == LL_RNG_BYP_DISABLE) || \
((__MODE__) == LL_RNG_BYP_ENABLE))
#endif /* defined(RNG_CR_BYP) */
/**
* @}
*/
@ -106,7 +102,7 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
return (SUCCESS);
}
#if defined(RNG_CR_CED) || defined(RNG_CR_BYP)
#if defined(RNG_CR_CED)
/**
* @brief Initialize RNG registers according to the specified parameters in RNG_InitStruct.
* @param RNGx RNG Instance
@ -120,26 +116,27 @@ ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
{
/* Check the parameters */
assert_param(IS_RNG_ALL_INSTANCE(RNGx));
#if defined(RNG_CR_CED)
assert_param(IS_LL_RNG_CED(RNG_InitStruct->ClockErrorDetection));
#endif /* defined(RNG_CR_CED) */
#if defined(RNG_CR_BYP)
assert_param(IS_LL_RNG_BYPASS(RNG_InitStruct->BypassMode));
#endif /* defined(RNG_CR_BYP) */
#if defined(RNG_CR_CED)
/* Clock Error Detection configuration */
MODIFY_REG(RNGx->CR, RNG_CR_CED, RNG_InitStruct->ClockErrorDetection);
#endif /* defined(RNG_CR_CED) */
#if defined(RNG_CR_BYP)
/* Bypass mode configuration */
MODIFY_REG(RNGx->CR, RNG_CR_BYP, RNG_InitStruct->BypassMode);
#endif /* defined(RNG_CR_BYP) */
return (SUCCESS);
}
#endif /* defined(RNG_CR_CED) || defined(RNG_CR_BYP) */
/**
* @brief Set each @ref LL_RNG_InitTypeDef field to default value.
* @param RNG_InitStruct: pointer to a @ref LL_RNG_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct)
{
/* Set RNG_InitStruct fields to default values */
RNG_InitStruct->ClockErrorDetection = LL_RNG_CED_ENABLE;
}
#endif /* defined(RNG_CR_CED) */
/**
* @}

19
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_sdmmc.c
View file

@ -1221,7 +1221,7 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
}while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));
/* Clear all the static flags */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
return SDMMC_ERROR_NONE;
}
@ -1272,7 +1272,7 @@ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_
}
/* Clear all the static flags */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
/* We have received response, retrieve it for analysis */
response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
@ -1395,7 +1395,7 @@ static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx)
{
/* No error flag set */
/* Clear all the static flags */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
}
return SDMMC_ERROR_NONE;
@ -1428,10 +1428,9 @@ static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
}
else
{
/* Clear all the static flags */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
}
return SDMMC_ERROR_NONE;
@ -1482,7 +1481,7 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_
}
/* Clear all the static flags */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
/* We have received response, retrieve it. */
response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
@ -1535,6 +1534,14 @@ static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
}
else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
{
/* Card is SD V2.0 compliant */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
return SDMMC_ERROR_CMD_CRC_FAIL;
}
if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND))
{
/* Card is SD V2.0 compliant */

394
ext/hal/st/stm32cube/stm32l4xx/soc/stm32l4r5xx.h
View file

@ -176,8 +176,6 @@ typedef enum
I2C4_ER_IRQn = 84, /*!< I2C4 Error interrupt */
DCMI_IRQn = 85, /*!< DCMI global interrupt */
DMA2D_IRQn = 90, /*!< DMA2D global interrupt */
LTDC_IRQn = 91, /*!< LTDC global Interrupt */
LTDC_ER_IRQn = 92, /*!< LTDC Error global Interrupt */
DMAMUX1_OVR_IRQn = 94 /*!< DMAMUX1 overrun global interrupt */
} IRQn_Type;
@ -698,54 +696,6 @@ typedef struct
__IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
} LPTIM_TypeDef;
/**
* @brief LCD-TFT Display Controller
*/
typedef struct
{
uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
__IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
__IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
__IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
__IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
__IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
__IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
__IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
__IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
__IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
__IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
__IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
__IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
__IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
} LTDC_TypeDef;
/**
* @brief LCD-TFT Display layer x Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
__IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
__IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
__IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
__IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
__IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
__IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
__IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
uint32_t RESERVED0[2]; /*!< Reserved */
__IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
__IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
__IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
uint32_t RESERVED1[3]; /*!< Reserved */
__IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
} LTDC_Layer_TypeDef;
/**
* @brief Operational Amplifier (OPAMP)
*/
@ -1390,9 +1340,6 @@ typedef struct
#define SAI2_BASE (APB2PERIPH_BASE + 0x5800U)
#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
@ -1569,9 +1516,6 @@ typedef struct
#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
@ -10601,289 +10545,6 @@ typedef struct
#define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
/******************************************************************************/
/* */
/* LCD-TFT Display Controller (LTDC) */
/* */
/******************************************************************************/
/******************** Bit definition for LTDC_SSCR register *****************/
#define LTDC_SSCR_VSH_Pos (0U)
#define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
#define LTDC_SSCR_HSW_Pos (16U)
#define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
/******************** Bit definition for LTDC_BPCR register *****************/
#define LTDC_BPCR_AVBP_Pos (0U)
#define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
#define LTDC_BPCR_AHBP_Pos (16U)
#define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
/******************** Bit definition for LTDC_AWCR register *****************/
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
/******************** Bit definition for LTDC_TWCR register *****************/
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
/******************** Bit definition for LTDC_GCR register ******************/
#define LTDC_GCR_LTDCEN_Pos (0U)
#define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
#define LTDC_GCR_DBW_Pos (4U)
#define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
#define LTDC_GCR_DGW_Pos (8U)
#define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
#define LTDC_GCR_DRW_Pos (12U)
#define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
#define LTDC_GCR_DEN_Pos (16U)
#define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
#define LTDC_GCR_PCPOL_Pos (28U)
#define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
#define LTDC_GCR_DEPOL_Pos (29U)
#define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
#define LTDC_GCR_VSPOL_Pos (30U)
#define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
#define LTDC_GCR_HSPOL_Pos (31U)
#define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
/******************** Bit definition for LTDC_SRCR register *****************/
#define LTDC_SRCR_IMR_Pos (0U)
#define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
#define LTDC_SRCR_VBR_Pos (1U)
#define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
/******************** Bit definition for LTDC_BCCR register *****************/
#define LTDC_BCCR_BCBLUE_Pos (0U)
#define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
#define LTDC_BCCR_BCGREEN_Pos (8U)
#define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
#define LTDC_BCCR_BCRED_Pos (16U)
#define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
/******************** Bit definition for LTDC_IER register ******************/
#define LTDC_IER_LIE_Pos (0U)
#define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
#define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
#define LTDC_IER_FUIE_Pos (1U)
#define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
#define LTDC_IER_TERRIE_Pos (2U)
#define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
#define LTDC_IER_RRIE_Pos (3U)
#define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
/******************** Bit definition for LTDC_ISR register ******************/
#define LTDC_ISR_LIF_Pos (0U)
#define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
#define LTDC_ISR_FUIF_Pos (1U)
#define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
#define LTDC_ISR_TERRIF_Pos (2U)
#define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
#define LTDC_ISR_RRIF_Pos (3U)
#define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
/******************** Bit definition for LTDC_ICR register ******************/
#define LTDC_ICR_CLIF_Pos (0U)
#define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
#define LTDC_ICR_CFUIF_Pos (1U)
#define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
#define LTDC_ICR_CTERRIF_Pos (2U)
#define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
#define LTDC_ICR_CRRIF_Pos (3U)
#define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
/******************** Bit definition for LTDC_LIPCR register ****************/
#define LTDC_LIPCR_LIPOS_Pos (0U)
#define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
/******************** Bit definition for LTDC_CPSR register *****************/
#define LTDC_CPSR_CYPOS_Pos (0U)
#define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
#define LTDC_CPSR_CXPOS_Pos (16U)
#define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
/******************** Bit definition for LTDC_CDSR register *****************/
#define LTDC_CDSR_VDES_Pos (0U)
#define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
#define LTDC_CDSR_HDES_Pos (1U)
#define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
#define LTDC_CDSR_VSYNCS_Pos (2U)
#define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
#define LTDC_CDSR_HSYNCS_Pos (3U)
#define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
/******************** Bit definition for LTDC_LxCR register *****************/
#define LTDC_LxCR_LEN_Pos (0U)
#define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
#define LTDC_LxCR_COLKEN_Pos (1U)
#define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
#define LTDC_LxCR_CLUTEN_Pos (4U)
#define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
/******************** Bit definition for LTDC_LxWHPCR register **************/
#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0x0FFF0000 */
#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
/******************** Bit definition for LTDC_LxWVPCR register **************/
#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0x0FFF0000 */
#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
/******************** Bit definition for LTDC_LxCKCR register ***************/
#define LTDC_LxCKCR_CKBLUE_Pos (0U)
#define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
#define LTDC_LxCKCR_CKGREEN_Pos (8U)
#define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
#define LTDC_LxCKCR_CKRED_Pos (16U)
#define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
/******************** Bit definition for LTDC_LxPFCR register ***************/
#define LTDC_LxPFCR_PF_Pos (0U)
#define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
/******************** Bit definition for LTDC_LxCACR register ***************/
#define LTDC_LxCACR_CONSTA_Pos (0U)
#define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
/******************** Bit definition for LTDC_LxDCCR register ***************/
#define LTDC_LxDCCR_DCBLUE_Pos (0U)
#define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
#define LTDC_LxDCCR_DCGREEN_Pos (8U)
#define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
#define LTDC_LxDCCR_DCRED_Pos (16U)
#define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
#define LTDC_LxDCCR_DCALPHA_Pos (24U)
#define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
/******************** Bit definition for LTDC_LxBFCR register ***************/
#define LTDC_LxBFCR_BF2_Pos (0U)
#define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
#define LTDC_LxBFCR_BF1_Pos (8U)
#define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
/******************** Bit definition for LTDC_LxCFBAR register **************/
#define LTDC_LxCFBAR_CFBADD_Pos (0U)
#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
/******************** Bit definition for LTDC_LxCFBLR register **************/
#define LTDC_LxCFBLR_CFBLL_Pos (0U)
#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
#define LTDC_LxCFBLR_CFBP_Pos (16U)
#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
/******************** Bit definition for LTDC_LxCFBLNR register *************/
#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
/******************** Bit definition for LTDC_LxCLUTWR register *************/
#define LTDC_LxCLUTWR_BLUE_Pos (0U)
#define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
#define LTDC_LxCLUTWR_GREEN_Pos (8U)
#define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
#define LTDC_LxCLUTWR_RED_Pos (16U)
#define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
/******************************************************************************/
/* */
/* Power Control */
@ -12704,9 +12365,6 @@ typedef struct
#define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
#define RCC_APB2RSTR_LTDCRST_Pos (26U)
#define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
#define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
/******************** Bit definition for RCC_AHB1ENR register ***************/
#define RCC_AHB1ENR_DMA1EN_Pos (0U)
@ -12908,9 +12566,6 @@ typedef struct
#define RCC_APB2ENR_DFSDM1EN_Pos (24U)
#define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
#define RCC_APB2ENR_LTDCEN_Pos (26U)
#define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
#define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
/******************** Bit definition for RCC_AHB1SMENR register ***************/
#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
@ -13118,9 +12773,6 @@ typedef struct
#define RCC_APB2SMENR_DFSDM1SMEN_Pos (24U)
#define RCC_APB2SMENR_DFSDM1SMEN_Msk (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */
#define RCC_APB2SMENR_DFSDM1SMEN RCC_APB2SMENR_DFSDM1SMEN_Msk
#define RCC_APB2SMENR_LTDCSMEN_Pos (26U)
#define RCC_APB2SMENR_LTDCSMEN_Msk (0x1U << RCC_APB2SMENR_LTDCSMEN_Pos) /*!< 0x04000000 */
#define RCC_APB2SMENR_LTDCSMEN RCC_APB2SMENR_LTDCSMEN_Msk
/******************** Bit definition for RCC_CCIPR register ******************/
#define RCC_CCIPR_USART1SEL_Pos (0U)
@ -13372,9 +13024,6 @@ typedef struct
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk
#define RNG_CR_BYP_Pos (6U)
#define RNG_CR_BYP_Msk (0x1U << RNG_CR_BYP_Pos) /*!< 0x00000040 */
#define RNG_CR_BYP RNG_CR_BYP_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
@ -14728,12 +14377,12 @@ typedef struct
#define SDMMC_STA_DABORT_Pos (11U)
#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
#define SDMMC_STA_CPSMACT_Pos (12U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_DPSMACT_Pos (13U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_DPSMACT_Pos (12U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_CPSMACT_Pos (13U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_TXFIFOHE_Pos (14U)
#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
@ -14891,13 +14540,27 @@ typedef struct
#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE ((uint32_t)0x00200000) /*!<BUSYD0ENDIE interrupt Enable */
#define SDMMC_MASK_SDMMCITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE ((uint32_t)0x00800000) /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE ((uint32_t)0x01000000) /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE ((uint32_t)0x02000000) /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE ((uint32_t)0x04000000) /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE ((uint32_t)0x10000000) /*!<IDMA buffer transfer complete Interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0END interrupt Enable */
#define SDMMC_MASK_SDIOITIE_Pos (22U)
#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE_Pos (23U)
#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE_Pos (25U)
#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE_Pos (26U)
#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x03000000 */
#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE_Pos (28U)
#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
/***************** Bit definition for SDMMC_FIFOCNT register *****************/
#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
@ -19995,9 +19658,6 @@ typedef struct
/****************** I2C Instances : wakeup capability from stop modes *********/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
/****************************** LTDC Instances ********************************/
#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
/******************************* HCD Instances *******************************/
#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)

43
ext/hal/st/stm32cube/stm32l4xx/soc/stm32l4r7xx.h
View file

@ -13533,9 +13533,6 @@ typedef struct
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk
#define RNG_CR_BYP_Pos (6U)
#define RNG_CR_BYP_Msk (0x1U << RNG_CR_BYP_Pos) /*!< 0x00000040 */
#define RNG_CR_BYP RNG_CR_BYP_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
@ -14889,12 +14886,12 @@ typedef struct
#define SDMMC_STA_DABORT_Pos (11U)
#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
#define SDMMC_STA_CPSMACT_Pos (12U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_DPSMACT_Pos (13U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_DPSMACT_Pos (12U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_CPSMACT_Pos (13U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_TXFIFOHE_Pos (14U)
#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
@ -15052,13 +15049,27 @@ typedef struct
#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE ((uint32_t)0x00200000) /*!<BUSYD0ENDIE interrupt Enable */
#define SDMMC_MASK_SDMMCITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE ((uint32_t)0x00800000) /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE ((uint32_t)0x01000000) /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE ((uint32_t)0x02000000) /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE ((uint32_t)0x04000000) /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE ((uint32_t)0x10000000) /*!<IDMA buffer transfer complete Interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0END interrupt Enable */
#define SDMMC_MASK_SDIOITIE_Pos (22U)
#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE_Pos (23U)
#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE_Pos (25U)
#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE_Pos (26U)
#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x03000000 */
#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE_Pos (28U)
#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
/***************** Bit definition for SDMMC_FIFOCNT register *****************/
#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)

43
ext/hal/st/stm32cube/stm32l4xx/soc/stm32l4r9xx.h
View file

@ -16665,9 +16665,6 @@ typedef struct
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk
#define RNG_CR_BYP_Pos (6U)
#define RNG_CR_BYP_Msk (0x1U << RNG_CR_BYP_Pos) /*!< 0x00000040 */
#define RNG_CR_BYP RNG_CR_BYP_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
@ -18021,12 +18018,12 @@ typedef struct
#define SDMMC_STA_DABORT_Pos (11U)
#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
#define SDMMC_STA_CPSMACT_Pos (12U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_DPSMACT_Pos (13U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_DPSMACT_Pos (12U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_CPSMACT_Pos (13U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_TXFIFOHE_Pos (14U)
#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
@ -18184,13 +18181,27 @@ typedef struct
#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE ((uint32_t)0x00200000) /*!<BUSYD0ENDIE interrupt Enable */
#define SDMMC_MASK_SDMMCITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE ((uint32_t)0x00800000) /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE ((uint32_t)0x01000000) /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE ((uint32_t)0x02000000) /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE ((uint32_t)0x04000000) /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE ((uint32_t)0x10000000) /*!<IDMA buffer transfer complete Interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0END interrupt Enable */
#define SDMMC_MASK_SDIOITIE_Pos (22U)
#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE_Pos (23U)
#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE_Pos (25U)
#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE_Pos (26U)
#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x03000000 */
#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE_Pos (28U)
#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
/***************** Bit definition for SDMMC_FIFOCNT register *****************/
#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)

394
ext/hal/st/stm32cube/stm32l4xx/soc/stm32l4s5xx.h
View file

@ -177,8 +177,6 @@ typedef enum
I2C4_ER_IRQn = 84, /*!< I2C4 Error interrupt */
DCMI_IRQn = 85, /*!< DCMI global interrupt */
DMA2D_IRQn = 90, /*!< DMA2D global interrupt */
LTDC_IRQn = 91, /*!< LTDC global Interrupt */
LTDC_ER_IRQn = 92, /*!< LTDC Error global Interrupt */
DMAMUX1_OVR_IRQn = 94 /*!< DMAMUX1 overrun global interrupt */
} IRQn_Type;
@ -699,54 +697,6 @@ typedef struct
__IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
} LPTIM_TypeDef;
/**
* @brief LCD-TFT Display Controller
*/
typedef struct
{
uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
__IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
__IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
__IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
__IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
__IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
__IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
__IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
__IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
__IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
__IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
__IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
__IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
__IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
} LTDC_TypeDef;
/**
* @brief LCD-TFT Display layer x Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
__IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
__IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
__IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
__IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
__IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
__IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
__IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
uint32_t RESERVED0[2]; /*!< Reserved */
__IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
__IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
__IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
uint32_t RESERVED1[3]; /*!< Reserved */
__IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
} LTDC_Layer_TypeDef;
/**
* @brief Operational Amplifier (OPAMP)
*/
@ -1448,9 +1398,6 @@ typedef struct
#define SAI2_BASE (APB2PERIPH_BASE + 0x5800U)
#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
@ -1630,9 +1577,6 @@ typedef struct
#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
@ -10930,289 +10874,6 @@ typedef struct
#define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
/******************************************************************************/
/* */
/* LCD-TFT Display Controller (LTDC) */
/* */
/******************************************************************************/
/******************** Bit definition for LTDC_SSCR register *****************/
#define LTDC_SSCR_VSH_Pos (0U)
#define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
#define LTDC_SSCR_HSW_Pos (16U)
#define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
/******************** Bit definition for LTDC_BPCR register *****************/
#define LTDC_BPCR_AVBP_Pos (0U)
#define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
#define LTDC_BPCR_AHBP_Pos (16U)
#define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
/******************** Bit definition for LTDC_AWCR register *****************/
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
/******************** Bit definition for LTDC_TWCR register *****************/
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
/******************** Bit definition for LTDC_GCR register ******************/
#define LTDC_GCR_LTDCEN_Pos (0U)
#define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
#define LTDC_GCR_DBW_Pos (4U)
#define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
#define LTDC_GCR_DGW_Pos (8U)
#define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
#define LTDC_GCR_DRW_Pos (12U)
#define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
#define LTDC_GCR_DEN_Pos (16U)
#define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
#define LTDC_GCR_PCPOL_Pos (28U)
#define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
#define LTDC_GCR_DEPOL_Pos (29U)
#define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
#define LTDC_GCR_VSPOL_Pos (30U)
#define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
#define LTDC_GCR_HSPOL_Pos (31U)
#define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
/******************** Bit definition for LTDC_SRCR register *****************/
#define LTDC_SRCR_IMR_Pos (0U)
#define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
#define LTDC_SRCR_VBR_Pos (1U)
#define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
/******************** Bit definition for LTDC_BCCR register *****************/
#define LTDC_BCCR_BCBLUE_Pos (0U)
#define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
#define LTDC_BCCR_BCGREEN_Pos (8U)
#define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
#define LTDC_BCCR_BCRED_Pos (16U)
#define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
/******************** Bit definition for LTDC_IER register ******************/
#define LTDC_IER_LIE_Pos (0U)
#define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
#define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
#define LTDC_IER_FUIE_Pos (1U)
#define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
#define LTDC_IER_TERRIE_Pos (2U)
#define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
#define LTDC_IER_RRIE_Pos (3U)
#define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
/******************** Bit definition for LTDC_ISR register ******************/
#define LTDC_ISR_LIF_Pos (0U)
#define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
#define LTDC_ISR_FUIF_Pos (1U)
#define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
#define LTDC_ISR_TERRIF_Pos (2U)
#define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
#define LTDC_ISR_RRIF_Pos (3U)
#define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
/******************** Bit definition for LTDC_ICR register ******************/
#define LTDC_ICR_CLIF_Pos (0U)
#define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
#define LTDC_ICR_CFUIF_Pos (1U)
#define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
#define LTDC_ICR_CTERRIF_Pos (2U)
#define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
#define LTDC_ICR_CRRIF_Pos (3U)
#define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
/******************** Bit definition for LTDC_LIPCR register ****************/
#define LTDC_LIPCR_LIPOS_Pos (0U)
#define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
/******************** Bit definition for LTDC_CPSR register *****************/
#define LTDC_CPSR_CYPOS_Pos (0U)
#define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
#define LTDC_CPSR_CXPOS_Pos (16U)
#define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
/******************** Bit definition for LTDC_CDSR register *****************/
#define LTDC_CDSR_VDES_Pos (0U)
#define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
#define LTDC_CDSR_HDES_Pos (1U)
#define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
#define LTDC_CDSR_VSYNCS_Pos (2U)
#define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
#define LTDC_CDSR_HSYNCS_Pos (3U)
#define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
/******************** Bit definition for LTDC_LxCR register *****************/
#define LTDC_LxCR_LEN_Pos (0U)
#define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
#define LTDC_LxCR_COLKEN_Pos (1U)
#define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
#define LTDC_LxCR_CLUTEN_Pos (4U)
#define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
/******************** Bit definition for LTDC_LxWHPCR register **************/
#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0x0FFF0000 */
#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
/******************** Bit definition for LTDC_LxWVPCR register **************/
#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0x0FFF0000 */
#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
/******************** Bit definition for LTDC_LxCKCR register ***************/
#define LTDC_LxCKCR_CKBLUE_Pos (0U)
#define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
#define LTDC_LxCKCR_CKGREEN_Pos (8U)
#define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
#define LTDC_LxCKCR_CKRED_Pos (16U)
#define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
/******************** Bit definition for LTDC_LxPFCR register ***************/
#define LTDC_LxPFCR_PF_Pos (0U)
#define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
/******************** Bit definition for LTDC_LxCACR register ***************/
#define LTDC_LxCACR_CONSTA_Pos (0U)
#define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
/******************** Bit definition for LTDC_LxDCCR register ***************/
#define LTDC_LxDCCR_DCBLUE_Pos (0U)
#define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
#define LTDC_LxDCCR_DCGREEN_Pos (8U)
#define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
#define LTDC_LxDCCR_DCRED_Pos (16U)
#define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
#define LTDC_LxDCCR_DCALPHA_Pos (24U)
#define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
/******************** Bit definition for LTDC_LxBFCR register ***************/
#define LTDC_LxBFCR_BF2_Pos (0U)
#define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
#define LTDC_LxBFCR_BF1_Pos (8U)
#define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
/******************** Bit definition for LTDC_LxCFBAR register **************/
#define LTDC_LxCFBAR_CFBADD_Pos (0U)
#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
/******************** Bit definition for LTDC_LxCFBLR register **************/
#define LTDC_LxCFBLR_CFBLL_Pos (0U)
#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
#define LTDC_LxCFBLR_CFBP_Pos (16U)
#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
/******************** Bit definition for LTDC_LxCFBLNR register *************/
#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
/******************** Bit definition for LTDC_LxCLUTWR register *************/
#define LTDC_LxCLUTWR_BLUE_Pos (0U)
#define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
#define LTDC_LxCLUTWR_GREEN_Pos (8U)
#define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
#define LTDC_LxCLUTWR_RED_Pos (16U)
#define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
/******************************************************************************/
/* */
/* Power Control */
@ -13039,9 +12700,6 @@ typedef struct
#define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
#define RCC_APB2RSTR_LTDCRST_Pos (26U)
#define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
#define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
/******************** Bit definition for RCC_AHB1ENR register ***************/
#define RCC_AHB1ENR_DMA1EN_Pos (0U)
@ -13249,9 +12907,6 @@ typedef struct
#define RCC_APB2ENR_DFSDM1EN_Pos (24U)
#define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
#define RCC_APB2ENR_LTDCEN_Pos (26U)
#define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
#define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
/******************** Bit definition for RCC_AHB1SMENR register ***************/
#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
@ -13465,9 +13120,6 @@ typedef struct
#define RCC_APB2SMENR_DFSDM1SMEN_Pos (24U)
#define RCC_APB2SMENR_DFSDM1SMEN_Msk (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */
#define RCC_APB2SMENR_DFSDM1SMEN RCC_APB2SMENR_DFSDM1SMEN_Msk
#define RCC_APB2SMENR_LTDCSMEN_Pos (26U)
#define RCC_APB2SMENR_LTDCSMEN_Msk (0x1U << RCC_APB2SMENR_LTDCSMEN_Pos) /*!< 0x04000000 */
#define RCC_APB2SMENR_LTDCSMEN RCC_APB2SMENR_LTDCSMEN_Msk
/******************** Bit definition for RCC_CCIPR register ******************/
#define RCC_CCIPR_USART1SEL_Pos (0U)
@ -13719,9 +13371,6 @@ typedef struct
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk
#define RNG_CR_BYP_Pos (6U)
#define RNG_CR_BYP_Msk (0x1U << RNG_CR_BYP_Pos) /*!< 0x00000040 */
#define RNG_CR_BYP RNG_CR_BYP_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
@ -15075,12 +14724,12 @@ typedef struct
#define SDMMC_STA_DABORT_Pos (11U)
#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
#define SDMMC_STA_CPSMACT_Pos (12U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_DPSMACT_Pos (13U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_DPSMACT_Pos (12U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_CPSMACT_Pos (13U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_TXFIFOHE_Pos (14U)
#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
@ -15238,13 +14887,27 @@ typedef struct
#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE ((uint32_t)0x00200000) /*!<BUSYD0ENDIE interrupt Enable */
#define SDMMC_MASK_SDMMCITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE ((uint32_t)0x00800000) /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE ((uint32_t)0x01000000) /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE ((uint32_t)0x02000000) /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE ((uint32_t)0x04000000) /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE ((uint32_t)0x10000000) /*!<IDMA buffer transfer complete Interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0END interrupt Enable */
#define SDMMC_MASK_SDIOITIE_Pos (22U)
#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE_Pos (23U)
#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE_Pos (25U)
#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE_Pos (26U)
#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x03000000 */
#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE_Pos (28U)
#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
/***************** Bit definition for SDMMC_FIFOCNT register *****************/
#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
@ -20345,9 +20008,6 @@ typedef struct
/****************** I2C Instances : wakeup capability from stop modes *********/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
/****************************** LTDC Instances ********************************/
#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
/******************************* HCD Instances *******************************/
#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)

43
ext/hal/st/stm32cube/stm32l4xx/soc/stm32l4s7xx.h
View file

@ -13880,9 +13880,6 @@ typedef struct
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk
#define RNG_CR_BYP_Pos (6U)
#define RNG_CR_BYP_Msk (0x1U << RNG_CR_BYP_Pos) /*!< 0x00000040 */
#define RNG_CR_BYP RNG_CR_BYP_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
@ -15236,12 +15233,12 @@ typedef struct
#define SDMMC_STA_DABORT_Pos (11U)
#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
#define SDMMC_STA_CPSMACT_Pos (12U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_DPSMACT_Pos (13U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_DPSMACT_Pos (12U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_CPSMACT_Pos (13U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_TXFIFOHE_Pos (14U)
#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
@ -15399,13 +15396,27 @@ typedef struct
#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE ((uint32_t)0x00200000) /*!<BUSYD0ENDIE interrupt Enable */
#define SDMMC_MASK_SDMMCITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE ((uint32_t)0x00800000) /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE ((uint32_t)0x01000000) /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE ((uint32_t)0x02000000) /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE ((uint32_t)0x04000000) /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE ((uint32_t)0x10000000) /*!<IDMA buffer transfer complete Interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0END interrupt Enable */
#define SDMMC_MASK_SDIOITIE_Pos (22U)
#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE_Pos (23U)
#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE_Pos (25U)
#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE_Pos (26U)
#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x03000000 */
#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE_Pos (28U)
#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
/***************** Bit definition for SDMMC_FIFOCNT register *****************/
#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)

43
ext/hal/st/stm32cube/stm32l4xx/soc/stm32l4s9xx.h
View file

@ -17012,9 +17012,6 @@ typedef struct
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk
#define RNG_CR_BYP_Pos (6U)
#define RNG_CR_BYP_Msk (0x1U << RNG_CR_BYP_Pos) /*!< 0x00000040 */
#define RNG_CR_BYP RNG_CR_BYP_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
@ -18368,12 +18365,12 @@ typedef struct
#define SDMMC_STA_DABORT_Pos (11U)
#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
#define SDMMC_STA_CPSMACT_Pos (12U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_DPSMACT_Pos (13U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_DPSMACT_Pos (12U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_CPSMACT_Pos (13U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_TXFIFOHE_Pos (14U)
#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
@ -18531,13 +18528,27 @@ typedef struct
#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE ((uint32_t)0x00200000) /*!<BUSYD0ENDIE interrupt Enable */
#define SDMMC_MASK_SDMMCITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE ((uint32_t)0x00800000) /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE ((uint32_t)0x01000000) /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE ((uint32_t)0x02000000) /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE ((uint32_t)0x04000000) /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE ((uint32_t)0x10000000) /*!<IDMA buffer transfer complete Interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0END interrupt Enable */
#define SDMMC_MASK_SDIOITIE_Pos (22U)
#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE_Pos (23U)
#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE_Pos (25U)
#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE_Pos (26U)
#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x03000000 */
#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE_Pos (28U)
#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
/***************** Bit definition for SDMMC_FIFOCNT register *****************/
#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)

4
ext/hal/st/stm32cube/stm32l4xx/soc/stm32l4xx.h
View file

@ -114,11 +114,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number $VERSION$
* @brief CMSIS Device version number
*/
#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
|(__STM32L4_CMSIS_VERSION_SUB1 << 16)\