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driver: clock control stm32: align f4 factor names on l4

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This commits align CONFIG_ factor names between stm32f4 and stm32l4
series to enable code factorization such as use of Q_DIVISOR.
Though, it does not concatenate kconfig sections as we might use
a bit of time to see what is needed in this regard

Change-Id: Ia603406d53949abf5675b801a5448397d5ab8462
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2017-04-19 08:00:22 +02:00 • committed by Kumar Gala
commit 288a9c145d
6 changed files with 22 additions and 22 deletions
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8
boards/arm/96b_carbon/96b_carbon_defconfig
View file

@ -31,10 +31,10 @@ CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
# CONFIG_CLOCK_STM32_HSE_BYPASS=y
# produce 84MHz clock at PLL output
CONFIG_CLOCK_STM32_PLLM_DIV_FACTOR=16
CONFIG_CLOCK_STM32_PLLN_MULTIPLIER=336
CONFIG_CLOCK_STM32_PLLP_DIV_FACTOR=4
CONFIG_CLOCK_STM32_PLLQ_DIV_FACTOR=7
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=16
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=336
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=7
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=1

8
boards/arm/nucleo_f401re/nucleo_f401re_defconfig
View file

@ -32,10 +32,10 @@ CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
# the 8MHz clock signal coming from integrated STLink
CONFIG_CLOCK_STM32_HSE_BYPASS=y
# produce 84MHz clock at PLL output
CONFIG_CLOCK_STM32_PLLM_DIV_FACTOR=8
CONFIG_CLOCK_STM32_PLLN_MULTIPLIER=336
CONFIG_CLOCK_STM32_PLLP_DIV_FACTOR=4
CONFIG_CLOCK_STM32_PLLQ_DIV_FACTOR=7
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=8
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=336
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=7
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=1

8
boards/arm/nucleo_f411re/nucleo_f411re_defconfig
View file

@ -32,10 +32,10 @@ CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
# the 8MHz clock signal coming from integrated STLink
CONFIG_CLOCK_STM32_HSE_BYPASS=y
# produce 84MHz clock at PLL output
CONFIG_CLOCK_STM32_PLLM_DIV_FACTOR=8
CONFIG_CLOCK_STM32_PLLN_MULTIPLIER=384
CONFIG_CLOCK_STM32_PLLP_DIV_FACTOR=4
CONFIG_CLOCK_STM32_PLLQ_DIV_FACTOR=8
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=8
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=384
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=8
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=1

8
drivers/clock_control/Kconfig.stm32
View file

@ -112,7 +112,7 @@ endif # SOC_SERIES_STM32F3X
if SOC_SERIES_STM32F4X
config CLOCK_STM32_PLLM_DIV_FACTOR
config CLOCK_STM32_PLL_M_DIVISOR
int "Division factor for PLL VCO input clock"
depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
default 8
@ -123,7 +123,7 @@ config CLOCK_STM32_PLLM_DIV_FACTOR
frequency of 2 MHz to limit PLL jitter.
Allowed values: 2-63
config CLOCK_STM32_PLLN_MULTIPLIER
config CLOCK_STM32_PLL_N_MULTIPLIER
int "Multiplier factor for PLL VCO output clock"
depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
default 336
@ -135,7 +135,7 @@ config CLOCK_STM32_PLLN_MULTIPLIER
where the frequency must be between 192 and 432 MHz.
Allowed values: 50-432 (STM32F401: 192-432)
config CLOCK_STM32_PLLP_DIV_FACTOR
config CLOCK_STM32_PLL_P_DIVISOR
int "PLL division factor for main system clock"
depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
default 4
@ -144,7 +144,7 @@ config CLOCK_STM32_PLLP_DIV_FACTOR
PLLP division factor needs to be set correctly to not exceed 84MHz.
Allowed values: 2, 4, 6, 8
config CLOCK_STM32_PLLQ_DIV_FACTOR
config CLOCK_STM32_PLL_Q_DIVISOR
int "Division factor for OTG FS, SDIO and RNG clocks"
depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
default 7

6
drivers/clock_control/stm32_ll_clock.c
View file

@ -171,11 +171,11 @@ static int stm32_clock_control_init(struct device *dev)
/* Disable PLL before configuration */
LL_RCC_PLL_Disable();
#ifdef CONFIG_CLOCK_STM32_PLLQ_DIV_FACTOR
#ifdef CONFIG_CLOCK_STM32_PLL_Q_DIVISOR
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ,
CONFIG_CLOCK_STM32_PLLQ_DIV_FACTOR
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR
<< POSITION_VAL(RCC_PLLCFGR_PLLQ));
#endif /* CONFIG_CLOCK_STM32_PLLQ_DIV_FACTOR */
#endif /* CONFIG_CLOCK_STM32_PLL_Q_DIVISOR */
#ifdef CONFIG_CLOCK_STM32_PLL_SRC_MSI
/* Switch to PLL with MSI as clock source */

6
drivers/clock_control/stm32f4x_ll_clock.c
View file

@ -28,9 +28,9 @@
*/
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
{
pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLLM_DIV_FACTOR);
pllinit->PLLN = CONFIG_CLOCK_STM32_PLLN_MULTIPLIER;
pllinit->PLLP = pllp(CONFIG_CLOCK_STM32_PLLP_DIV_FACTOR);
pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);
pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER;
pllinit->PLLP = pllp(CONFIG_CLOCK_STM32_PLL_P_DIVISOR);
}
#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */