driver: clock control stm32: align f4 factor names on l4
This commits align CONFIG_ factor names between stm32f4 and stm32l4 series to enable code factorization such as use of Q_DIVISOR. Though, it does not concatenate kconfig sections as we might use a bit of time to see what is needed in this regard Change-Id: Ia603406d53949abf5675b801a5448397d5ab8462 Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
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6 changed files with 22 additions and 22 deletions
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@ -31,10 +31,10 @@ CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
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# CONFIG_CLOCK_STM32_HSE_BYPASS=y
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# produce 84MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLLM_DIV_FACTOR=16
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CONFIG_CLOCK_STM32_PLLN_MULTIPLIER=336
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CONFIG_CLOCK_STM32_PLLP_DIV_FACTOR=4
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CONFIG_CLOCK_STM32_PLLQ_DIV_FACTOR=7
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CONFIG_CLOCK_STM32_PLL_M_DIVISOR=16
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CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=336
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CONFIG_CLOCK_STM32_PLL_P_DIVISOR=4
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CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=7
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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CONFIG_CLOCK_STM32_APB1_PRESCALER=2
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CONFIG_CLOCK_STM32_APB2_PRESCALER=1
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@ -32,10 +32,10 @@ CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
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# the 8MHz clock signal coming from integrated STLink
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CONFIG_CLOCK_STM32_HSE_BYPASS=y
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# produce 84MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLLM_DIV_FACTOR=8
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CONFIG_CLOCK_STM32_PLLN_MULTIPLIER=336
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CONFIG_CLOCK_STM32_PLLP_DIV_FACTOR=4
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CONFIG_CLOCK_STM32_PLLQ_DIV_FACTOR=7
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CONFIG_CLOCK_STM32_PLL_M_DIVISOR=8
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CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=336
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CONFIG_CLOCK_STM32_PLL_P_DIVISOR=4
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CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=7
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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CONFIG_CLOCK_STM32_APB1_PRESCALER=2
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CONFIG_CLOCK_STM32_APB2_PRESCALER=1
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@ -32,10 +32,10 @@ CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
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# the 8MHz clock signal coming from integrated STLink
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CONFIG_CLOCK_STM32_HSE_BYPASS=y
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# produce 84MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLLM_DIV_FACTOR=8
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CONFIG_CLOCK_STM32_PLLN_MULTIPLIER=384
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CONFIG_CLOCK_STM32_PLLP_DIV_FACTOR=4
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CONFIG_CLOCK_STM32_PLLQ_DIV_FACTOR=8
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CONFIG_CLOCK_STM32_PLL_M_DIVISOR=8
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CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=384
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CONFIG_CLOCK_STM32_PLL_P_DIVISOR=4
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CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=8
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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CONFIG_CLOCK_STM32_APB1_PRESCALER=2
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CONFIG_CLOCK_STM32_APB2_PRESCALER=1
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@ -112,7 +112,7 @@ endif # SOC_SERIES_STM32F3X
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if SOC_SERIES_STM32F4X
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config CLOCK_STM32_PLLM_DIV_FACTOR
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config CLOCK_STM32_PLL_M_DIVISOR
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int "Division factor for PLL VCO input clock"
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depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
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default 8
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@ -123,7 +123,7 @@ config CLOCK_STM32_PLLM_DIV_FACTOR
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frequency of 2 MHz to limit PLL jitter.
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Allowed values: 2-63
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config CLOCK_STM32_PLLN_MULTIPLIER
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config CLOCK_STM32_PLL_N_MULTIPLIER
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int "Multiplier factor for PLL VCO output clock"
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depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
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default 336
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@ -135,7 +135,7 @@ config CLOCK_STM32_PLLN_MULTIPLIER
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where the frequency must be between 192 and 432 MHz.
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Allowed values: 50-432 (STM32F401: 192-432)
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config CLOCK_STM32_PLLP_DIV_FACTOR
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config CLOCK_STM32_PLL_P_DIVISOR
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int "PLL division factor for main system clock"
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depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
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default 4
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@ -144,7 +144,7 @@ config CLOCK_STM32_PLLP_DIV_FACTOR
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PLLP division factor needs to be set correctly to not exceed 84MHz.
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Allowed values: 2, 4, 6, 8
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config CLOCK_STM32_PLLQ_DIV_FACTOR
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config CLOCK_STM32_PLL_Q_DIVISOR
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int "Division factor for OTG FS, SDIO and RNG clocks"
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depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
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default 7
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@ -171,11 +171,11 @@ static int stm32_clock_control_init(struct device *dev)
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/* Disable PLL before configuration */
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LL_RCC_PLL_Disable();
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#ifdef CONFIG_CLOCK_STM32_PLLQ_DIV_FACTOR
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#ifdef CONFIG_CLOCK_STM32_PLL_Q_DIVISOR
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ,
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CONFIG_CLOCK_STM32_PLLQ_DIV_FACTOR
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CONFIG_CLOCK_STM32_PLL_Q_DIVISOR
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<< POSITION_VAL(RCC_PLLCFGR_PLLQ));
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#endif /* CONFIG_CLOCK_STM32_PLLQ_DIV_FACTOR */
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#endif /* CONFIG_CLOCK_STM32_PLL_Q_DIVISOR */
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#ifdef CONFIG_CLOCK_STM32_PLL_SRC_MSI
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/* Switch to PLL with MSI as clock source */
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@ -28,9 +28,9 @@
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*/
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void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
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{
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pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLLM_DIV_FACTOR);
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pllinit->PLLN = CONFIG_CLOCK_STM32_PLLN_MULTIPLIER;
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pllinit->PLLP = pllp(CONFIG_CLOCK_STM32_PLLP_DIV_FACTOR);
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pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);
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pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER;
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pllinit->PLLP = pllp(CONFIG_CLOCK_STM32_PLL_P_DIVISOR);
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}
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#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
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