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drivers: pwm: bbled: Update bbled-pwm dts files

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Updated Overlay, dtsi and yaml files.

Signed-off-by: Manimaran A <manimaran.a@microchip.com>
This commit is contained in:
Manimaran A 2023-09-27 10:58:24 +05:30 • committed by Carles Cufí
commit 28475a3496
5 changed files with 221 additions and 4 deletions
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7
dts/bindings/pwm/microchip,xec-pwmbbled.yaml
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@ -30,11 +30,9 @@ properties:
description: |
Clock source selection: 32 KHz is available in deep sleep.
- PWM_BBLED_CLK_AHB: Clock source is the PLL based AHB clock
- PWM_BBLED_CLK_SLOW: Clock source is the PLL based PCR slow clock
- PWM_BBLED_CLK_32K: Clock source is the 32KHz domain
enum:
- "PWM_BBLED_CLK_32K"
- "PWM_BBLED_CLK_SLOW"
- "PWM_BBLED_CLK_48M"
pinctrl-0:
@ -44,7 +42,7 @@ properties:
required: true
"#pwm-cells":
const: 2
const: 3
enable-low-power-32k:
type: boolean
@ -55,9 +53,10 @@ properties:
When BBLED enter into Suspend state, 48MHz clock will be switched off by
PCR(Power, Clock and Reset) block. But 32KHz Core clock will be available to BBLED.
There may be a product requirement, either to blink (or) not blink LED in Suspend state.
Flag "enable-low-power-32k" shall be used along with 32KHz clock to blink (or) not blink
Property "enable-low-power-32k" shall be used along with 32KHz clock to blink (or) not blink
the LED in Suspend state.
pwm-cells:
- channel
- period
- flags