arch/stm32: remove irq definition files
Since they are not used anymore because can be replaced by CMSIS definition or generated from device tree, remove IRQ definition file soc_irq.h Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou
Kumar Gala
parent
d84795b0c1
commit
2800729614
12 changed files with 0 additions and 569 deletions
|
|
@ -30,8 +30,6 @@
|
|||
|
||||
#include <stm32f0xx.h>
|
||||
|
||||
#include "soc_irq.h"
|
||||
|
||||
#ifdef CONFIG_SERIAL_HAS_DRIVER
|
||||
#include <stm32f0xx_ll_usart.h>
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,59 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2017 RnDity Sp. z o.o.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file Interrupt numbers for STM32F0 family processors.
|
||||
*
|
||||
* Based on reference manual:
|
||||
* STM32F030x4/x6/x8/xC,
|
||||
* STM32F070x6/xB advanced ARM ® -based MCUs
|
||||
*
|
||||
* Chapter 11.1.3: Interrupt and exception vectors
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _STM32F0_SOC_IRQ_H_
|
||||
#define _STM32F0_SOC_IRQ_H_
|
||||
|
||||
/* FIXME: Remove when use of enum line number in IRQ_CONNECT is
|
||||
* made possible by GH-2657.
|
||||
* soc_irq.h, once it is possible, should be removed.
|
||||
*/
|
||||
|
||||
#define STM32F0_IRQ_WWDG 0
|
||||
/* reserved */
|
||||
#define STM32F0_IRQ_RTC 2
|
||||
#define STM32F0_IRQ_FLASH 3
|
||||
#define STM32F0_IRQ_RCC 4
|
||||
#define STM32F0_IRQ_EXTI0_1 5
|
||||
#define STM32F0_IRQ_EXTI2_3 6
|
||||
#define STM32F0_IRQ_EXTI4_15 7
|
||||
/* reserved */
|
||||
#define STM32F0_IRQ_DMA_CH1 9
|
||||
#define STM32F0_IRQ_DMA_CH2_3 10
|
||||
#define STM32F0_IRQ_DMA_CH4_5 11
|
||||
#define STM32F0_IRQ_ADC 12
|
||||
#define STM32F0_IRQ_TIM1_BRK_UP_TRG_COM 13
|
||||
#define STM32F0_IRQ_TIM1_CC 14
|
||||
/* reserved */
|
||||
#define STM32F0_IRQ_TIM3 16
|
||||
#define STM32F0_IRQ_TIM6 17
|
||||
/* reserved */
|
||||
#define STM32F0_IRQ_TIM14 19
|
||||
#define STM32F0_IRQ_TIM15 20
|
||||
#define STM32F0_IRQ_TIM16 21
|
||||
#define STM32F0_IRQ_TIM17 22
|
||||
#define STM32F0_IRQ_I2C1 23
|
||||
#define STM32F0_IRQ_I2C2 24
|
||||
#define STM32F0_IRQ_SPI1 25
|
||||
#define STM32F0_IRQ_SPI2 26
|
||||
#define STM32F0_IRQ_USART1 27
|
||||
#define STM32F0_IRQ_USART2 28
|
||||
#define STM32F0_IRQ_USART3_4_5_6 29
|
||||
/* reserved */
|
||||
#define STM32F0_IRQ_USB 31
|
||||
|
||||
#endif /* _STM32F0_SOC_IRQ_H_ */
|
||||
|
|
@ -30,9 +30,6 @@
|
|||
|
||||
#include <stm32f1xx.h>
|
||||
|
||||
|
||||
#include "soc_irq.h"
|
||||
|
||||
#ifdef CONFIG_SERIAL_HAS_DRIVER
|
||||
#include <stm32f1xx_ll_usart.h>
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,95 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Open-RnD Sp. z o.o.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file Interrupt numbers for STM32F1 family processors.
|
||||
*
|
||||
* Based on reference manual:
|
||||
* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
|
||||
* advanced ARM(r)-based 32-bit MCUs
|
||||
*
|
||||
* Chapter 10.1.2: Interrupt and exception vectors
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _STM32F1_SOC_IRQ_H_
|
||||
#define _STM32F1_SOC_IRQ_H_
|
||||
|
||||
#define STM32F1_IRQ_WWDG 0
|
||||
#define STM32F1_IRQ_PVD 1
|
||||
#define STM32F1_IRQ_TAMPER 2
|
||||
#define STM32F1_IRQ_RTC 3
|
||||
#define STM32F1_IRQ_FLAGS 4
|
||||
#define STM32F1_IRQ_RCC 5
|
||||
#define STM32F1_IRQ_EXTI0 6
|
||||
#define STM32F1_IRQ_EXTI1 7
|
||||
#define STM32F1_IRQ_EXTI2 8
|
||||
#define STM32F1_IRQ_EXTI3 9
|
||||
#define STM32F1_IRQ_EXTI4 10
|
||||
#define STM32F1_IRQ_DMA1_CH1 11
|
||||
#define STM32F1_IRQ_DMA1_CH2 12
|
||||
#define STM32F1_IRQ_DMA1_CH3 13
|
||||
#define STM32F1_IRQ_DMA1_CH4 14
|
||||
#define STM32F1_IRQ_DMA1_CH5 15
|
||||
#define STM32F1_IRQ_DMA1_CH6 16
|
||||
#define STM32F1_IRQ_DMA1_CH7 17
|
||||
#define STM32F1_IRQ_ADC1_2 18
|
||||
#define STM32F1_IRQ_USB_HP_CAN_TX 19
|
||||
#define STM32F1_IRQ_USB_LP_CAN_RX0 20
|
||||
#define STM32F1_IRQ_CAN_RX1 21
|
||||
#define STM32F1_IRQ_CAN_SCE 22
|
||||
#define STM32F1_IRQ_EXTI9_5 23
|
||||
#define STM32F1_IRQ_TIM1_BRK 24
|
||||
#define STM32F1_IRQ_TIM1_UP 25
|
||||
#define STM32F1_IRQ_TIM1_TRG_COM 26
|
||||
#define STM32F1_IRQ_TIM1_CC 27
|
||||
#define STM32F1_IRQ_TIM2 28
|
||||
#define STM32F1_IRQ_TIM3 29
|
||||
#define STM32F1_IRQ_TIM4 30
|
||||
#define STM32F1_IRQ_I2C1_EV 31
|
||||
#define STM32F1_IRQ_I2C1_ER 32
|
||||
#define STM32F1_IRQ_I2C2_EV 33
|
||||
#define STM32F1_IRQ_I2C2_ER 34
|
||||
#define STM32F1_IRQ_SPI1 35
|
||||
#define STM32F1_IRQ_SPI2 36
|
||||
#define STM32F1_IRQ_USART1 37
|
||||
#define STM32F1_IRQ_USART2 38
|
||||
#define STM32F1_IRQ_USART3 39
|
||||
#define STM32F1_IRQ_EXTI15_10 40
|
||||
#define STM32F1_IRQ_RTC_ALARM 41
|
||||
#define STM32F1_IRQ_USB_WAKEUP 42
|
||||
#define STM32F1_IRQ_OTG_FS_WKUP STM32F1_IRQ_USB_WAKEUP
|
||||
#define STM32F1_IRQ_TIM8_BRK 43
|
||||
#define STM32F1_IRQ_TIM8_UP 44
|
||||
#define STM32F1_IRQ_TIM8_TRG_COM 45
|
||||
#define STM32F1_IRQ_TIM8_CC 46
|
||||
#define STM32F1_IRQ_ADC3 47
|
||||
#define STM32F1_IRQ_FSMC 48
|
||||
#define STM32F1_IRQ_SDIO 49
|
||||
#define STM32F1_IRQ_TIM5 50
|
||||
#define STM32F1_IRQ_SPI3 51
|
||||
#define STM32F1_IRQ_UART4 52
|
||||
#define STM32F1_IRQ_UART5 53
|
||||
#define STM32F1_IRQ_TIM6 54
|
||||
#define STM32F1_IRQ_TIM7 55
|
||||
#define STM32F1_IRQ_DMA2_CH1 56
|
||||
#define STM32F1_IRQ_DMA2_CH2 57
|
||||
#define STM32F1_IRQ_DMA2_CH3 58
|
||||
#define STM32F1_IRQ_DMA2_CH4_5 59
|
||||
/* IRQs below this point are available on connectivity line
|
||||
* devices only
|
||||
*/
|
||||
#define STM32F1_IRQ_DMA2_CH4 STM32F1_IRQ_DMA2_CH4_5
|
||||
#define STM32F1_IRQ_DMA2_CH5 60
|
||||
#define STM32F1_IRQ_ETH 61
|
||||
#define STM32F1_IRQ_ETH_WKUP 62
|
||||
#define STM32F1_IRQ_CAN2_TX 63
|
||||
#define STM32F1_IRQ_CAN2_RX0 64
|
||||
#define STM32F1_IRQ_CAN2_RX1 65
|
||||
#define STM32F1_IRQ_CAN2_SCE 66
|
||||
#define STM32F1_IRQ_OTG_FS 67
|
||||
|
||||
#endif /* _STM32F1_SOC_IRQ_H_ */
|
||||
|
|
@ -31,8 +31,6 @@
|
|||
|
||||
#include <stm32f3xx.h>
|
||||
|
||||
#include "soc_irq.h"
|
||||
|
||||
#ifdef CONFIG_SERIAL_HAS_DRIVER
|
||||
#include <stm32f3xx_ll_usart.h>
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,118 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2016 RnDity Sp. z o.o.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file Interrupt numbers for STM32F3 family processors.
|
||||
*
|
||||
* Based on reference manual:
|
||||
* STM32F303xB/C/D/E, STM32F303x6/8, STM32F328x8, STM32F358xC,
|
||||
* STM32F398xE advanced ARM(r)-based MCUs
|
||||
*
|
||||
* Chapter 14.1.3: Interrupt and exception vectors
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _STM32F3_SOC_IRQ_H_
|
||||
#define _STM32F3_SOC_IRQ_H_
|
||||
|
||||
/* FIXME: Remove when use of enum line number in IRQ_CONNECT is
|
||||
* made possible by GH-2657.
|
||||
* soc_irq.h, once it is possible, should be removed. */
|
||||
|
||||
#define STM32F3_IRQ_WWDG 0
|
||||
#define STM32F3_IRQ_PVD 1
|
||||
#define STM32F3_IRQ_TAMPER 2
|
||||
#define STM32F3_IRQ_RTC 3
|
||||
#define STM32F3_IRQ_FLASH 4
|
||||
#define STM32F3_IRQ_RCC 5
|
||||
#define STM32F3_IRQ_EXTI0 6
|
||||
#define STM32F3_IRQ_EXTI1 7
|
||||
#define STM32F3_IRQ_EXTI2_TS 8
|
||||
#define STM32F3_IRQ_EXTI3 9
|
||||
#define STM32F3_IRQ_EXTI4 10
|
||||
#define STM32F3_IRQ_DMA1_CH1 11
|
||||
#define STM32F3_IRQ_DMA1_CH2 12
|
||||
#define STM32F3_IRQ_DMA1_CH3 13
|
||||
#define STM32F3_IRQ_DMA1_CH4 14
|
||||
#define STM32F3_IRQ_DMA1_CH5 15
|
||||
#define STM32F3_IRQ_DMA1_CH6 16
|
||||
#define STM32F3_IRQ_DMA1_CH7 17
|
||||
#define STM32F3_IRQ_ADC1_2 18
|
||||
#define STM32F3_IRQ_USB_HP_CAN_TX 19
|
||||
#define STM32F3_IRQ_USB_LP_CAN_RX0 20
|
||||
#define STM32F3_IRQ_CAN_RX1 21
|
||||
#define STM32F3_IRQ_CAN_SCE 22
|
||||
#define STM32F3_IRQ_EXTI9_5 23
|
||||
#define STM32F3_IRQ_TIM15 24
|
||||
#define STM32F3_IRQ_TIM1_BRK STM32F3_IRQ_TIM15
|
||||
#define STM32F3_IRQ_TIM16 25
|
||||
#define STM32F3_IRQ_TIM1_UP STM32F3_IRQ_TIM16
|
||||
#define STM32F3_IRQ_TIM17 26
|
||||
#define STM32F3_IRQ_TIM1_TRG_COM STM32F3_IRQ_TIM17
|
||||
#define STM32F3_IRQ_TIM18 27
|
||||
#define STM32F3_IRQ_DAC2_URR STM32F3_IRQ_TIM18
|
||||
#define STM32F3_IRQ_TIM2 28
|
||||
#define STM32F3_IRQ_TIM3 29
|
||||
#define STM32F3_IRQ_TIM4 30
|
||||
#define STM32F3_IRQ_I2C1_EV 31
|
||||
#define STM32F3_IRQ_I2C1_ER 32
|
||||
#define STM32F3_IRQ_I2C2_EV 33
|
||||
#define STM32F3_IRQ_I2C2_ER 34
|
||||
#define STM32F3_IRQ_SPI1 35
|
||||
#define STM32F3_IRQ_SPI2 36
|
||||
#define STM32F3_IRQ_USART1 37
|
||||
#define STM32F3_IRQ_USART2 38
|
||||
#define STM32F3_IRQ_USART3 39
|
||||
#define STM32F3_IRQ_EXTI15_10 40
|
||||
#define STM32F3_IRQ_RTC_ALARM 41
|
||||
#define STM32F3_IRQ_USB_WAKEUP 42
|
||||
#define STM32F3_IRQ_TIM12 43
|
||||
#define STM32F3_IRQ_TIM8_BRK STM32F3_IRQ_TIM12
|
||||
#define STM32F3_IRQ_TIM13 44
|
||||
#define STM32F3_IRQ_TIM8_UP STM32F3_IRQ_TIM13
|
||||
#define STM32F3_IRQ_TIM14 45
|
||||
#define STM32F3_IRQ_TIM8_TRG_COM STM32F3_IRQ_TIM14
|
||||
#define STM32F3_IRQ_TIM8_CC 46
|
||||
#define STM32F3_IRQ_ADC3 47
|
||||
#define STM32F3_IRQ_FMC 48
|
||||
/* reserved */
|
||||
/* reserved */
|
||||
#define STM32F3_IRQ_TIM5 50
|
||||
#define STM32F3_IRQ_SPI3 51
|
||||
#define STM32F3_IRQ_UART4 52
|
||||
#define STM32F3_IRQ_UART5 53
|
||||
#define STM32F3_IRQ_TIM6 54
|
||||
#define STM32F3_IRQ_DAC1_URR STM32F3_IRQ_TIM6
|
||||
#define STM32F3_IRQ_TIM7 55
|
||||
#define STM32F3_IRQ_DMA2_CH1 56
|
||||
#define STM32F3_IRQ_DMA2_CH2 57
|
||||
#define STM32F3_IRQ_DMA2_CH3 58
|
||||
#define STM32F3_IRQ_DMA2_CH4 59
|
||||
#define STM32F3_IRQ_DMA2_CH5 60
|
||||
#define STM32F3_IRQ_ADC4 61
|
||||
/* reserved */
|
||||
/* reserved */
|
||||
#define STM32F3_IRQ_COMP_1_2_3 64
|
||||
#define STM32F3_IRQ_COMP_2 STM32F3_IRQ_COMP_1_2_3
|
||||
#define STM32F3_IRQ_COMP_1_2 STM32F3_IRQ_COMP_1_2_3
|
||||
#define STM32F3_IRQ_COMP_4_5_6 65
|
||||
#define STM32F3_IRQ_COMP_4_6 STM32F3_IRQ_COMP_4_5_6
|
||||
#define STM32F3_IRQ_COMP_7 66
|
||||
#define STM32F3_IRQ_OTG_FS 67
|
||||
#define STM32F3_IRQ_I2C3_EV 72
|
||||
#define STM32F3_IRQ_I2C3_EV_EXTI27 STM32F3_IRQ_I2C3_EV
|
||||
#define STM32F3_IRQ_I2C3_ER 73
|
||||
#define STM32F3_IRQ_USB_HP 74
|
||||
#define STM32F3_IRQ_USB_LP 75
|
||||
#define STM32F3_IRQ_USB_WAKEUP_RMP 76
|
||||
#define STM32F3_IRQ_TIM20_BRK 77
|
||||
#define STM32F3_IRQ_TIM19 78
|
||||
#define STM32F3_IRQ_TIM20_UP STM32F3_IRQ_TIM19
|
||||
#define STM32F3_IRQ_TIM20_TRG_COM 79
|
||||
#define STM32F3_IRQ_TIM20_CC 80
|
||||
#define STM32F3_IRQ_FPU 81
|
||||
|
||||
#endif /* _STM32F3_SOC_IRQ_H_ */
|
||||
|
|
@ -30,8 +30,6 @@
|
|||
|
||||
#include <stm32f4xx.h>
|
||||
|
||||
#include "soc_irq.h"
|
||||
|
||||
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
|
||||
#include <stm32f4xx_ll_utils.h>
|
||||
#include <stm32f4xx_ll_bus.h>
|
||||
|
|
|
|||
|
|
@ -1,125 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Linaro Limited.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file Interrupt numbers for STM32F4 family processors.
|
||||
*
|
||||
* Based on reference manual:
|
||||
* RM0368 Reference manual STM32F401xB/C and STM32F401xD/E
|
||||
* advanced ARM(r)-based 32-bit MCUs
|
||||
*
|
||||
* Chapter 10.1.3: Interrupt and exception vectors
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _STM32F4_SOC_IRQ_H_
|
||||
#define _STM32F4_SOC_IRQ_H_
|
||||
|
||||
#define STM32F4_IRQ_WWDG 0
|
||||
#define STM32F4_IRQ_PVD 1
|
||||
#define STM32F4_IRQ_EXTI16 STM32F4_IRQ_PVD
|
||||
#define STM32F4_IRQ_TAMP_STAMP 2
|
||||
#define STM32F4_IRQ_EXTI21 STM32F4_IRQ_TAMP_STAMP
|
||||
#define STM32F4_IRQ_RTC_WKUP 3
|
||||
#define STM32F4_IRQ_EXTI22 STM32F4_IRQ_RTC_WKUP
|
||||
#define STM32F4_IRQ_FLASH 4
|
||||
#define STM32F4_IRQ_RCC 5
|
||||
#define STM32F4_IRQ_EXTI0 6
|
||||
#define STM32F4_IRQ_EXTI1 7
|
||||
#define STM32F4_IRQ_EXTI2 8
|
||||
#define STM32F4_IRQ_EXTI3 9
|
||||
#define STM32F4_IRQ_EXTI4 10
|
||||
#define STM32F4_IRQ_DMA1_STREAM0 11
|
||||
#define STM32F4_IRQ_DMA1_STREAM1 12
|
||||
#define STM32F4_IRQ_DMA1_STREAM2 13
|
||||
#define STM32F4_IRQ_DMA1_STREAM3 14
|
||||
#define STM32F4_IRQ_DMA1_STREAM4 15
|
||||
#define STM32F4_IRQ_DMA1_STREAM5 16
|
||||
#define STM32F4_IRQ_DMA1_STREAM6 17
|
||||
#define STM32F4_IRQ_ADC 18
|
||||
#define STM32F4_IRQ_CAN1_TX 19
|
||||
#define STM32F4_IRQ_CAN1_RX0 20
|
||||
#define STM32F4_IRQ_CAN1_RX1 21
|
||||
#define STM32F4_IRQ_CAN1_SCE 22
|
||||
#define STM32F4_IRQ_EXTI9_5 23
|
||||
#define STM32F4_IRQ_TIM1_BRK_TIM9 24
|
||||
#define STM32F4_IRQ_TIM1_UP_TIM10 25
|
||||
#define STM32F4_IRQ_TIM1_TRG_COM_TIM11 26
|
||||
#define STM32F4_IRQ_TIM1_CC 27
|
||||
#define STM32F4_IRQ_TIM2 28
|
||||
#define STM32F4_IRQ_TIM3 29
|
||||
#define STM32F4_IRQ_TIM4 30
|
||||
#define STM32F4_IRQ_I2C1_EV 31
|
||||
#define STM32F4_IRQ_I2C1_ER 32
|
||||
#define STM32F4_IRQ_I2C2_EV 33
|
||||
#define STM32F4_IRQ_I2C2_ER 34
|
||||
#define STM32F4_IRQ_SPI1 35
|
||||
#define STM32F4_IRQ_SPI2 36
|
||||
#define STM32F4_IRQ_USART1 37
|
||||
#define STM32F4_IRQ_USART2 38
|
||||
#define STM32F4_IRQ_USART3 39
|
||||
#define STM32F4_IRQ_EXTI15_10 40
|
||||
#define STM32F4_IRQ_RTC_ALARM 41
|
||||
#define STM32F4_IRQ_EXTI17 STM32F4_IRQ_RTC_ALARM
|
||||
#define STM32F4_IRQ_OTG_FS_WKUP 42
|
||||
#define STM32F4_IRQ_EXTI18 STM32F4_IRQ_OTG_FS_WKUP
|
||||
#define STM32F4_IRQ_TIM8_BRK_TIM12 43
|
||||
#define STM32F4_IRQ_TIM8_UP_TIM12 44
|
||||
#define STM32F4_IRQ_TIM8_TRG_COM_TIM14 45
|
||||
#define STM32F4_IRQ_TIM8_CC 46
|
||||
#define STM32F4_IRQ_DMA1_STREAM7 47
|
||||
#define STM32F4_IRQ_FSMC 48
|
||||
#define STM32F4_IRQ_SDIO 49
|
||||
#define STM32F4_IRQ_TIM5 50
|
||||
#define STM32F4_IRQ_SPI3 51
|
||||
#define STM32F4_IRQ_UART4 52
|
||||
#define STM32F4_IRQ_UART5 53
|
||||
#define STM32F4_IRQ_TIM6_DAC 54
|
||||
#define STM32F4_IRQ_TIM7 55
|
||||
#define STM32F4_IRQ_DMA2_STREAM0 56
|
||||
#define STM32F4_IRQ_DMA2_STREAM1 57
|
||||
#define STM32F4_IRQ_DMA2_STREAM2 58
|
||||
#define STM32F4_IRQ_DMA2_STREAM3 59
|
||||
#define STM32F4_IRQ_DMA2_STREAM4 60
|
||||
#define STM32F4_IRQ_ETH 61
|
||||
#define STM32F4_IRQ_ETH_WKUP 62
|
||||
#define STM32F4_IRQ_CAN2_TX 63
|
||||
#define STM32F4_IRQ_CAN2_RX0 64
|
||||
#define STM32F4_IRQ_CAN2_RX1 65
|
||||
#define STM32F4_IRQ_CAN2_SCE 66
|
||||
#define STM32F4_IRQ_OTG_FS 67
|
||||
#define STM32F4_IRQ_DMA2_STREAM5 68
|
||||
#define STM32F4_IRQ_DMA2_STREAM6 69
|
||||
#define STM32F4_IRQ_DMA2_STREAM7 70
|
||||
#define STM32F4_IRQ_USART6 71
|
||||
#define STM32F4_IRQ_I2C3_EV 72
|
||||
#define STM32F4_IRQ_I2C3_ER 73
|
||||
#define STM32F4_IRQ_OTG_HS_EP1_OUT 74
|
||||
#define STM32F4_IRQ_OTG_HS_EP1_IN 75
|
||||
#define STM32F4_IRQ_OTG_HS_WKUP 76
|
||||
#define STM32F4_IRQ_OTG_HS 77
|
||||
#define STM32F4_IRQ_DCMI 78
|
||||
#define STM32F4_IRQ_CRYP 79
|
||||
#define STM32F4_IRQ_HASH_RNG 80
|
||||
#define STM32F4_IRQ_FPU 81
|
||||
#define STM32F4_IRQ_UART7 82
|
||||
#define STM32F4_IRQ_UART8 83
|
||||
#define STM32F4_IRQ_SPI4 84
|
||||
#define STM32F4_IRQ_SPI5 85
|
||||
#define STM32F4_IRQ_SPI6 86
|
||||
#define STM32F4_IRQ_SAI1 87
|
||||
#define STM32F4_IRQ_LTDC 88
|
||||
#define STM32F4_IRQ_LTDC_ER 89
|
||||
#define STM32F4_IRQ_DMA2D 90
|
||||
#define STM32F4_IRQ_QUADSPI 91
|
||||
#define STM32F4_IRQ_DSI 92
|
||||
#define STM32F4_IRQ_CEC 93
|
||||
#define STM32F4_IRQ_SPDIF_RX 94
|
||||
#define STM32F4_IRQ_FMPI2C1_EV 95
|
||||
#define STM32F4_IRQ_FMPI2C1_ER 96
|
||||
#define STM32F4_IRQ_LPTIM1 97
|
||||
|
||||
#endif /* _STM32F4_SOC_IRQ_H_ */
|
||||
|
|
@ -29,8 +29,6 @@
|
|||
|
||||
#include <stm32l0xx.h>
|
||||
|
||||
#include "soc_irq.h"
|
||||
|
||||
#include <stm32l0xx_ll_system.h>
|
||||
|
||||
#ifdef CONFIG_SERIAL_HAS_DRIVER
|
||||
|
|
|
|||
|
|
@ -1,58 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Endre Karlson <endre.karlson@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file Interrupt numbers for STM32L0 family processors.
|
||||
*
|
||||
* Based on reference manual:
|
||||
* STM32L0X advanced ARM ® -based 32-bit MCUs
|
||||
*
|
||||
* Chapter 11.1.3: Interrupt and exception vectors
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _STM32L0_SOC_IRQ_H_
|
||||
#define _STM32L0_SOC_IRQ_H_
|
||||
|
||||
/* FIXME: Remove when use of enum line number in IRQ_CONNECT is
|
||||
* made possible by GH-2657.
|
||||
* soc_irq.h, once it is possible, should be removed.
|
||||
*/
|
||||
|
||||
#define STM32L0_IRQ_WWDG 0
|
||||
#define STM32L0_IRQ_PVD 1
|
||||
#define STM32L0_IRQ_RTC 2
|
||||
#define STM32L0_IRQ_FLASH 3
|
||||
#define STM32L0_IRQ_RCC 4
|
||||
#define STM32L0_IRQ_EXTI0_1 5
|
||||
#define STM32L0_IRQ_EXTI2_3 6
|
||||
#define STM32L0_IRQ_EXTI4_15 7
|
||||
#define STM32L0_IRQ_TSC 8
|
||||
#define STM32L0_IRQ_DMA_CH1 9
|
||||
#define STM32L0_IRQ_DMA_CH2_3 10
|
||||
#define STM32L0_IRQ_DMA_CH4_7 11
|
||||
#define STM32L0_IRQ_ADC 12
|
||||
#define STM32L0_IRQ_LPTIM1 13
|
||||
#define STM32L0_IRQ_USART_4_5 14
|
||||
#define STM32L0_IRQ_TIM2 15
|
||||
#define STM32L0_IRQ_TIM3 16
|
||||
#define STM32L0_IRQ_TIM6_DAC 17
|
||||
#define STM32L0_IRQ_TIM7 18
|
||||
/* reserved */
|
||||
#define STM32L0_IRQ_TIM21 20
|
||||
#define STM32L0_IRQ_I2C3 21
|
||||
#define STM32L0_IRQ_TIM22 22
|
||||
#define STM32L0_IRQ_I2C1 23
|
||||
#define STM32L0_IRQ_I2C2 24
|
||||
#define STM32L0_IRQ_SPI1 25
|
||||
#define STM32L0_IRQ_SPI2 26
|
||||
#define STM32L0_IRQ_USART1 27
|
||||
#define STM32L0_IRQ_USART2 28
|
||||
#define STM32L0_IRQ_LPUART1_AES_RNG 29
|
||||
#define STM32L0_IRQ_LCD 30
|
||||
#define STM32L0_IRQ_USB 31
|
||||
|
||||
#endif /* _STM32L0_SOC_IRQ_H_ */
|
||||
|
|
@ -29,8 +29,6 @@
|
|||
/* base address for where GPIO registers start */
|
||||
#define GPIO_PORTS_BASE (GPIOA_BASE)
|
||||
|
||||
#include "soc_irq.h"
|
||||
|
||||
#ifdef CONFIG_SERIAL_HAS_DRIVER
|
||||
#include <stm32l4xx_ll_usart.h>
|
||||
#include <stm32l4xx_ll_lpuart.h>
|
||||
|
|
|
|||
|
|
@ -1,101 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Open-RnD Sp. z o.o.
|
||||
* Copyright (c) 2016 BayLibre, SAS
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _STM32L4_SOC_IRQ_H_
|
||||
#define _STM32L4_SOC_IRQ_H_
|
||||
|
||||
/*
|
||||
* We cannot use the enum present in the ST headers for the IRQs because
|
||||
* of the IRQ_CONNECT macro. The macro exepects a number or a symbol that can
|
||||
* be processed by the preprocessor.
|
||||
*/
|
||||
|
||||
#define STM32L4_IRQ_WWDG 0
|
||||
#define STM32L4_IRQ_PVD 1
|
||||
#define STM32L4_IRQ_TAMPER 2
|
||||
#define STM32L4_IRQ_RTC 3
|
||||
#define STM32L4_IRQ_FLASH 4
|
||||
#define STM32L4_IRQ_RCC 5
|
||||
#define STM32L4_IRQ_EXTI0 6
|
||||
#define STM32L4_IRQ_EXTI1 7
|
||||
#define STM32L4_IRQ_EXTI2 8
|
||||
#define STM32L4_IRQ_EXTI3 9
|
||||
#define STM32L4_IRQ_EXTI4 10
|
||||
#define STM32L4_IRQ_DMA1_CH1 11
|
||||
#define STM32L4_IRQ_DMA1_CH2 12
|
||||
#define STM32L4_IRQ_DMA1_CH3 13
|
||||
#define STM32L4_IRQ_DMA1_CH4 14
|
||||
#define STM32L4_IRQ_DMA1_CH5 15
|
||||
#define STM32L4_IRQ_DMA1_CH6 16
|
||||
#define STM32L4_IRQ_DMA1_CH7 17
|
||||
#define STM32L4_IRQ_ADC1_2 18
|
||||
#define STM32L4_IRQ_CAN_TX 19
|
||||
#define STM32L4_IRQ_CAN_RX0 20
|
||||
#define STM32L4_IRQ_CAN_RX1 21
|
||||
#define STM32L4_IRQ_CAN_SCE 22
|
||||
#define STM32L4_IRQ_EXTI9_5 23
|
||||
#define STM32L4_IRQ_TIM1_BRK 24
|
||||
#define STM32L4_IRQ_TIM1_UP 25
|
||||
#define STM32L4_IRQ_TIM1_TRG_COM 26
|
||||
#define STM32L4_IRQ_TIM1_CC 27
|
||||
#define STM32L4_IRQ_TIM2 28
|
||||
#define STM32L4_IRQ_TIM3 29
|
||||
#define STM32L4_IRQ_TIM4 30
|
||||
#define STM32L4_IRQ_I2C1_EV 31
|
||||
#define STM32L4_IRQ_I2C1_ER 32
|
||||
#define STM32L4_IRQ_I2C2_EV 33
|
||||
#define STM32L4_IRQ_I2C2_ER 34
|
||||
#define STM32L4_IRQ_SPI1 35
|
||||
#define STM32L4_IRQ_SPI2 36
|
||||
#define STM32L4_IRQ_USART1 37
|
||||
#define STM32L4_IRQ_USART2 38
|
||||
#define STM32L4_IRQ_USART3 39
|
||||
#define STM32L4_IRQ_EXTI15_10 40
|
||||
#define STM32L4_IRQ_RTC_ALARM 41
|
||||
#define STM32L4_IRQ_DFSDM1_FLT3 42
|
||||
#define STM32L4_IRQ_TIM8_BRK 43
|
||||
#define STM32L4_IRQ_TIM8_UP 44
|
||||
#define STM32L4_IRQ_TIM8_TRG_COM 45
|
||||
#define STM32L4_IRQ_TIM8_CC 46
|
||||
#define STM32L4_IRQ_ADC3 47
|
||||
#define STM32L4_IRQ_FSMC 48
|
||||
#define STM32L4_IRQ_SDIO 49
|
||||
#define STM32L4_IRQ_TIM5 50
|
||||
#define STM32L4_IRQ_SPI3 51
|
||||
#define STM32L4_IRQ_UART4 52
|
||||
#define STM32L4_IRQ_UART5 53
|
||||
#define STM32L4_IRQ_TIM6 54
|
||||
#define STM32L4_IRQ_TIM7 55
|
||||
#define STM32L4_IRQ_DMA2_CH1 56
|
||||
#define STM32L4_IRQ_DMA2_CH2 57
|
||||
#define STM32L4_IRQ_DMA2_CH3 58
|
||||
#define STM32L4_IRQ_DMA2_CH4 59
|
||||
#define STM32L4_IRQ_DMA2_CH5 60
|
||||
#define STM32L4_IRQ_DFSDM1_FLT0 61
|
||||
#define STM32L4_IRQ_DFSDM1_FLT1 62
|
||||
#define STM32L4_IRQ_DFSDM1_FLT2 63
|
||||
#define STM32L4_IRQ_COMP 64
|
||||
#define STM32L4_IRQ_LPTIM1 65
|
||||
#define STM32L4_IRQ_LPTIM2 66
|
||||
#define STM32L4_IRQ_OTG_FS 67
|
||||
#define STM32L4_IRQ_DMA2_CH6 68
|
||||
#define STM32L4_IRQ_DMA2_CH7 69
|
||||
#define STM32L4_IRQ_LPUART1 70
|
||||
#define STM32L4_IRQ_QUADSPI 71
|
||||
#define STM32L4_IRQ_I2C3_EV 72
|
||||
#define STM32L4_IRQ_I2C3_ER 73
|
||||
#define STM32L4_IRQ_SAI1 74
|
||||
#define STM32L4_IRQ_SAI2 75
|
||||
#define STM32L4_IRQ_SWPMI1 76
|
||||
#define STM32L4_IRQ_TSC 77
|
||||
#define STM32L4_IRQ_LCD 78
|
||||
#define STM32L4_IRQ_AES 79
|
||||
#define STM32L4_IRQ_RNG 80
|
||||
#define STM32L4_IRQ_FPU 81
|
||||
#define STM32L4_IRQ_CRS 82
|
||||
|
||||
#endif /* _STM32L4_SOC_IRQ_H_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue