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drivers: counter: remove qmsi counter driver

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No users of this driver after dropping quark platforms.

COUNTER_0_NAME was only defined by the QMSI driver and was defined but
not used in DTS fixup files of ateml_sam0 SoCs. Removing those leftover
defines as well.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2019-09-17 12:53:43 -04:00 • committed by Maureen Helm
commit 27ff3f15f6
10 changed files with 0 additions and 669 deletions
Download patch file Download diff file Expand all files Collapse all files

3
drivers/counter/CMakeLists.txt
View file

@ -2,8 +2,6 @@
zephyr_library()
zephyr_library_sources_ifdef(CONFIG_AON_COUNTER_QMSI counter_qmsi_aon.c)
zephyr_library_sources_ifdef(CONFIG_AON_TIMER_QMSI counter_qmsi_aonpt.c)
zephyr_library_sources_ifdef(CONFIG_TIMER_TMR_CMSDK_APB timer_tmr_cmsdk_apb.c)
zephyr_library_sources_ifdef(CONFIG_TIMER_DTMR_CMSDK_APB timer_dtmr_cmsdk_apb.c)
zephyr_library_sources_ifdef(CONFIG_COUNTER_GECKO_RTCC counter_gecko_rtcc.c)
@ -11,7 +9,6 @@ zephyr_library_sources_ifdef(CONFIG_COUNTER_IMX_EPIT counter_imx_epit.c)
zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_RTC counter_mcux_rtc.c)
zephyr_library_sources_ifdef(CONFIG_COUNTER_NRF_TIMER counter_nrfx_timer.c)
zephyr_library_sources_ifdef(CONFIG_COUNTER_NRF_RTC counter_nrfx_rtc.c)
zephyr_library_sources_ifdef(CONFIG_RTC_QMSI counter_rtc_qmsi.c)
zephyr_library_sources_ifdef(CONFIG_COUNTER_RTC_STM32 counter_ll_stm32_rtc.c)
zephyr_library_sources_ifdef(CONFIG_COUNTER_SAM0_TC32 counter_sam0_tc32.c)
zephyr_library_sourceS_ifdef(CONFIG_COUNTER_CMOS counter_cmos.c)

2
drivers/counter/Kconfig
View file

@ -19,8 +19,6 @@ source "subsys/logging/Kconfig.template.log_config"
source "drivers/counter/Kconfig.gecko"
source "drivers/counter/Kconfig.qmsi"
source "drivers/counter/Kconfig.tmr_cmsdk_apb"
source "drivers/counter/Kconfig.dtmr_cmsdk_apb"

66
drivers/counter/Kconfig.qmsi
View file

@ -1,66 +0,0 @@
# Kconfig - counter configuration options
#
# Copyright (c) 2016 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
#
config AON_COUNTER_QMSI
bool "AON counter driver"
depends on QMSI
help
Enable support for AON counter.
config AON_COUNTER_QMSI_DEV_NAME
string "QMSI AON Counter Device Name"
depends on AON_COUNTER_QMSI
default "AON_COUNTER"
help
Specify the device name for AON counter driver.
config AON_TIMER_QMSI
bool "AON periodic timer driver"
depends on QMSI
help
Enable support for AON periodic timer.
config COUNTER_0_NAME
string "QMSI AON Timer Device Name"
depends on AON_TIMER_QMSI
default "AON_TIMER"
help
Specify the device name for AON timer driver.
config AON_TIMER_IRQ_PRI
int "Interrupt priority"
depends on AON_TIMER_QMSI
help
aon timer interrupt priority.
config AON_API_REENTRANCY
bool "AON driver API reentrancy"
depends on AON_TIMER_QMSI
help
Enable support for AON driver API reentrancy.
config RTC_QMSI
bool "QMSI RTC Driver"
depends on QMSI
help
Build QMSI RTC driver.
if RTC_QMSI
config RTC_QMSI_API_REENTRANCY
bool "RTC shim driver API reentrancy"
help
Enable support for RTC shim driver API reentrancy.
config RTC_PRESCALER
int "Prescaler size"
default 1
help
RTC prescaler used to determine ticks per second
endif

63
drivers/counter/counter_qmsi_aon.c
View file

@ -1,63 +0,0 @@
/*
* Copyright (c) 2016 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <device.h>
#include <init.h>
#include <drivers/counter.h>
#include "qm_aon_counters.h"
static int aon_counter_qmsi_start(struct device *dev)
{
if (qm_aonc_enable(QM_AONC_0)) {
return -EIO;
}
return 0;
}
static int aon_counter_qmsi_stop(struct device *dev)
{
qm_aonc_disable(QM_AONC_0);
return 0;
}
static u32_t aon_counter_qmsi_read(struct device *dev)
{
u32_t value;
qm_aonc_get_value(QM_AONC_0, (uint32_t *)&value);
return value;
}
static int aon_counter_qmsi_set_top(struct device *dev,
const struct counter_top_cfg *cfg)
{
return -ENODEV;
}
static const struct counter_driver_api aon_counter_qmsi_api = {
.start = aon_counter_qmsi_start,
.stop = aon_counter_qmsi_stop,
.read = aon_counter_qmsi_read,
.set_top_value = aon_counter_qmsi_set_top,
};
static int aon_counter_init(struct device *dev)
{
return 0;
}
DEVICE_AND_API_INIT(aon_counter, CONFIG_AON_COUNTER_QMSI_DEV_NAME,
aon_counter_init, NULL, NULL, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&aon_counter_qmsi_api);

268
drivers/counter/counter_qmsi_aonpt.c
View file

@ -1,268 +0,0 @@
/*
* Copyright (c) 2016 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <device.h>
#include <init.h>
#include <drivers/interrupt_controller/ioapic.h>
#include <drivers/counter.h>
#include <power/power.h>
#include <soc.h>
#include <sys/util.h>
#include "qm_aon_counters.h"
#include "qm_isr.h"
static void aonpt_int_callback(void *user_data);
static counter_top_callback_t user_cb;
struct aonpt_config {
struct counter_config_info info;
};
struct aon_data {
#ifdef CONFIG_AON_API_REENTRANCY
struct k_sem sem;
#endif
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
u32_t device_power_state;
#endif
};
#define AONPT_HAS_CONTEXT_DATA \
(CONFIG_AON_API_REENTRANCY || CONFIG_DEVICE_POWER_MANAGEMENT)
#if AONPT_HAS_CONTEXT_DATA
static struct aon_data aonpt_context;
#define AONPT_CONTEXT (&aonpt_context)
#else
#define AONPT_CONTEXT (NULL)
#endif
#ifdef CONFIG_AON_API_REENTRANCY
#define RP_GET(dev) (&((struct aon_data *)(dev->driver_data))->sem)
#else
#define RP_GET(dev) (NULL)
#endif
static int aon_timer_qmsi_start(struct device *dev)
{
qm_aonpt_config_t qmsi_cfg;
int result = 0;
user_cb = NULL;
qmsi_cfg.callback = NULL;
qmsi_cfg.int_en = false;
/* AONPT is a countdown timer. So, set the initial value to
* the maximum value.
*/
qmsi_cfg.count = 0xffffffff;
qmsi_cfg.callback_data = NULL;
if (IS_ENABLED(CONFIG_AON_API_REENTRANCY)) {
k_sem_take(RP_GET(dev), K_FOREVER);
}
if (qm_aonpt_set_config(QM_AONC_0, &qmsi_cfg)) {
result = -EIO;
}
if (IS_ENABLED(CONFIG_AON_API_REENTRANCY)) {
k_sem_give(RP_GET(dev));
}
return result;
}
static int aon_timer_qmsi_stop(struct device *dev)
{
qm_aonpt_config_t qmsi_cfg;
qmsi_cfg.callback = NULL;
qmsi_cfg.int_en = false;
qmsi_cfg.count = 0;
qmsi_cfg.callback_data = NULL;
if (IS_ENABLED(CONFIG_AON_API_REENTRANCY)) {
k_sem_take(RP_GET(dev), K_FOREVER);
}
qm_aonpt_set_config(QM_AONC_0, &qmsi_cfg);
if (IS_ENABLED(CONFIG_AON_API_REENTRANCY)) {
k_sem_give(RP_GET(dev));
}
return 0;
}
static u32_t aon_timer_qmsi_read(struct device *dev)
{
u32_t value;
qm_aonpt_get_value(QM_AONC_0, (uint32_t *)&value);
return value;
}
static int aon_timer_qmsi_set_top(struct device *dev,
const struct counter_top_cfg *cfg)
{
qm_aonpt_config_t qmsi_cfg;
int result = 0;
/* Counter is always reset when top value is updated. */
if (cfg->flags & COUNTER_TOP_CFG_DONT_RESET) {
return -ENOTSUP;
}
user_cb = cfg->callback;
qmsi_cfg.callback = aonpt_int_callback;
qmsi_cfg.int_en = true;
qmsi_cfg.count = cfg->ticks;
qmsi_cfg.callback_data = cfg->user_data;
if (IS_ENABLED(CONFIG_AON_API_REENTRANCY)) {
k_sem_take(RP_GET(dev), K_FOREVER);
}
if (qm_aonpt_set_config(QM_AONC_0, &qmsi_cfg)) {
user_cb = NULL;
result = -EIO;
}
if (IS_ENABLED(CONFIG_AON_API_REENTRANCY)) {
k_sem_give(RP_GET(dev));
}
return result;
}
static u32_t aon_timer_qmsi_get_pending_int(struct device *dev)
{
return QM_AONC[QM_AONC_0]->aonpt_stat;
}
static const struct counter_driver_api aon_timer_qmsi_api = {
.start = aon_timer_qmsi_start,
.stop = aon_timer_qmsi_stop,
.read = aon_timer_qmsi_read,
.set_top_value = aon_timer_qmsi_set_top,
.get_pending_int = aon_timer_qmsi_get_pending_int,
};
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
static qm_aonc_context_t aonc_ctx;
static void aonpt_qmsi_set_power_state(struct device *dev, u32_t power_state)
{
struct aon_data *context = dev->driver_data;
context->device_power_state = power_state;
}
static u32_t aonpt_qmsi_get_power_state(struct device *dev)
{
struct aon_data *context = dev->driver_data;
return context->device_power_state;
}
static int aonpt_suspend_device(struct device *dev)
{
qm_aonpt_save_context(QM_AONC_0, &aonc_ctx);
aonpt_qmsi_set_power_state(dev, DEVICE_PM_SUSPEND_STATE);
return 0;
}
static int aonpt_resume_device_from_suspend(struct device *dev)
{
qm_aonpt_restore_context(QM_AONC_0, &aonc_ctx);
aonpt_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
return 0;
}
/*
* Implements the driver control management functionality
* the *context may include IN data or/and OUT data
*/
static int aonpt_qmsi_device_ctrl(struct device *dev, u32_t ctrl_command,
void *context, device_pm_cb cb, void *arg)
{
int ret = 0;
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
ret = aonpt_suspend_device(dev);
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
ret = aonpt_resume_device_from_suspend(dev);
}
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
*((u32_t *)context) = aonpt_qmsi_get_power_state(dev);
}
if (cb) {
cb(dev, ret, context, arg);
}
return ret;
}
#else
#define aonpt_qmsi_set_power_state(...)
#endif
static int aon_timer_init(struct device *dev)
{
dev->driver_api = &aon_timer_qmsi_api;
user_cb = NULL;
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_AONPT_0_INT),
CONFIG_AON_TIMER_IRQ_PRI, qm_aonpt_0_isr, NULL,
IOAPIC_EDGE | IOAPIC_HIGH);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_AONPT_0_INT));
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->aonpt_0_int_mask);
if (IS_ENABLED(CONFIG_AON_API_REENTRANCY)) {
k_sem_init(RP_GET(dev), 1, UINT_MAX);
}
aonpt_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
return 0;
}
static const struct aonpt_config aonpt_conf_info = {
.info = {
.max_top_value = UINT32_MAX,
.freq = 32768,
.flags = 0,
.channels = 0,
}
};
DEVICE_DEFINE(aon_timer, CONFIG_COUNTER_0_NAME, aon_timer_init,
aonpt_qmsi_device_ctrl, AONPT_CONTEXT, &aonpt_conf_info,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&aon_timer_qmsi_api);
static void aonpt_int_callback(void *user_data)
{
if (user_cb) {
(*user_cb)(DEVICE_GET(aon_timer), user_data);
}
}

258
drivers/counter/counter_rtc_qmsi.c
View file

@ -1,258 +0,0 @@
/*
* Copyright (c) 2015 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <device.h>
#include <drivers/interrupt_controller/ioapic.h>
#include <drivers/counter.h>
#include <init.h>
#include <kernel.h>
#include <power/power.h>
#include <soc.h>
#include <sys/util.h>
#include "qm_isr.h"
#include "qm_rtc.h"
static void rtc_callback(void *user_data);
static counter_alarm_callback_t user_cb;
struct rtc_config {
struct counter_config_info info;
};
struct rtc_data {
#ifdef CONFIG_RTC_QMSI_API_REENTRANCY
struct k_sem sem;
#endif
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
u32_t device_power_state;
#endif
};
#define RTC_HAS_CONTEXT_DATA \
(CONFIG_RTC_QMSI_API_REENTRANCY || CONFIG_DEVICE_POWER_MANAGEMENT)
#if RTC_HAS_CONTEXT_DATA
static struct rtc_data rtc_context;
#define RTC_CONTEXT (&rtc_context)
#else
#define RTC_CONTEXT (NULL)
#endif /* RTC_HAS_CONTEXT_DATA */
#ifdef CONFIG_RTC_QMSI_API_REENTRANCY
#define RP_GET(dev) (&((struct rtc_data *)(dev->driver_data))->sem)
#else
#define RP_GET(dev) (NULL)
#endif
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
static void rtc_qmsi_set_power_state(struct device *dev, u32_t power_state)
{
struct rtc_data *context = dev->driver_data;
context->device_power_state = power_state;
}
static u32_t rtc_qmsi_get_power_state(struct device *dev)
{
struct rtc_data *context = dev->driver_data;
return context->device_power_state;
}
#else
#define rtc_qmsi_set_power_state(...)
#endif
static int rtc_qmsi_enable(struct device *dev)
{
clk_periph_enable(CLK_PERIPH_RTC_REGISTER | CLK_PERIPH_CLK);
return 0;
}
static int rtc_qmsi_disable(struct device *dev)
{
clk_periph_disable(CLK_PERIPH_RTC_REGISTER);
return 0;
}
static int rtc_qmsi_cancel_alarm(struct device *dev, u8_t chan_id)
{
clk_periph_disable(CLK_PERIPH_RTC_REGISTER);
return 0;
}
static int rtc_qmsi_set_top(struct device *dev,
const struct counter_top_cfg *cfg)
{
const struct counter_config_info *info = dev->config->config_info;
if ((cfg->ticks != info->max_top_value) ||
!(cfg->flags & COUNTER_TOP_CFG_DONT_RESET)) {
return -ENOTSUP;
} else {
return 0;
}
}
static int rtc_qmsi_set_alarm(struct device *dev, u8_t chan_id,
const struct counter_alarm_cfg *alarm_cfg)
{
qm_rtc_config_t qm_cfg;
int result = 0;
qm_cfg.init_val = 0;
qm_cfg.alarm_en = 1;
qm_cfg.alarm_val = alarm_cfg->ticks;
user_cb = alarm_cfg->callback;
/* Casting callback type due different input parameter from QMSI
* compared aganst the Zephyr callback from void cb(struct device *dev)
* to void cb(void *)
*/
qm_cfg.callback = rtc_callback;
qm_cfg.callback_data = (void *)alarm_cfg;
/* Set prescaler value. Ideally, the divider should come from struct
* rtc_config instead. It's safe to use RTC_DIVIDER here for now since
* values defined by clk_rtc_div and by QMSI's clk_rtc_div_t match for
* both D2000 and SE.
*/
qm_cfg.prescaler = (clk_rtc_div_t)CONFIG_RTC_PRESCALER - 1;
if (IS_ENABLED(CONFIG_RTC_QMSI_API_REENTRANCY)) {
k_sem_take(RP_GET(dev), K_FOREVER);
}
if (qm_rtc_set_config(QM_RTC_0, &qm_cfg)) {
result = -EIO;
}
if (IS_ENABLED(CONFIG_RTC_QMSI_API_REENTRANCY)) {
k_sem_give(RP_GET(dev));
}
k_busy_wait(60);
qm_rtc_set_alarm(QM_RTC_0, alarm_cfg->ticks);
return result;
}
static u32_t rtc_qmsi_read(struct device *dev)
{
return QM_RTC[QM_RTC_0]->rtc_ccvr;
}
static u32_t rtc_qmsi_get_pending_int(struct device *dev)
{
return QM_RTC[QM_RTC_0]->rtc_stat;
}
static const struct counter_driver_api api = {
.start = rtc_qmsi_enable,
.stop = rtc_qmsi_disable,
.read = rtc_qmsi_read,
.set_top_value = rtc_qmsi_set_top,
.set_alarm = rtc_qmsi_set_alarm,
.cancel_alarm = rtc_qmsi_cancel_alarm,
.get_pending_int = rtc_qmsi_get_pending_int,
};
static int rtc_qmsi_init(struct device *dev)
{
if (IS_ENABLED(CONFIG_RTC_QMSI_API_REENTRANCY)) {
k_sem_init(RP_GET(dev), 1, UINT_MAX);
}
IRQ_CONNECT(DT_RTC_0_IRQ, DT_RTC_0_IRQ_PRI,
qm_rtc_0_isr, NULL, DT_RTC_0_IRQ_FLAGS);
/* Unmask RTC interrupt */
irq_enable(DT_RTC_0_IRQ);
/* Route RTC interrupt to the current core */
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->rtc_0_int_mask);
rtc_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
return 0;
}
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
static qm_rtc_context_t rtc_ctx;
static int rtc_suspend_device(struct device *dev)
{
qm_rtc_save_context(QM_RTC_0, &rtc_ctx);
rtc_qmsi_set_power_state(dev, DEVICE_PM_SUSPEND_STATE);
return 0;
}
static int rtc_resume_device(struct device *dev)
{
qm_rtc_restore_context(QM_RTC_0, &rtc_ctx);
rtc_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
return 0;
}
/*
* Implements the driver control management functionality
* the *context may include IN data or/and OUT data
*/
static int rtc_qmsi_device_ctrl(struct device *dev, u32_t ctrl_command,
void *context, device_pm_cb cb, void *arg)
{
int ret = 0;
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
ret = rtc_suspend_device(dev);
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
ret = rtc_resume_device(dev);
}
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
*((u32_t *)context) = rtc_qmsi_get_power_state(dev);
}
if (cb) {
cb(dev, ret, context, arg);
}
return ret;
}
#endif
static const struct rtc_config rtc_conf_info = {
.info = {
.max_top_value = UINT32_MAX,
.freq = 32768,
.flags = COUNTER_CONFIG_INFO_COUNT_UP,
.channels = 1,
}
};
DEVICE_DEFINE(rtc, DT_RTC_0_NAME, &rtc_qmsi_init, rtc_qmsi_device_ctrl,
RTC_CONTEXT, &rtc_conf_info, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &api);
static void rtc_callback(void *user_data)
{
const struct counter_alarm_cfg *cfg = user_data;
if (user_cb) {
(*user_cb)(DEVICE_GET(rtc), 0, cfg->ticks, user_data);
}
}

2
soc/arm/atmel_sam0/samd20/dts_fixup.h
View file

@ -6,8 +6,6 @@
#define CONFIG_WDT_0_NAME DT_INST_0_ATMEL_SAM0_WATCHDOG_LABEL
#define CONFIG_COUNTER_0_NAME DT_INST_0_ATMEL_SAM0_TC32_LABEL
#define CONFIG_I2C_0_NAME DT_INST_0_ATMEL_SAM0_I2C_LABEL
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS

2
soc/arm/atmel_sam0/samd21/dts_fixup.h
View file

@ -6,8 +6,6 @@
#define CONFIG_WDT_0_NAME DT_INST_0_ATMEL_SAM0_WATCHDOG_LABEL
#define CONFIG_COUNTER_0_NAME DT_INST_0_ATMEL_SAM0_TC32_LABEL
#define CONFIG_I2C_0_NAME DT_INST_0_ATMEL_SAM0_I2C_LABEL
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS

2
soc/arm/atmel_sam0/samr21/dts_fixup.h
View file

@ -10,8 +10,6 @@
#define CONFIG_WDT_0_NAME DT_INST_0_ATMEL_SAM0_WATCHDOG_LABEL
#define CONFIG_COUNTER_0_NAME DT_INST_0_ATMEL_SAM0_TC32_LABEL
#define CONFIG_I2C_0_NAME DT_INST_0_ATMEL_SAM0_I2C_LABEL
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS

3
tests/drivers/counter/counter_basic_api/src/test_counter.c
View file

@ -72,9 +72,6 @@ const char *devices[] = {
DT_RTC_0_NAME,
#endif
#ifdef CONFIG_COUNTER_0_NAME
CONFIG_COUNTER_0_NAME,
#endif
};
typedef void (*counter_test_func_t)(const char *dev_name);