From 276bcd724e4e086942b521c4cd4bc9fb20b9e3bf Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Mon, 12 Apr 2021 14:35:09 +0200 Subject: [PATCH] include/drivers: clock_control: Add support for STM32L0 bindings Add support for STM32L0 clocks bindings. Also, add a small tweak to SYSCLK selection to factorize some lines. Signed-off-by: Erwan Gouriou --- .../clock_control/stm32_clock_control.h | 22 ++++++++++--------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/include/drivers/clock_control/stm32_clock_control.h b/include/drivers/clock_control/stm32_clock_control.h index b248189030e..e0c701b6dd9 100644 --- a/include/drivers/clock_control/stm32_clock_control.h +++ b/include/drivers/clock_control/stm32_clock_control.h @@ -98,11 +98,15 @@ /* We don't need to make a disctinction between PREDIV and PREDIV1 in dts */ /* As PREDIV and PREDIV1 have the same description we can use prop prediv for both */ #define STM32_PLL_PREDIV STM32_PLL_PREDIV1 +#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay) +#define STM32_PLL_DIVISOR DT_PROP(DT_NODELABEL(pll), div) +#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul) #else #define STM32_PLL_XTPRE CONFIG_CLOCK_STM32_PLL_XTPRE #define STM32_PLL_MULTIPLIER CONFIG_CLOCK_STM32_PLL_MULTIPLIER #define STM32_PLL_PREDIV1 CONFIG_CLOCK_STM32_PLL_PREDIV1 #define STM32_PLL_PREDIV CONFIG_CLOCK_STM32_PLL_PREDIV +#define STM32_PLL_DIVISOR CONFIG_CLOCK_STM32_PLL_DIVISOR #endif #define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc)) @@ -110,14 +114,10 @@ #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32_rcc, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32f0_rcc, okay)) && \ DT_NODE_HAS_PROP(DT_NODELABEL(rcc), clocks) -#define STM32_SYSCLK_SRC_PLL DT_NODE_HAS_PROP(DT_NODELABEL(rcc), clocks) && \ - DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(pll)) -#define STM32_SYSCLK_SRC_HSI DT_NODE_HAS_PROP(DT_NODELABEL(rcc), clocks) && \ - DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) -#define STM32_SYSCLK_SRC_HSE DT_NODE_HAS_PROP(DT_NODELABEL(rcc), clocks) && \ - DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) -#define STM32_SYSCLK_SRC_MSI DT_NODE_HAS_PROP(DT_NODELABEL(rcc), clocks) && \ - DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msi)) +#define STM32_SYSCLK_SRC_PLL DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(pll)) +#define STM32_SYSCLK_SRC_HSI DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) +#define STM32_SYSCLK_SRC_HSE DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) +#define STM32_SYSCLK_SRC_MSI DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msi)) #else #define STM32_SYSCLK_SRC_PLL CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL #define STM32_SYSCLK_SRC_HSI CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI @@ -135,7 +135,8 @@ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f0_pll_clock, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \ - DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay)) && \ + DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \ + DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay)) && \ DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks) #define STM32_PLL_SRC_MSI DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi)) #define STM32_PLL_SRC_HSI DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) @@ -154,7 +155,8 @@ #define STM32_LSE_CLOCK CONFIG_CLOCK_STM32_LSE #endif -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \ + DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay) #define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range) #else #define STM32_MSI_RANGE CONFIG_CLOCK_STM32_MSI_RANGE