michaelh/zephyr
1
0
Fork 0
Code Releases Activity

Fixed file description and applied doxygen style

Browse source 
Removed old style file description and documnetation and apply
doxygen synatx.

Change-Id: I3ac9f06d4f574bf3c79c6f6044cec3a7e2f6e4c8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2015-12-04 10:09:39 -05:00
commit 275ca60b08
182 changed files with 796 additions and 796 deletions
Download patch file Download diff file Expand all files Collapse all files

14
arch/arc/core/atomic.S
View file

@ -1,5 +1,3 @@
/* armAtomic.S - ARC atomic operations library */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,11 +14,13 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
This library provides routines to perform a number of atomic operations * @brief ARC atomic operations library
on a memory location: add, subtract, increment, decrement, bitwise OR, *
bitwise NOR, bitwise AND, bitwise NAND, set, clear and compare-and-swap. * This library provides routines to perform a number of atomic operations
* on a memory location: add, subtract, increment, decrement, bitwise OR,
* bitwise NOR, bitwise AND, bitwise NAND, set, clear and compare-and-swap.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

10
arch/arc/core/cpu_idle.S
View file

@ -1,5 +1,3 @@
/* cpu_idle.S - CPU power management */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,9 +14,11 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
CPU power management routines. * @brief CPU power management
*
* CPU power management routines.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

14
arch/arc/core/fast_irq.S
View file

@ -1,5 +1,3 @@
/* fast_irq.S - handling of transitions to-and-from fast IRQs (FIRQ) */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,11 +14,13 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
This module implements the code for handling entry to and exit from Fast IRQs. * @brief Handling of transitions to-and-from fast IRQs (FIRQ)
*
See isr_wrapper.S for details. * This module implements the code for handling entry to and exit from Fast IRQs.
*
* See isr_wrapper.S for details.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

8
arch/arc/core/fatal.c
View file

@ -1,5 +1,3 @@
/* fatal.c - fatal fault handling */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Fatal fault handling
*
* This module implements the routines necessary for handling fatal faults on * This module implements the routines necessary for handling fatal faults on
* ARCv2 CPUs. * ARCv2 CPUs.
*/ */

8
arch/arc/core/fault.c
View file

@ -1,5 +1,3 @@
/* fault.c - common fault handler for ARCv2 */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Common fault handler for ARCv2
*
* Common fault handler for ARCv2 processors. * Common fault handler for ARCv2 processors.
*/ */

8
arch/arc/core/fault_s.S
View file

@ -1,5 +1,3 @@
/* fault_s.S - fault handlers for ARCv2 */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Fault handlers for ARCv2
*
* Fault handlers for ARCv2 processors. * Fault handlers for ARCv2 processors.
*/ */

8
arch/arc/core/irq_manage.c
View file

@ -1,5 +1,3 @@
/* irq_manage.c - ARCv2 interrupt management */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief ARCv2 interrupt management
*
* *
* Interrupt management: * Interrupt management:
* *

14
arch/arc/core/isr_wrapper.S
View file

@ -1,5 +1,3 @@
/* isr_wrapper.S - wrapper around ISRs with logic for context switching */
/* /*
* Copyright (c) 2014-2015 Wind River Systems, Inc. * Copyright (c) 2014-2015 Wind River Systems, Inc.
* *
@ -16,11 +14,13 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
* @brief Wrapper around ISRs with logic for context switching
Wrapper installed in vector table for handling dynamic interrupts that accept *
a parameter. *
* Wrapper installed in vector table for handling dynamic interrupts that accept
* a parameter.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

8
arch/arc/core/offsets/offsets.c
View file

@ -1,5 +1,3 @@
/* offsets.c - ARCv2 nano kernel structure member offset definition file */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief ARCv2 nano kernel structure member offset definition file
*
* This module is responsible for the generation of the absolute symbols whose * This module is responsible for the generation of the absolute symbols whose
* value represents the member offsets for various ARCv2 nanokernel * value represents the member offsets for various ARCv2 nanokernel
* structures. * structures.

8
arch/arc/core/prep_c.c
View file

@ -1,5 +1,3 @@
/* prep_c.c - full C support initialization */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Full C support initialization
*
* *
* Initialization of full C support: zero the .bss, copy the .data if XIP, * Initialization of full C support: zero the .bss, copy the .data if XIP,
* call _Cstart(). * call _Cstart().

16
arch/arc/core/regular_irq.S
View file

@ -1,5 +1,3 @@
/* regular_irq.S - handling of transitions to-and-from regular IRQs (RIRQ) */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,12 +14,14 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
This module implements the code for handling entry to and exit from regular * @brief Handling of transitions to-and-from regular IRQs (RIRQ)
IRQs. *
* This module implements the code for handling entry to and exit from regular
See isr_wrapper.S for details. * IRQs.
*
* See isr_wrapper.S for details.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

10
arch/arc/core/reset.S
View file

@ -1,5 +1,3 @@
/* reset.S - reset handler */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,9 +14,11 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
Reset handler that prepares the system for running C code. * @brief Reset handler
*
* Reset handler that prepares the system for running C code.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

16
arch/arc/core/swap.S
View file

@ -1,5 +1,3 @@
/* swap.S - thread context switching */
/* /*
* Copyright (c) 2014-2015 Wind River Systems, Inc. * Copyright (c) 2014-2015 Wind River Systems, Inc.
* *
@ -16,12 +14,14 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
This module implements the routines necessary for thread context switching * @brief Thread context switching
on ARCv2 CPUs. *
* This module implements the routines necessary for thread context switching
See isr_wrapper.S for details. * on ARCv2 CPUs.
*
* See isr_wrapper.S for details.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

8
arch/arc/core/sys_fatal_error_handler.c
View file

@ -1,5 +1,3 @@
/* fatal_error.c - ARCv2 system fatal error handler */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief ARCv2 system fatal error handler
*
* This module provides the _SysFatalErrorHandler() routine for ARCv2 BSPs. * This module provides the _SysFatalErrorHandler() routine for ARCv2 BSPs.
*/ */

8
arch/arc/core/thread.c
View file

@ -1,5 +1,3 @@
/* thread.c - new thread creation for ARCv2 */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief New thread creation for ARCv2
*
* Core nanokernel fiber related primitives for the ARCv2 processor * Core nanokernel fiber related primitives for the ARCv2 processor
* architecture. * architecture.
*/ */

8
arch/arc/core/thread_entry_wrapper.S
View file

@ -1,5 +1,3 @@
/* thread_entry_wrapper.S - wrapper for _thread_entry */
/* /*
* Copyright (c) 2014-2015 Wind River Systems, Inc. * Copyright (c) 2014-2015 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Wrapper for _thread_entry
*
* Wrapper for _thread_entry routine when called from the initial context. * Wrapper for _thread_entry routine when called from the initial context.
*/ */

8
arch/arc/core/vector_table.c
View file

@ -1,5 +1,3 @@
/* vector_table.c - populated exception vector table */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Populated exception vector table
*
* Vector table with exceptions filled in. The reset vector is the system entry * Vector table with exceptions filled in. The reset vector is the system entry
* point, ie. the first instruction executed. * point, ie. the first instruction executed.
* *

8
arch/arc/include/nano_private.h
View file

@ -1,5 +1,3 @@
/* nano_private.h - private nanokernel definitions */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Private nanokernel definitions
*
* This file contains private nanokernel structures definitions and various * This file contains private nanokernel structures definitions and various
* other definitions for the ARCv2 processor architecture. * other definitions for the ARCv2 processor architecture.
* *

8
arch/arc/include/v2/cache.h
View file

@ -1,5 +1,3 @@
/* cache.h - cache helper functions (ARC) */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Cache helper functions (ARC)
*
* This file contains private nanokernel structures definitions and various * This file contains private nanokernel structures definitions and various
* other definitions for the ARCv2 processor architecture. * other definitions for the ARCv2 processor architecture.
*/ */

8
arch/arc/include/v2/irq.h
View file

@ -1,5 +1,3 @@
/* irq.h - interrupt helper functions (ARC) */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Interrupt helper functions (ARC)
*
* This file contains private nanokernel structures definitions and various * This file contains private nanokernel structures definitions and various
* other definitions for the ARCv2 processor architecture. * other definitions for the ARCv2 processor architecture.
*/ */

8
arch/arc/include/vector_table.h
View file

@ -1,5 +1,3 @@
/* vector_table.h - definitions for the exception vector table */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Definitions for the exception vector table
*
* *
* Definitions for the boot vector table. * Definitions for the boot vector table.
* *

8
arch/arc/platforms/generic_arc/board.h
View file

@ -1,5 +1,3 @@
/* board.h - board configuration macros for the generic arc BSP */
/* /*
* Copyright (c) 2014-2015 Wind River Systems, Inc. * Copyright (c) 2014-2015 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Board configuration macros for the generic arc BSP
*
* This header file is used to specify and describe board-level aspects for the * This header file is used to specify and describe board-level aspects for the
* generic arc BSP. * generic arc BSP.
*/ */

8
arch/arc/platforms/generic_arc/irq_vector_table.c
View file

@ -1,5 +1,3 @@
/* irq_vector_table.c - IRQ part of vector table for generic arc BSP */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief IRQ part of vector table for generic arc BSP
*
* This file contains the IRQ part of the vector table. It is meant to be used * This file contains the IRQ part of the vector table. It is meant to be used
* for one of two cases: * for one of two cases:
* *

12
arch/arc/platforms/generic_arc/linker.cmd
View file

@ -1,5 +1,3 @@
/* linker.cmd - Linker command/script file */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,10 +14,12 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
This is the linker script for both standard images and XIP images. * @brief Linker command/script file
*/ *
* This is the linker script for both standard images and XIP images.
*/
/* Flash base address and size */ /* Flash base address and size */
#define FLASH_START 0x40034000 /* Flash bank 1 */ #define FLASH_START 0x40034000 /* Flash bank 1 */

8
arch/arc/platforms/generic_arc/sw_isr_table.c
View file

@ -1,5 +1,3 @@
/* sw_isr_table.c - Software ISR table for generic arc BSP */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Software ISR table for generic arc BSP
*
* This contains the ISR table meant to be used for ISRs that take a parameter. * This contains the ISR table meant to be used for ISRs that take a parameter.
* It is also used when ISRs are to be connected at runtime, and in this case * It is also used when ISRs are to be connected at runtime, and in this case
* provides a table that is filled with _SpuriousIRQ bindings. * provides a table that is filled with _SpuriousIRQ bindings.

8
arch/arc/platforms/generic_arc/system.c
View file

@ -1,5 +1,3 @@
/* system.c - system/hardware module for generic arc BSP */
/* /*
* Copyright (c) 2014-2015 Wind River Systems, Inc. * Copyright (c) 2014-2015 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief System/hardware module for generic arc BSP
*
* This module provides routines to initialize and support board-level hardware * This module provides routines to initialize and support board-level hardware
* for the generic arc platform. * for the generic arc platform.
*/ */

14
arch/arm/core/atomic.S
View file

@ -1,5 +1,3 @@
/* armAtomic.S - ARM atomic operations library */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,11 +14,13 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
This library provides routines to perform a number of atomic operations * @brief ARM atomic operations library
on a memory location: add, subtract, increment, decrement, bitwise OR, *
bitwise NOR, bitwise AND, bitwise NAND, set, clear and compare-and-swap. * This library provides routines to perform a number of atomic operations
* on a memory location: add, subtract, increment, decrement, bitwise OR,
* bitwise NOR, bitwise AND, bitwise NAND, set, clear and compare-and-swap.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

8
arch/arm/core/cortex_m/nmi.c
View file

@ -1,5 +1,3 @@
/* nmi.c - NMI handler infrastructure */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief NMI handler infrastructure
*
* Provides a boot time handler that simply hangs in a sleep loop, and a run * Provides a boot time handler that simply hangs in a sleep loop, and a run
* time handler that resets the CPU. Also provides a mechanism for hooking a * time handler that resets the CPU. Also provides a mechanism for hooking a
* custom run time handler. * custom run time handler.

8
arch/arm/core/cortex_m/prep_c.c
View file

@ -1,5 +1,3 @@
/* prep_c.c - full C support initialization */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Full C support initialization
*
* *
* Initialization of full C support: zero the .bss, copy the .data if XIP, * Initialization of full C support: zero the .bss, copy the .data if XIP,
* call _Cstart(). * call _Cstart().

10
arch/arm/core/cortex_m/reset.S
View file

@ -1,5 +1,3 @@
/* reset_s.S - reset handler */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,9 +14,11 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
Reset handler that prepares the system for running C code. * @brief Reset handler
*
* Reset handler that prepares the system for running C code.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

8
arch/arm/core/cortex_m/scb.c
View file

@ -1,5 +1,3 @@
/* scb.h - ARM CORTEX-M3 System Control Block interface */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief ARM CORTEX-M3 System Control Block interface
*
* *
* Most of the SCB interface consists of simple bit-flipping methods, and is * Most of the SCB interface consists of simple bit-flipping methods, and is
* implemented as inline functions in scb.h. This module thus contains only data * implemented as inline functions in scb.h. This module thus contains only data

8
arch/arm/core/cortex_m/scs.c
View file

@ -1,5 +1,3 @@
/* scs.c - ARM CORTEX-M Series System Control Space */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief ARM CORTEX-M Series System Control Space
*
* Most of the SCS interface consists of simple bit-flipping methods, and is * Most of the SCS interface consists of simple bit-flipping methods, and is
* implemented as inline functions in scs.h. This module thus contains only data * implemented as inline functions in scs.h. This module thus contains only data
* definitions and more complex routines, if needed. * definitions and more complex routines, if needed.

10
arch/arm/core/cortex_m/sw_isr_table.S
View file

@ -1,5 +1,3 @@
/* ISR table for static ISR declarations for ARM */
/* /*
* Copyright (c) 2015 Wind River Systems, Inc. * Copyright (c) 2015 Wind River Systems, Inc.
* *
@ -16,9 +14,11 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
Software ISR table for ARM * @brief ISR table for static ISR declarations for ARM
*
* Software ISR table for ARM
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

20
arch/arm/core/cortex_m/vector_table.S
View file

@ -1,5 +1,3 @@
/* vector_table.S - populated vector table in ROM */
/* /*
* Copyright (c) 2013-2015 Wind River Systems, Inc. * Copyright (c) 2013-2015 Wind River Systems, Inc.
* *
@ -16,14 +14,16 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
Vector table in ROM for starting system. The reset vector is the system entry * @brief Populated vector table in ROM
point, ie. the first instruction executed. *
* Vector table in ROM for starting system. The reset vector is the system entry
The table is populated with all the system exception handlers. The NMI vector * point, ie. the first instruction executed.
must be populated with a valid handler since it can happen at any time. The *
rest should not be triggered until the kernel is ready to handle them. * The table is populated with all the system exception handlers. The NMI vector
* must be populated with a valid handler since it can happen at any time. The
* rest should not be triggered until the kernel is ready to handle them.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

8
arch/arm/core/cortex_m/vector_table.h
View file

@ -1,5 +1,3 @@
/* vector_table.h - definitions for the boot vector table */
/* /*
* Copyright (c) 2013-2015 Wind River Systems, Inc. * Copyright (c) 2013-2015 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Definitions for the boot vector table
*
* *
* Definitions for the boot vector table. * Definitions for the boot vector table.
* *

8
arch/arm/core/cpu_idle.S
View file

@ -1,5 +1,3 @@
/* cpu_idle.S - ARM CORTEX-M3 power management */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
* @brief ARM CORTEX-M3 power management
*
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

16
arch/arm/core/exc_exit.S
View file

@ -1,5 +1,3 @@
/* exc_exit.S - ARM CORTEX-M3 exception/interrupt exit API */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,12 +14,14 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
* @brief ARM CORTEX-M3 exception/interrupt exit API
Provides functions for performing kernel handling when exiting exceptions or *
interrupts that are installed directly in the vector table (i.e. that are not *
wrapped around by _isr_wrapper()). * Provides functions for performing kernel handling when exiting exceptions or
* interrupts that are installed directly in the vector table (i.e. that are not
* wrapped around by _isr_wrapper()).
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

8
arch/arm/core/fatal.c
View file

@ -1,5 +1,3 @@
/* fatal.c - nanokernel fatal error handler for ARM Cortex-M */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Nanokernel fatal error handler for ARM Cortex-M
*
* This module provides the _NanoFatalErrorHandler() routine for ARM Cortex-M. * This module provides the _NanoFatalErrorHandler() routine for ARM Cortex-M.
*/ */

8
arch/arm/core/fault.c
View file

@ -1,5 +1,3 @@
/* fault.c - common fault handler for ARM Cortex-M */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Common fault handler for ARM Cortex-M
*
* Common fault handler for ARM Cortex-M processors. * Common fault handler for ARM Cortex-M processors.
*/ */

10
arch/arm/core/fault_s.S
View file

@ -1,5 +1,3 @@
/* fault_s.S - fault handlers for ARM Cortex-M */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,9 +14,11 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
Fault handlers for ARM Cortex-M processors. * @brief Fault handlers for ARM Cortex-M
*
* Fault handlers for ARM Cortex-M processors.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

8
arch/arm/core/fiber_abort.c
View file

@ -1,5 +1,3 @@
/* fiber_abort.c - ARM Cortex-M fiber_abort() routine */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief ARM Cortex-M fiber_abort() routine
*
* The ARM Cortex-M architecture provides its own fiber_abort() to deal with * The ARM Cortex-M architecture provides its own fiber_abort() to deal with
* different CPU modes (handler vs thread) when a fiber aborts. When its entry * different CPU modes (handler vs thread) when a fiber aborts. When its entry
* point returns or when it aborts itself, the CPU is in thread mode and must * point returns or when it aborts itself, the CPU is in thread mode and must

22
arch/arm/core/gdb_stub.S
View file

@ -1,5 +1,3 @@
/* gdb_stub.S - extra work performed upon exception entry/exit for GDB */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,15 +14,17 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
* @brief Extra work performed upon exception entry/exit for GDB
Prep work done when entering exceptions consists of saving the callee-saved *
registers before they get used by exception handlers, and recording the fact *
that we are running in an exception. * Prep work done when entering exceptions consists of saving the callee-saved
* registers before they get used by exception handlers, and recording the fact
Upon exception exit, it must be recorded that the task is not in an exception * that we are running in an exception.
anymore. *
* Upon exception exit, it must be recorded that the task is not in an exception
* anymore.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

8
arch/arm/core/gdb_stub_irq_vector_table.c
View file

@ -1,5 +1,3 @@
/* gdb_stub_irq_vector_table.c - stubs for IRQ part of vector table */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Stubs for IRQ part of vector table
*
* When GDB is enabled, the static IRQ vector table needs to install the * When GDB is enabled, the static IRQ vector table needs to install the
* _irq_vector_table_entry_with_gdb_stub stub to do some work before calling the * _irq_vector_table_entry_with_gdb_stub stub to do some work before calling the
* user-installed ISRs. * user-installed ISRs.

8
arch/arm/core/irq_init.c
View file

@ -1,5 +1,3 @@
/* irq_init.c - ARM Cortex-M interrupt initialization */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief ARM Cortex-M interrupt initialization
*
* The ARM Cortex-M architecture provides its own fiber_abort() to deal with * The ARM Cortex-M architecture provides its own fiber_abort() to deal with
* different CPU modes (handler vs thread) when a fiber aborts. When its entry * different CPU modes (handler vs thread) when a fiber aborts. When its entry
* point returns or when it aborts itself, the CPU is in thread mode and must * point returns or when it aborts itself, the CPU is in thread mode and must

8
arch/arm/core/irq_manage.c
View file

@ -1,5 +1,3 @@
/* irq_manage.c - ARM CORTEX-M3 interrupt management */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief ARM CORTEX-M3 interrupt management
*
* *
* Interrupt management: enabling/disabling and dynamic ISR * Interrupt management: enabling/disabling and dynamic ISR
* connecting/replacing. SW_ISR_TABLE_DYNAMIC has to be enabled for * connecting/replacing. SW_ISR_TABLE_DYNAMIC has to be enabled for

13
arch/arm/core/isr_wrapper.S
View file

@ -1,5 +1,3 @@
/* isr_wrapper.S - ARM CORTEX-M3 wrapper for ISRs with parameter */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,11 +14,12 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
* @brief ARM CORTEX-M3 wrapper for ISRs with parameter
Wrapper installed in vector table for handling dynamic interrupts that accept *
a parameter. * Wrapper installed in vector table for handling dynamic interrupts that accept
* a parameter.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

8
arch/arm/core/offsets/offsets.c
View file

@ -1,5 +1,3 @@
/* offsets.c - ARM nano kernel structure member offset definition file */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief ARM nano kernel structure member offset definition file
*
* This module is responsible for the generation of the absolute symbols whose * This module is responsible for the generation of the absolute symbols whose
* value represents the member offsets for various ARM nanokernel * value represents the member offsets for various ARM nanokernel
* structures. * structures.

12
arch/arm/core/swap.S
View file

@ -1,5 +1,3 @@
/* swap.S - thread context switching for ARM Cortex-M */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,10 +14,12 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
This module implements the routines necessary for thread context switching * @brief Thread context switching for ARM Cortex-M
on ARM Cortex-M3/M4 CPUs. *
* This module implements the routines necessary for thread context switching
* on ARM Cortex-M3/M4 CPUs.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

8
arch/arm/core/sys_fatal_error_handler.c
View file

@ -1,5 +1,3 @@
/* sysFatalErrorHandler - ARM Cortex-M system fatal error handler */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief ARM Cortex-M system fatal error handler
*
* This module provides the _SysFatalErrorHandler() routine for Cortex-M * This module provides the _SysFatalErrorHandler() routine for Cortex-M
* platforms. * platforms.
*/ */

8
arch/arm/core/task_abort.c
View file

@ -1,5 +1,3 @@
/* task_abort.c - ARM Cortex-M _TaskAbort() routine */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief ARM Cortex-M _TaskAbort() routine
*
* The ARM Cortex-M architecture provides its own _TaskAbort() to deal with * The ARM Cortex-M architecture provides its own _TaskAbort() to deal with
* different CPU modes (handler vs thread) when a task aborts. When its entry * different CPU modes (handler vs thread) when a task aborts. When its entry
* point returns or when it aborts itself, the CPU is in thread mode and must * point returns or when it aborts itself, the CPU is in thread mode and must

8
arch/arm/core/thread.c
View file

@ -1,5 +1,3 @@
/* thread.c - new thread creation for ARM Cortex-M */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief New thread creation for ARM Cortex-M
*
* Core nanokernel fiber related primitives for the ARM Cortex-M processor * Core nanokernel fiber related primitives for the ARM Cortex-M processor
* architecture. * architecture.
*/ */

8
arch/arm/include/cortex_m/exc.h
View file

@ -1,5 +1,3 @@
/* exc.h - exception/interrupt context helpers for Cortex-M CPUs */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Exception/interrupt context helpers for Cortex-M CPUs
*
* Exception/interrupt context helpers. * Exception/interrupt context helpers.
*/ */

8
arch/arm/include/cortex_m/stack.h
View file

@ -1,5 +1,3 @@
/* stack.h - stack helpers for Cortex-M CPUs */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Stack helpers for Cortex-M CPUs
*
* Stack helper functions. * Stack helper functions.
*/ */

2
arch/arm/include/kernel_event_logger_arch.h
View file

@ -14,7 +14,7 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* @file * @file
* @brief Kernel event logger support for ARM * @brief Kernel event logger support for ARM
*/ */

8
arch/arm/include/nano_private.h
View file

@ -1,5 +1,3 @@
/* nano_private.h - private nanokernel definitions (ARM) */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Private nanokernel definitions (ARM)
*
* This file contains private nanokernel structures definitions and various * This file contains private nanokernel structures definitions and various
* other definitions for the ARM Cortex-M3 processor architecture. * other definitions for the ARM Cortex-M3 processor architecture.
* *

8
arch/arm/include/start_task_arch.h
View file

@ -1,5 +1,3 @@
/* start_task.h - ARM nanokernel declarations to start a task */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief ARM nanokernel declarations to start a task
*
* ARM-specific parts of start_task(). * ARM-specific parts of start_task().
* *
* Currently empty, only here for abstraction. * Currently empty, only here for abstraction.

8
arch/arm/platforms/fsl_frdm_k64f/board.h
View file

@ -1,5 +1,3 @@
/* board.h - board configuration macros for the fsl_frdm_k64f platform */
/* /*
* Copyright (c) 2014-2015 Wind River Systems, Inc. * Copyright (c) 2014-2015 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Board configuration macros for the fsl_frdm_k64f platform
*
* This header file is used to specify and describe board-level aspects for the * This header file is used to specify and describe board-level aspects for the
* 'fsl_frdm_k64f' platform. * 'fsl_frdm_k64f' platform.
*/ */

8
arch/arm/platforms/fsl_frdm_k64f/irq_vector_table.c
View file

@ -1,5 +1,3 @@
/* irq_vector_table.c - IRQ part of vector table */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief IRQ part of vector table
*
* This file contains the IRQ part of the vector table. It is meant to be used * This file contains the IRQ part of the vector table. It is meant to be used
* for one of two cases: * for one of two cases:
* *

10
arch/arm/platforms/fsl_frdm_k64f/linker.cmd
View file

@ -1,5 +1,3 @@
/* linker.cmd - Linker command/script file */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,9 +14,11 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
This is the linker script for both standard images and XIP images. * @brief Linker command/script file
*
* This is the linker script for both standard images and XIP images.
*/ */
/* /*

18
arch/arm/platforms/fsl_frdm_k64f/nmi_on_reset.S
View file

@ -1,5 +1,3 @@
/* nmi_on_reset.S - default basic NMI handler before the kernel is up */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,13 +14,15 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
Provide a default handler for NMI before the system is up. The default action * @brief Default basic NMI handler before the kernel is up
is to hard hang, sleeping. *
* Provide a default handler for NMI before the system is up. The default action
This might be preferable than rebooting to help debugging, or because * is to hard hang, sleeping.
rebooting might trigger the exact same problem over and over. *
* This might be preferable than rebooting to help debugging, or because
* rebooting might trigger the exact same problem over and over.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

8
arch/arm/platforms/fsl_frdm_k64f/system.c
View file

@ -1,5 +1,3 @@
/* system.c - system/hardware module for fsl_frdm_k64f platform */
/* /*
* Copyright (c) 2014-2015 Wind River Systems, Inc. * Copyright (c) 2014-2015 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief System/hardware module for fsl_frdm_k64f platform
*
* This module provides routines to initialize and support board-level * This module provides routines to initialize and support board-level
* hardware for the fsl_frdm_k64f platform. * hardware for the fsl_frdm_k64f platform.
*/ */

10
arch/arm/platforms/fsl_frdm_k64f/wdog.S
View file

@ -1,5 +1,3 @@
/* wdog.S - watchdog initialization for fsl_frdm_k64f platform */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,9 +14,11 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
This module initializes the watchdog for the fsl_frdm_k64f platform. * @brief Watchdog initialization for fsl_frdm_k64f platform
*
* This module initializes the watchdog for the fsl_frdm_k64f platform.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

8
arch/arm/platforms/qemu_arm/board.h
View file

@ -1,5 +1,3 @@
/* board.h - board configuration macros for the QEMU for arm platform */
/* /*
* Copyright (c) 2013-2015 Wind River Systems, Inc. * Copyright (c) 2013-2015 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Board configuration macros for the QEMU for arm platform
*
* This header file is used to specify and describe board-level aspects for * This header file is used to specify and describe board-level aspects for
* the 'QEMU' platform. * the 'QEMU' platform.
*/ */

8
arch/arm/platforms/qemu_arm/irq_vector_table.c
View file

@ -1,5 +1,3 @@
/* irq_vector_table.c - IRQ part of vector table */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief IRQ part of vector table
*
* This file contains the IRQ part of the vector table. It is meant to be used * This file contains the IRQ part of the vector table. It is meant to be used
* for one of two cases: * for one of two cases:
* *

18
arch/arm/platforms/qemu_arm/nmi_on_reset.S
View file

@ -1,5 +1,3 @@
/* nmi_on_reset.S - default basic NMI handler before the kernel is up */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,13 +14,15 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
Provide a default handler for NMI before the system is up. The default action * @brief Default basic NMI handler before the kernel is up
is to hard hang, sleeping. *
* Provide a default handler for NMI before the system is up. The default action
This might be preferable than rebooting to help debugging, or because * is to hard hang, sleeping.
rebooting might trigger the exact same problem over and over. *
* This might be preferable than rebooting to help debugging, or because
* rebooting might trigger the exact same problem over and over.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

8
arch/arm/platforms/qemu_arm/scp.c
View file

@ -1,5 +1,3 @@
/* scp.c - TI LM3S6965 System Control Peripherals interface */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief TI LM3S6965 System Control Peripherals interface
*
* *
* Library for controlling target-specific devices present in the 0x400fe000 * Library for controlling target-specific devices present in the 0x400fe000
* peripherals memory region. * peripherals memory region.

8
arch/arm/platforms/qemu_arm/scp.h
View file

@ -1,5 +1,3 @@
/* scp.h - TI LM3S6965 System Control Peripherals interface */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief TI LM3S6965 System Control Peripherals interface
*
* This module defines the System Control Peripheral Registers for TI LM3S6965 * This module defines the System Control Peripheral Registers for TI LM3S6965
* processor. The registers defined are in region 0x400fe000. * processor. The registers defined are in region 0x400fe000.
* *

8
arch/arm/platforms/qemu_arm/system.c
View file

@ -1,5 +1,3 @@
/* system.c - system/hardware module for ti_lm3s6965 platform */
/* /*
* Copyright (c) 2013-2015 Wind River Systems, Inc. * Copyright (c) 2013-2015 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief System/hardware module for ti_lm3s6965 platform
*
* This module provides routines to initialize and support board-level hardware * This module provides routines to initialize and support board-level hardware
* for the ti_lm3s6965 platform. * for the ti_lm3s6965 platform.
*/ */

5
arch/x86/core/atomic.c
View file

@ -15,9 +15,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* @file Atomic ops for x86 * @file Atomic ops for x86
* DESCRIPTION This module provides the atomic operators for IA-32 *
* This module provides the atomic operators for IA-32
* architectures on platforms that support the LOCK prefix instruction. * architectures on platforms that support the LOCK prefix instruction.
* *
* The atomic operations are guaranteed to be atomic with respect * The atomic operations are guaranteed to be atomic with respect

8
arch/x86/core/cache.c
View file

@ -1,5 +1,3 @@
/* cache.c - cache manipulation */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -15,8 +13,10 @@
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Cache manipulation
*
* This module contains functions for manipulation caches. * This module contains functions for manipulation caches.
*/ */

10
arch/x86/core/cache_s.S
View file

@ -1,5 +1,3 @@
/* cache_s.S - cache manipulation */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -15,9 +13,11 @@
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
This module contains functions for manipulating caches. * @brief Cache manipulation
*
* This module contains functions for manipulating caches.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

14
arch/x86/core/crt0.S
View file

@ -1,5 +1,3 @@
/* crt0.S - crt0 module for the IA-32 boards */
/* /*
* Copyright (c) 2010-2015 Wind River Systems, Inc. * Copyright (c) 2010-2015 Wind River Systems, Inc.
* *
@ -15,11 +13,13 @@
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
This module contains the initial code executed by the Zephyr Kernel ELF image * @brief Crt0 module for the IA-32 boards
after having been loaded into RAM. *
*/ * This module contains the initial code executed by the Zephyr Kernel ELF image
* after having been loaded into RAM.
*/
#define _ASMLANGUAGE #define _ASMLANGUAGE

12
arch/x86/core/driver_static_irq_stubs.S
View file

@ -1,5 +1,3 @@
/* driver_static_irq_stubs.S - interrupt stubs */
/* /*
* Copyright (c) 2012-2015, Wind River Systems, Inc. * Copyright (c) 2012-2015, Wind River Systems, Inc.
* *
@ -16,10 +14,12 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
This module contains the static interrupt stubs for the various drivers employed * @brief Interrupt stubs
by x86 platforms. *
* This module contains the static interrupt stubs for the various drivers employed
* by x86 platforms.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

8
arch/x86/core/excconnect.c
View file

@ -1,5 +1,3 @@
/* excconnect.c - exception management support for IA-32 arch */
/* /*
* Copyright (c) 2010-2014 Wind River Systems, Inc. * Copyright (c) 2010-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Exception management support for IA-32 arch
*
* This module provides routines to manage exceptions (synchronous interrupts) * This module provides routines to manage exceptions (synchronous interrupts)
* on the IA-32 architecture. * on the IA-32 architecture.
* *

8
arch/x86/core/fatal.c
View file

@ -1,5 +1,3 @@
/* fatal.c - nanokernel fatal error handler */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Nanokernel fatal error handler
*
* This module provides the _NanoFatalErrorHandler() routine. * This module provides the _NanoFatalErrorHandler() routine.
*/ */

8
arch/x86/core/float.c
View file

@ -1,5 +1,3 @@
/* float.c - floating point resource sharing routines */
/* /*
* Copyright (c) 2010-2014 Wind River Systems, Inc. * Copyright (c) 2010-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Floating point resource sharing routines
*
* This module allows multiple tasks and fibers to safely share the system's * This module allows multiple tasks and fibers to safely share the system's
* floating point resources, by allowing the system to save FPU state * floating point resources, by allowing the system to save FPU state
* information in a task or fiber's stack region when a pre-emptive context * information in a task or fiber's stack region when a pre-emptive context

8
arch/x86/core/gdt.c
View file

@ -1,5 +1,3 @@
/* gdt.c - Global Descriptor Table support */
/* /*
* Copyright (c) 2011-2014 Wind River Systems, Inc. * Copyright (c) 2011-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Global Descriptor Table support
*
* This module contains routines for updating the global descriptor table (GDT) * This module contains routines for updating the global descriptor table (GDT)
* for the IA-32 architecture. * for the IA-32 architecture.
*/ */

16
arch/x86/core/i386_sysV_abi/excstub.S
View file

@ -1,5 +1,3 @@
/* excstub.S - exception management support for IA-32 architecture */
/* /*
* Copyright (c) 2011-2015 Wind River Systems, Inc. * Copyright (c) 2011-2015 Wind River Systems, Inc.
* *
@ -16,12 +14,14 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
This module implements assembly routines to manage exceptions (synchronous * @brief Exception management support for IA-32 architecture
interrupts) on the Intel IA-32 architecture. More specifically, *
exceptions are implemented in this module. The stubs are invoked when entering * This module implements assembly routines to manage exceptions (synchronous
and exiting a C exception handler. * interrupts) on the Intel IA-32 architecture. More specifically,
* exceptions are implemented in this module. The stubs are invoked when entering
* and exiting a C exception handler.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

18
arch/x86/core/i386_sysV_abi/intstub.S
View file

@ -1,5 +1,3 @@
/* intstub.S - interrupt management support for IA-32 architecture */
/* /*
* Copyright (c) 2010-2014 Wind River Systems, Inc. * Copyright (c) 2010-2014 Wind River Systems, Inc.
* *
@ -16,13 +14,15 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
This module implements assembly routines to manage interrupts on * @brief Interrupt management support for IA-32 architecture
the Intel IA-32 architecture. More specifically, the interrupt (asynchronous *
exception) stubs are implemented in this module. The stubs are invoked when * This module implements assembly routines to manage interrupts on
entering and exiting a C interrupt handler. * the Intel IA-32 architecture. More specifically, the interrupt (asynchronous
*/ * exception) stubs are implemented in this module. The stubs are invoked when
* entering and exiting a C interrupt handler.
*/
#define _ASMLANGUAGE #define _ASMLANGUAGE

22
arch/x86/core/i386_sysV_abi/swap.S
View file

@ -1,5 +1,3 @@
/* swap.S - nanokernel swapper code for IA-32 */
/* /*
* Copyright (c) 2010-2015 Wind River Systems, Inc. * Copyright (c) 2010-2015 Wind River Systems, Inc.
* *
@ -16,15 +14,17 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
This module implements the _Swap() routine for the IA-32 architecture. * @brief Nanokernel swapper code for IA-32
*
Note that the file include/nanokernel/x86/swapstk.h defines * This module implements the _Swap() routine for the IA-32 architecture.
a representation of the save stack frame generated by _Swap() in order *
to generate offsets (in the form of absolute symbols) for consumption by * Note that the file include/nanokernel/x86/swapstk.h defines
host tools. Please update swapstk.h if changing the structure of the * a representation of the save stack frame generated by _Swap() in order
save frame on the stack. * to generate offsets (in the form of absolute symbols) for consumption by
* host tools. Please update swapstk.h if changing the structure of the
* save frame on the stack.
*/ */
#define _ASMLANGUAGE #define _ASMLANGUAGE

8
arch/x86/core/i386_sysV_abi/thread.c
View file

@ -1,5 +1,3 @@
/* thread.c - nanokernel thread support primitives */
/* /*
* Copyright (c) 2010-2015 Wind River Systems, Inc. * Copyright (c) 2010-2015 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Nanokernel thread support primitives
*
* This module provides core nanokernel fiber related primitives for the IA-32 * This module provides core nanokernel fiber related primitives for the IA-32
* processor architecture. * processor architecture.
*/ */

8
arch/x86/core/intconnect.c
View file

@ -1,5 +1,3 @@
/* intconnect.c - interrupt management support for IA-32 arch */
/* /*
* Copyright (c) 2010-2014 Wind River Systems, Inc. * Copyright (c) 2010-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Interrupt management support for IA-32 arch
*
* This module provides routines to manage asynchronous interrupts * This module provides routines to manage asynchronous interrupts
* on the IA-32 architecture. * on the IA-32 architecture.
* *

8
arch/x86/core/offsets/offsets.c
View file

@ -1,5 +1,3 @@
/* offsets.c - nanokernel structure member offset definition file */
/* /*
* Copyright (c) 2010-2014 Wind River Systems, Inc. * Copyright (c) 2010-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Nanokernel structure member offset definition file
*
* This module is responsible for the generation of the absolute symbols whose * This module is responsible for the generation of the absolute symbols whose
* value represents the member offsets for various IA-32 nanokernel structures. * value represents the member offsets for various IA-32 nanokernel structures.
* *

8
arch/x86/core/strtask.c
View file

@ -1,5 +1,3 @@
/* strtask.c - Intel nanokernel APIs to start a task */
/* /*
* Copyright (c) 2010-2014 Wind River Systems, Inc. * Copyright (c) 2010-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Intel nanokernel APIs to start a task
*
* Intel-specific parts of start_task(). Only FP functionality currently. * Intel-specific parts of start_task(). Only FP functionality currently.
*/ */

8
arch/x86/core/sys_fatal_error_handler.c
View file

@ -1,5 +1,3 @@
/* sysFatalErrorHandler - common system fatal error handler */
/* /*
* Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2013-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Common system fatal error handler
*
* This module provides the _SysFatalErrorHandler() routine which is common to * This module provides the _SysFatalErrorHandler() routine which is common to
* supported platforms. * supported platforms.
*/ */

8
arch/x86/include/gdt.h
View file

@ -1,5 +1,3 @@
/* gdt.h - IA-32 Global Descriptor Table (GDT) definitions */
/* /*
* Copyright (c) 2011-2012, 2014 Wind River Systems, Inc. * Copyright (c) 2011-2012, 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief IA-32 Global Descriptor Table (GDT) definitions
*
* This file provides definitions for the Global Descriptor Table (GDT) for the * This file provides definitions for the Global Descriptor Table (GDT) for the
* IA-32 architecture. * IA-32 architecture.
*/ */

8
arch/x86/include/idtEnt.h
View file

@ -1,5 +1,3 @@
/* idtEnt.h - IA-32 IDT Entry code */
/* /*
* Copyright (c) 2012-2014, Wind River Systems, Inc. * Copyright (c) 2012-2014, Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief IA-32 IDT Entry code
*
* This header file provides code for constructing an IA-32 interrupt * This header file provides code for constructing an IA-32 interrupt
* descriptor. * descriptor.
*/ */

2
arch/x86/include/kernel_event_logger_arch.h
View file

@ -14,7 +14,7 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* @file * @file
* @brief Kernel event logger support for x86 * @brief Kernel event logger support for x86
*/ */

8
arch/x86/include/nano_private.h
View file

@ -1,5 +1,3 @@
/* nano_private.h - private nanokernel definitions (IA-32) */
/* /*
* Copyright (c) 2010-2014 Wind River Systems, Inc. * Copyright (c) 2010-2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Private nanokernel definitions (IA-32)
*
* This file contains private nanokernel structures definitions and various * This file contains private nanokernel structures definitions and various
* other definitions for the Intel Architecture 32 bit (IA-32) processor * other definitions for the Intel Architecture 32 bit (IA-32) processor
* architecture. * architecture.

8
arch/x86/include/start_task_arch.h
View file

@ -1,5 +1,3 @@
/* start_task.h - Intel nanokernel declarations to start a task */
/* /*
* Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Intel nanokernel declarations to start a task
*
* Intel-specific parts of start_task(). Only FP functionality currently. * Intel-specific parts of start_task(). Only FP functionality currently.
*/ */

8
arch/x86/include/swapstk.h
View file

@ -1,5 +1,3 @@
/* swapstk.h - stack frame created by swap (IA-32) */
/* /*
* Copyright (c) 2011-2012, 2014 Wind River Systems, Inc. * Copyright (c) 2011-2012, 2014 Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Stack frame created by swap (IA-32)
*
* This file details the stack frame generated by _Swap() when it saves a task * This file details the stack frame generated by _Swap() when it saves a task
* or fiber's context. This is specific to the IA-32 processor architecture. * or fiber's context. This is specific to the IA-32 processor architecture.
* *

8
arch/x86/platforms/galileo/board.h
View file

@ -1,5 +1,3 @@
/* board.h - board configuration macros for the galileo platform */
/* /*
* Copyright (c) 2013-2015, Wind River Systems, Inc. * Copyright (c) 2013-2015, Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Board configuration macros for the galileo platform
*
* This header file is used to specify and describe board-level aspects for * This header file is used to specify and describe board-level aspects for
* the 'galileo' platform. * the 'galileo' platform.
*/ */

8
arch/x86/platforms/galileo/galileo.c
View file

@ -1,5 +1,3 @@
/* galileo.c - system/hardware module for the galileo platform */
/* /*
* Copyright (c) 2013-2015, Wind River Systems, Inc. * Copyright (c) 2013-2015, Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief System/hardware module for the galileo platform
*
* This module provides routines to initialize and support board-level hardware * This module provides routines to initialize and support board-level hardware
* for the galileo platform. * for the galileo platform.
* *

10
arch/x86/platforms/galileo/linker.cmd
View file

@ -1,5 +1,3 @@
/* linker.cmd - Linker command/script file */
/* /*
* Copyright (c) 2011-2014, Wind River Systems, Inc. * Copyright (c) 2011-2014, Wind River Systems, Inc.
* *
@ -16,9 +14,11 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
This is the linker script for both standard images and XIP images. * @brief Linker command/script file
*
* This is the linker script for both standard images and XIP images.
*/ */
#include <autoconf.h> #include <autoconf.h>

8
arch/x86/platforms/ia32/board.h
View file

@ -1,5 +1,3 @@
/* board.h - board configuration macros for the ia32 platform */
/* /*
* Copyright (c) 2010-2015, Wind River Systems, Inc. * Copyright (c) 2010-2015, Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Board configuration macros for the ia32 platform
*
* This header file is used to specify and describe board-level aspects for * This header file is used to specify and describe board-level aspects for
* the 'ia32' platform. * the 'ia32' platform.
*/ */

8
arch/x86/platforms/ia32/ia32.c
View file

@ -1,5 +1,3 @@
/* ia32.c - system/hardware module for the ia32 platform */
/* /*
* Copyright (c) 2011-2015, Wind River Systems, Inc. * Copyright (c) 2011-2015, Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief System/hardware module for the ia32 platform
*
* This module provides routines to initialize and support board-level hardware * This module provides routines to initialize and support board-level hardware
* for the ia32 platform. * for the ia32 platform.
*/ */

10
arch/x86/platforms/ia32/linker.cmd
View file

@ -1,5 +1,3 @@
/* linker.cmd - Linker command/script file */
/* /*
* Copyright (c) 2011-2014, Wind River Systems, Inc. * Copyright (c) 2011-2014, Wind River Systems, Inc.
* *
@ -16,9 +14,11 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
This is the linker script for both standard images and XIP images. * @brief Linker command/script file
*
* This is the linker script for both standard images and XIP images.
*/ */
#include <autoconf.h> #include <autoconf.h>

8
arch/x86/platforms/ia32_pci/board.h
View file

@ -1,5 +1,3 @@
/* board.h - board configuration macros for the ia32_pci platform */
/* /*
* Copyright (c) 2013-2015, Wind River Systems, Inc. * Copyright (c) 2013-2015, Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief Board configuration macros for the ia32_pci platform
*
* This header file is used to specify and describe board-level aspects for * This header file is used to specify and describe board-level aspects for
* the 'ia32_pci' platform. * the 'ia32_pci' platform.
*/ */

8
arch/x86/platforms/ia32_pci/ia32_pci.c
View file

@ -1,5 +1,3 @@
/* ia32_pci.c - system/hardware module for the ia32_pci platform */
/* /*
* Copyright (c) 2013-2015, Wind River Systems, Inc. * Copyright (c) 2013-2015, Wind River Systems, Inc.
* *
@ -16,8 +14,10 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
* DESCRIPTION * @file
* @brief System/hardware module for the ia32_pci platform
*
* This module provides routines to initialize and support board-level hardware * This module provides routines to initialize and support board-level hardware
* for the ia32_pci platform. * for the ia32_pci platform.
* *

10
arch/x86/platforms/ia32_pci/linker.cmd
View file

@ -1,5 +1,3 @@
/* linker.cmd - Linker command/script file */
/* /*
* Copyright (c) 2011-2014, Wind River Systems, Inc. * Copyright (c) 2011-2014, Wind River Systems, Inc.
* *
@ -16,9 +14,11 @@
* limitations under the License. * limitations under the License.
*/ */
/* /**
DESCRIPTION * @file
This is the linker script for both standard images and XIP images. * @brief Linker command/script file
*
* This is the linker script for both standard images and XIP images.
*/ */
#include <autoconf.h> #include <autoconf.h>

Some files were not shown because too many files have changed in this diff Show more