Fixed file description and applied doxygen style

Removed old style file description and documnetation and apply
doxygen synatx.

Change-Id: I3ac9f06d4f574bf3c79c6f6044cec3a7e2f6e4c8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

arch/arm/core/atomic.S

@@ -1,5 +1,3 @@
-/* armAtomic.S - ARM atomic operations library */
-
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
  *
@@ -16,11 +14,13 @@
  * limitations under the License.
  */
 
-/*
-DESCRIPTION
-This library provides routines to perform a number of atomic operations
-on a memory location: add, subtract, increment, decrement, bitwise OR,
-bitwise NOR, bitwise AND, bitwise NAND, set, clear and compare-and-swap.
+/**
+ * @file
+ * @brief ARM atomic operations library
+ *
+ * This library provides routines to perform a number of atomic operations
+ * on a memory location: add, subtract, increment, decrement, bitwise OR,
+ * bitwise NOR, bitwise AND, bitwise NAND, set, clear and compare-and-swap.
  */
 
 #define _ASMLANGUAGE

arch/arm/core/cortex_m/nmi.c

@@ -1,5 +1,3 @@
-/* nmi.c - NMI handler infrastructure */
-
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
  *
@@ -16,8 +14,10 @@
  * limitations under the License.
  */
 
-/*
- * DESCRIPTION
+/**
+ * @file
+ * @brief NMI handler infrastructure
+ *
  * Provides a boot time handler that simply hangs in a sleep loop, and a run
  * time handler that resets the CPU. Also provides a mechanism for hooking a
  * custom run time handler.

arch/arm/core/cortex_m/prep_c.c

@@ -1,5 +1,3 @@
-/* prep_c.c - full C support initialization */
-
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
  *
@@ -16,8 +14,10 @@
  * limitations under the License.
  */
 
-/*
- * DESCRIPTION
+/**
+ * @file
+ * @brief Full C support initialization
+ *
  *
  * Initialization of full C support: zero the .bss, copy the .data if XIP,
  * call _Cstart().

arch/arm/core/cortex_m/reset.S

@@ -1,5 +1,3 @@
-/* reset_s.S - reset handler */
-
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
  *
@@ -16,9 +14,11 @@
  * limitations under the License.
  */
 
-/*
-DESCRIPTION
-Reset handler that prepares the system for running C code.
+/**
+ * @file
+ * @brief Reset handler
+ *
+ * Reset handler that prepares the system for running C code.
  */
 
 #define _ASMLANGUAGE

arch/arm/core/cortex_m/scb.c

@@ -1,5 +1,3 @@
-/* scb.h - ARM CORTEX-M3 System Control Block interface */
-
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
  *
@@ -16,8 +14,10 @@
  * limitations under the License.
  */
 
-/*
- * DESCRIPTION
+/**
+ * @file
+ * @brief ARM CORTEX-M3 System Control Block interface
+ *
  *
  * Most of the SCB interface consists of simple bit-flipping methods, and is
  * implemented as inline functions in scb.h. This module thus contains only data

arch/arm/core/cortex_m/scs.c

@@ -1,5 +1,3 @@
-/* scs.c - ARM CORTEX-M Series System Control Space */
-
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
  *
@@ -16,8 +14,10 @@
  * limitations under the License.
  */
 
-/*
- * DESCRIPTION
+/**
+ * @file
+ * @brief ARM CORTEX-M Series System Control Space
+ *
  * Most of the SCS interface consists of simple bit-flipping methods, and is
  * implemented as inline functions in scs.h. This module thus contains only data
  * definitions and more complex routines, if needed.

arch/arm/core/cortex_m/sw_isr_table.S

@@ -1,5 +1,3 @@
-/* ISR table for static ISR declarations for ARM */
-
 /*
  * Copyright (c) 2015 Wind River Systems, Inc.
  *
@@ -16,9 +14,11 @@
  * limitations under the License.
  */
 
-/*
-DESCRIPTION
-Software ISR table for ARM
+/**
+ * @file
+ * @brief ISR table for static ISR declarations for ARM
+ *
+ * Software ISR table for ARM
  */
 
 #define _ASMLANGUAGE

arch/arm/core/cortex_m/vector_table.S

@@ -1,5 +1,3 @@
-/* vector_table.S - populated vector table in ROM */
-
 /*
  * Copyright (c) 2013-2015 Wind River Systems, Inc.
  *
@@ -16,14 +14,16 @@
  * limitations under the License.
  */
 
-/*
-DESCRIPTION
-Vector table in ROM for starting system. The reset vector is the system entry
-point, ie. the first instruction executed.
-
-The table is populated with all the system exception handlers. The NMI vector
-must be populated with a valid handler since it can happen at any time. The
-rest should not be triggered until the kernel is ready to handle them.
+/**
+ * @file
+ * @brief Populated vector table in ROM
+ *
+ * Vector table in ROM for starting system. The reset vector is the system entry
+ * point, ie. the first instruction executed.
+ *
+ * The table is populated with all the system exception handlers. The NMI vector
+ * must be populated with a valid handler since it can happen at any time. The
+ * rest should not be triggered until the kernel is ready to handle them.
  */
 
 #define _ASMLANGUAGE

arch/arm/core/cortex_m/vector_table.h

@@ -1,5 +1,3 @@
-/* vector_table.h - definitions for the boot vector table */
-
 /*
  * Copyright (c) 2013-2015 Wind River Systems, Inc.
  *
@@ -16,8 +14,10 @@
  * limitations under the License.
  */
 
-/*
- * DESCRIPTION
+/**
+ * @file
+ * @brief Definitions for the boot vector table
+ *
  *
  * Definitions for the boot vector table.
  *

arch/arm/core/cpu_idle.S

@@ -1,5 +1,3 @@
-/* cpu_idle.S - ARM CORTEX-M3 power management */
-
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
  *
@@ -16,8 +14,10 @@
  * limitations under the License.
  */
 
-/*
-DESCRIPTION
+/**
+ * @file
+ * @brief ARM CORTEX-M3 power management
+ *
  */
 
 #define _ASMLANGUAGE

arch/arm/core/exc_exit.S

@@ -1,5 +1,3 @@
-/* exc_exit.S - ARM CORTEX-M3 exception/interrupt exit API */
-
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
  *
@@ -16,12 +14,14 @@
  * limitations under the License.
  */
 
-/*
-DESCRIPTION
-
-Provides functions for performing kernel handling when exiting exceptions or
-interrupts that are installed directly in the vector table (i.e. that are not
-wrapped around by _isr_wrapper()).
+/**
+ * @file
+ * @brief ARM CORTEX-M3 exception/interrupt exit API
+ *
+ *
+ * Provides functions for performing kernel handling when exiting exceptions or
+ * interrupts that are installed directly in the vector table (i.e. that are not
+ * wrapped around by _isr_wrapper()).
  */
 
 #define _ASMLANGUAGE

arch/arm/core/fatal.c

@@ -1,5 +1,3 @@
-/* fatal.c - nanokernel fatal error handler for ARM Cortex-M */
-
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
@@ -16,8 +14,10 @@
  * limitations under the License.
  */
 
-/*
- * DESCRIPTION
+/**
+ * @file
+ * @brief Nanokernel fatal error handler for ARM Cortex-M
+ *
  * This module provides the _NanoFatalErrorHandler() routine for ARM Cortex-M.
  */
 

arch/arm/core/fault.c

@@ -1,5 +1,3 @@
-/* fault.c - common fault handler for ARM Cortex-M */
-
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
@@ -16,8 +14,10 @@
  * limitations under the License.
  */
 
-/*
- * DESCRIPTION
+/**
+ * @file
+ * @brief Common fault handler for ARM Cortex-M
+ *
  * Common fault handler for ARM Cortex-M processors.
  */
 

arch/arm/core/fault_s.S

@@ -1,5 +1,3 @@
-/* fault_s.S - fault handlers for ARM Cortex-M */
-
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
  *
@@ -16,9 +14,11 @@
  * limitations under the License.
  */
 
-/*
-DESCRIPTION
-Fault handlers for ARM Cortex-M processors.
+/**
+ * @file
+ * @brief Fault handlers for ARM Cortex-M
+ *
+ * Fault handlers for ARM Cortex-M processors.
  */
 
 #define _ASMLANGUAGE

arch/arm/core/fiber_abort.c

@@ -1,5 +1,3 @@
-/* fiber_abort.c - ARM Cortex-M fiber_abort() routine */
-
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
@@ -16,8 +14,10 @@
  * limitations under the License.
  */
 
-/*
- * DESCRIPTION
+/**
+ * @file
+ * @brief ARM Cortex-M fiber_abort() routine
+ *
  * The ARM Cortex-M architecture provides its own fiber_abort() to deal with
  * different CPU modes (handler vs thread) when a fiber aborts. When its entry
  * point returns or when it aborts itself, the CPU is in thread mode and must

arch/arm/core/gdb_stub.S

@@ -1,5 +1,3 @@
-/* gdb_stub.S - extra work performed upon exception entry/exit for GDB */
-
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
@@ -16,15 +14,17 @@
  * limitations under the License.
  */
 
-/*
-DESCRIPTION
-
-Prep work done when entering exceptions consists of saving the callee-saved
-registers before they get used by exception handlers, and recording the fact
-that we are running in an exception.
-
-Upon exception exit, it must be recorded that the task is not in an exception
-anymore.
+/**
+ * @file
+ * @brief Extra work performed upon exception entry/exit for GDB
+ *
+ *
+ * Prep work done when entering exceptions consists of saving the callee-saved
+ * registers before they get used by exception handlers, and recording the fact
+ * that we are running in an exception.
+ *
+ * Upon exception exit, it must be recorded that the task is not in an exception
+ * anymore.
  */
 
 #define _ASMLANGUAGE

arch/arm/core/gdb_stub_irq_vector_table.c

@@ -1,5 +1,3 @@
-/* gdb_stub_irq_vector_table.c - stubs for IRQ part of vector table */
-
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
@@ -16,8 +14,10 @@
  * limitations under the License.
  */
 
-/*
- * DESCRIPTION
+/**
+ * @file
+ * @brief Stubs for IRQ part of vector table
+ *
  * When GDB is enabled, the static IRQ vector table needs to install the
  * _irq_vector_table_entry_with_gdb_stub stub to do some work before calling the
  * user-installed ISRs.

arch/arm/core/irq_init.c

@@ -1,5 +1,3 @@
-/* irq_init.c - ARM Cortex-M interrupt initialization */
-
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
@@ -16,8 +14,10 @@
  * limitations under the License.
  */
 
-/*
- * DESCRIPTION
+/**
+ * @file
+ * @brief ARM Cortex-M interrupt initialization
+ *
  * The ARM Cortex-M architecture provides its own fiber_abort() to deal with
  * different CPU modes (handler vs thread) when a fiber aborts. When its entry
  * point returns or when it aborts itself, the CPU is in thread mode and must

arch/arm/core/irq_manage.c

@@ -1,5 +1,3 @@
-/* irq_manage.c - ARM CORTEX-M3 interrupt management */
-
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
  *
@@ -16,8 +14,10 @@
  * limitations under the License.
  */
 
-/*
- * DESCRIPTION
+/**
+ * @file
+ * @brief ARM CORTEX-M3 interrupt management
+ *
  *
  * Interrupt management: enabling/disabling and dynamic ISR
  * connecting/replacing.  SW_ISR_TABLE_DYNAMIC has to be enabled for

arch/arm/core/isr_wrapper.S

@@ -1,5 +1,3 @@
-/* isr_wrapper.S - ARM CORTEX-M3 wrapper for ISRs with parameter  */
-
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
  *
@@ -16,11 +14,12 @@
  * limitations under the License.
  */
 
-/*
-DESCRIPTION
-
-Wrapper installed in vector table for handling dynamic interrupts that accept
-a parameter.
+/**
+ * @file
+ * @brief ARM CORTEX-M3 wrapper for ISRs with parameter
+ *
+ * Wrapper installed in vector table for handling dynamic interrupts that accept
+ * a parameter.
  */
 
 #define _ASMLANGUAGE

arch/arm/core/offsets/offsets.c

@@ -1,5 +1,3 @@
-/* offsets.c - ARM nano kernel structure member offset definition file */
-
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
  *
@@ -16,8 +14,10 @@
  * limitations under the License.
  */
 
-/*
- * DESCRIPTION
+/**
+ * @file
+ * @brief ARM nano kernel structure member offset definition file
+ *
  * This module is responsible for the generation of the absolute symbols whose
  * value represents the member offsets for various ARM nanokernel
  * structures.

arch/arm/core/swap.S

@@ -1,5 +1,3 @@
-/* swap.S - thread context switching for ARM Cortex-M */
-
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
  *
@@ -16,10 +14,12 @@
  * limitations under the License.
  */
 
-/*
-DESCRIPTION
-This module implements the routines necessary for thread context switching
-on ARM Cortex-M3/M4 CPUs.
+/**
+ * @file
+ * @brief Thread context switching for ARM Cortex-M
+ *
+ * This module implements the routines necessary for thread context switching
+ * on ARM Cortex-M3/M4 CPUs.
  */
 
 #define _ASMLANGUAGE

arch/arm/core/sys_fatal_error_handler.c

@@ -1,5 +1,3 @@
-/* sysFatalErrorHandler - ARM Cortex-M system fatal error handler */
-
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
@@ -16,8 +14,10 @@
  * limitations under the License.
  */
 
-/*
- * DESCRIPTION
+/**
+ * @file
+ * @brief ARM Cortex-M system fatal error handler
+ *
  * This module provides the _SysFatalErrorHandler() routine for Cortex-M
  * platforms.
  */

arch/arm/core/task_abort.c

@@ -1,5 +1,3 @@
-/* task_abort.c - ARM Cortex-M _TaskAbort() routine */
-
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
@@ -16,8 +14,10 @@
  * limitations under the License.
  */
 
-/*
- * DESCRIPTION
+/**
+ * @file
+ * @brief ARM Cortex-M _TaskAbort() routine
+ *
  * The ARM Cortex-M architecture provides its own _TaskAbort() to deal with
  * different CPU modes (handler vs thread) when a task aborts. When its entry
  * point returns or when it aborts itself, the CPU is in thread mode and must

arch/arm/core/thread.c

@@ -1,5 +1,3 @@
-/* thread.c - new thread creation for ARM Cortex-M */
-
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
  *
@@ -16,8 +14,10 @@
  * limitations under the License.
  */
 
-/*
- * DESCRIPTION
+/**
+ * @file
+ * @brief New thread creation for ARM Cortex-M
+ *
  * Core nanokernel fiber related primitives for the ARM Cortex-M processor
  * architecture.
  */