diff --git a/boards/adi/max32666evkit/Kconfig.max32666evkit b/boards/adi/max32666evkit/Kconfig.max32666evkit new file mode 100644 index 00000000000..a648082e506 --- /dev/null +++ b/boards/adi/max32666evkit/Kconfig.max32666evkit @@ -0,0 +1,7 @@ +# MAX32666EVKIT boards configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32666EVKIT + select SOC_MAX32666_CPU0 if BOARD_MAX32666EVKIT_MAX32666_CPU0 diff --git a/boards/adi/max32666evkit/board.cmake b/boards/adi/max32666evkit/board.cmake new file mode 100644 index 00000000000..80033d85bdc --- /dev/null +++ b/boards/adi/max32666evkit/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max32665.cfg]") +board_runner_args(jlink "--device=MAX32666" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32666evkit/board.yml b/boards/adi/max32666evkit/board.yml new file mode 100644 index 00000000000..5d1beff7716 --- /dev/null +++ b/boards/adi/max32666evkit/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32666evkit + vendor: adi + socs: + - name: max32666 diff --git a/boards/adi/max32666evkit/doc/img/max32666evkit.webp b/boards/adi/max32666evkit/doc/img/max32666evkit.webp new file mode 100644 index 00000000000..6eed641e252 Binary files /dev/null and b/boards/adi/max32666evkit/doc/img/max32666evkit.webp differ diff --git a/boards/adi/max32666evkit/doc/index.rst b/boards/adi/max32666evkit/doc/index.rst new file mode 100644 index 00000000000..7177f1eeb71 --- /dev/null +++ b/boards/adi/max32666evkit/doc/index.rst @@ -0,0 +1,311 @@ +.. _max32666evkit: + +MAX32666EVKIT +############# + +Overview +******** +The MAX32666EVKIT provides a platform for evaluating the capabilities of the MAX32665 and MAX32666 +high-efficiency Arm® microcontrollers and audio DSP for wearable and hearable device applications. + + +The Zephyr port is running on the MAX32666 MCU. + +.. image:: img/max32666evkit.webp + :align: center + :alt: MAX32666EVKIT Front + + +Hardware +******** + +- MAX32666 MCU: + + - High-Efficiency Microcontroller and Audio DSP for Wearable and Hearable Devices + + - Arm Cortex-M4 with FPU Up to 96MHz + - Optional Second Arm Cortex-M4 with FPU Optimized for Data Processing + - Low-Power 7.3728MHz System Clock Option + - 1MB Flash, Organized into Dual Banks 2 x 512KB + - 560KB (448KB ECC) SRAM; 3 x 16KB Cache + - Optional Error Correction Code (ECC-SEC-DED)for Cache, SRAM, and Internal Flash + + - Bluetooth 5 Low Energy Radio + + - 1Mbps and 2Mbps Data Throughput + - Long Range (125kbps and 500kbps) + - Advertising Extension + - Rx Sensitivity: -95dbm; Tx Power Up to +4.5dbm + - On-Chip Matching with Single-Ended Antenna Port + + - Power Management Maximizes Operating Time for Battery Applications + + - Integrated SIMO SMPS for Coin-Cell Operation + - Dynamic Voltage Scaling Minimizes Active Core Power Consumption + - 27.3μA/MHz at 3.3V Executing from Cache + - Selectable SRAM Retention in Low Power Modes with RTC Enabled + + - Multiple Peripherals for System Control + + - Three QSPI Master/Slave with Three Chip Selects Each + - Three 4-Wire UARTs + - Three I2C Master/Slave + - Up to 50 GPIO + - QSPI (SPIXF) with Real-Time Flash Decryption + - QSPI (SPIXR) RAM Interface Provides SRAMExpansion + - 8-Input 10-Bit Delta-Sigma ADC 7.8ksps + - USB 2.0 HS Engine with Internal Transceiver + - PDM Interface Supports Two Digital Microphones + - I2S with TDM + - Six 32-Bit Timers + - Two High-Speed Timers + - 1-Wire Master + - Sixteen Pulse Trains (PWM) + - Secure Digital Interface Supports SD3.0/SDIO3.0/eMMC4.51 + + - Secure Valuable IP/Data with Hardware Security + + - Trust Protection Unit (TPU) with MAA SupportsFast ECDSA and Modular Arithmetic + - AES128/192/256, DES, 3DES, Hardware Accelerator + - TRNG Seed Generator + - SHA-2 Accelerator•Secure Bootloader + +- Benefits and Features of MAX32666EVKIT: + + - Bluetooth SMA connector with a 2.4GHz Hinged Whip Antenna + - 1.28in 128 x 128 Monochrome TFT Display + - 64MB XIP Flash + - 1MB XIP RAM + - Stereo Audio Codec with Line-In and Line-Out 3.5mm Jacks + - Digital Audio Microphone + - USB 2.0 Micro B Interface + - USB 2.0 Micro B to Serial UARTs + - Micro SD Card Interface + - Select GPIOs Accessed Through a 0.1in Header + - Access to the 8 Analog Inputs Through a 0.1in Header + - Arm® or SWD JTAG 20-Pin Header + - 1-Wire RJ11 Port + - Can Be Solely Sourced by a Coin Cell Battery + - Board Power Provided by Either USB Port + - Individual Power Measurement on All IC Rails Through Jumpers + - On-Board 1.8V and 3.3V Regulators + - Two General-Purpose LEDs and Two General-Purpose Pushbutton Switches + + +Supported Features +================== + +Below interfaces are supported by Zephyr on MAX32666EVKIT. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ + + +Connections and IOs +=================== + + ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| Name | Name | Settings | Description | ++===========+===============+===============+==================================================================================================+ +| JP1 | I2C0_SCL/SDA | | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects I2C0 SCL and SDA 1.5K pullups from VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects I2C0 SCL and SDA 1.5K pullups to VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP2 | I2C1_SCL/SDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects I2C1 SCL and SDA 1.5K pullups from VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects I2C1 SCL and SDA 1.5K pullups to VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP3 | I2C2_SCL/SDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects I2C2 SCL and SDA 1.5K pullups from VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects I2C2 SCL and SDA 1.5K pullups to VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP4 | P1_14 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects LED D2 from P1_14. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects LED D2 to P1_14. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP5 | P1_15 | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects LED D3 from P1_15. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects LED D3 to P1_15. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP6 | VBUS | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects VBUS to USB connector CN1 to supply board power. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects VBUS to USB connector CN2 to supply board power. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP7 | N/A | N/A | N/A | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP8 | N/A | N/A | N/A | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP9 | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_20 | | | 2-1 | | | Connects the USB to serial UART to GPIO P0_20 (RX1). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_28 | | | 2-3 | | | Connects the USB to serial UART to GPIO P0_28 (RX2). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP10 | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_21 | | | 2-1 | | | Connects the USB to serial UART to GPIO P0_21 (TX1). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_29 | | | 2-3 | | | Connects the USB to serial UART to GPIO P0_29 (TX2). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP11 | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_22 | | | 2-1 | | | Connects the USB to serial UART to GPIO P0_22 (CTS1_N). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_30 | | | 2-3 | | | Connects the USB to serial UART to GPIO P0_30 (CTS2_N). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP12 | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_23 | | | 2-1 | | | Connects the USB to serial UART to GPIO P0_23 (RTS1_N). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | P0_31 | | | 2-3 | | | Connects the USB to serial UART to GPIO P0_31 (RTS2_N). | | +| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP13 | VREGI | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects VREGI to the coin cell battery. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects VREGI to 3V3. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP14 | VDDIOH | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects VDDIOH to VREGO_A | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 3-4 | | | Connects VDDIOH to 1V8. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 5-6 | | | Connects VDDIOH to 3V3. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP15 | VDDIOH | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VDDIOH. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP16 | VDDB | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDDB. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VDDB. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP17 | VDDIO | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Connects VDDIO to VREGO_A. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects VDDIO to 1V8. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP18 | VDDIO | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDDIO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VDDIO. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP19 | VDDA | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VDDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VDDA. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP20 | VCORE_A | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VCORE_A. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VCORE_A. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP21 | VCORE_B | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VCORE_B. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VCORE_B. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP22 | VTXIN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VTXIN. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VTXIN. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP23 | VRXIN | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects power from VRXIN. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | Close | | | Connects power to VRXIN. | | +| | | +-----------+ | +-------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ + + + +Programming and Debugging +************************* + +Flashing +======== + +The MAX32666 MCU can be flashed by connecting an external debug probe to the +SWD port. SWD debug can be accessed through the Cortex 10-pin connector, J6. +Logic levels are fixed to VDDIOH (1.8V or 3.3V). + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 20-pin connector (J7) or a Cortex® 10-pin connector (J6). + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32666EVKIT web page`_ + +.. _MAX32666EVKIT web page: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/MAX32666EVKIT.html diff --git a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts new file mode 100644 index 00000000000..1726cc897ce --- /dev/null +++ b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32666EVKIT"; + compatible = "adi,max32666evkit"; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram4; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio1 14 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>; + label = "Red LED"; + }; + led2: led_2 { + gpios = <&gpio1 15 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>; + label = "Blue LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + pb1: pb1 { + gpios = <&gpio1 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW + | MAX32_GPIO_VSEL_VDDIOH)>; + label = "SW2"; + zephyr,code = ; + }; + pb2: pb2 { + gpios = <&gpio1 7 (GPIO_PULL_UP | GPIO_ACTIVE_LOW + | MAX32_GPIO_VSEL_VDDIOH)>; + label = "SW3"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + sw0 = &pb1; + sw1 = &pb2; + }; +}; + +&uart1 { + pinctrl-0 = <&uart1_tx_p0_21 &uart1_rx_p0_20>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; diff --git a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml new file mode 100644 index 00000000000..f2b63efd1e6 --- /dev/null +++ b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml @@ -0,0 +1,14 @@ +identifier: max32666evkit/max32666/cpu0 +name: max32666evkit cpu0 +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - serial +ram: 560 +flash: 1024 diff --git a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0_defconfig b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0_defconfig new file mode 100644 index 00000000000..fc547f746b1 --- /dev/null +++ b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable uart driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y