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Rename VXMICRO_ARCH_arm -> CONFIG_ARM

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Change-Id: I32b2e39781825504e7936b3df0c864988650c35c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2015-06-05 22:27:08 -04:00
commit 274622ea69
12 changed files with 21 additions and 21 deletions
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2
arch/arm/include/asm_inline.h
View file

@ -33,7 +33,7 @@
#ifndef _ASM_INLINE_H
#define _ASM_INLINE_H
#if !defined(VXMICRO_ARCH_arm) || !defined(CONFIG_CPU_CORTEXM)
#if !defined(CONFIG_ARM) || !defined(CONFIG_CPU_CORTEXM)
#error arch/arm/include/asm_inline.h is for ARM CortexM only
#endif

6
doc/doxygen/irq_test_common_commented.h
View file

@ -42,7 +42,7 @@ Interrupt stuff, abstracted across CPU architectures.
#if defined(CONFIG_X86_32)
#define IRQ_PRIORITY 3
#elif defined(VXMICRO_ARCH_arm)
#elif defined(CONFIG_ARM)
#if defined(CONFIG_CPU_CORTEXM)
#define IRQ_PRIORITY _EXC_PRIO(3)
#endif /* CONFIG_CPU_CORTEXM */
@ -96,7 +96,7 @@ static char sw_isr_trigger_1[] =
};
#endif /* NUM_SW_IRQS >= 2 */
#elif defined(VXMICRO_ARCH_arm)
#elif defined(CONFIG_ARM)
#if defined(CONFIG_CPU_CORTEXM)
#include <nanokernel.h>
static inline void sw_isr_trigger_0(void)
@ -160,7 +160,7 @@ static int initIRQ
sw_isr_trigger_1[1] = vector;
}
#endif /* NUM_SW_IRQS >= 2 */
#elif defined(VXMICRO_ARCH_arm)
#elif defined(CONFIG_ARM)
#if defined(CONFIG_CPU_CORTEXM)
if (i->isr[0])
{

2
include/arch/cpu.h
View file

@ -35,7 +35,7 @@
#if defined(CONFIG_X86_32)
#include <arch/x86/arch.h>
#elif defined(VXMICRO_ARCH_arm)
#elif defined(CONFIG_ARM)
#include <arch/arm/arch.h>
#elif defined(VXMICRO_ARCH_arc)
#include <arch/arc/arch.h>

2
include/linker-defs.h
View file

@ -47,7 +47,7 @@ This file may be included by:
/* include platform dependent linker-defs */
#ifdef CONFIG_X86_32
#include <arch/x86/linker-defs-arch.h>
#elif defined(VXMICRO_ARCH_arm)
#elif defined(CONFIG_ARM)
/* Nothing yet to include */
#elif defined(VXMICRO_ARCH_arc)
/* Nothing yet to include */

2
include/section_tags.h
View file

@ -42,7 +42,7 @@
#define __noinit __section(NOINIT, _FILE_PATH_HASH, __COUNTER__)
#if defined(VXMICRO_ARCH_arm)
#if defined(CONFIG_ARM)
#define __scs_section __section(SCS_SECTION, _FILE_PATH_HASH, __COUNTER__)
#define __scp_section __section(SCP_SECTION, _FILE_PATH_HASH, __COUNTER__)

2
include/sections.h
View file

@ -62,7 +62,7 @@
#define DATA data
#define NOINIT noinit
#if defined(VXMICRO_ARCH_arm)
#if defined(CONFIG_ARM)
#define SCS_SECTION scs
#define SCP_SECTION scp

2
include/toolchain/common.h
View file

@ -93,7 +93,7 @@ Macros to abstract compiler capabilities (common to all toolchains).
#define PERFOPT_ALIGN .balign 1
#endif
#elif defined(VXMICRO_ARCH_arm)
#elif defined(CONFIG_ARM)
#ifdef CONFIG_ISA_THUMB
#define PERFOPT_ALIGN .balign 2

12
include/toolchain/gcc.h
View file

@ -53,7 +53,7 @@
/* The GNU assembler for Cortex-M3 uses # for immediate values, not
* comments, so the @nobits# trick does not work.
*/
#if defined(VXMICRO_ARCH_arm)
#if defined(CONFIG_ARM)
#define _NODATA_SECTION(segment) __attribute__((section(#segment)))
#else
#define _NODATA_SECTION(segment) \
@ -120,7 +120,7 @@ __extension__ ({ \
#if defined(_ASMLANGUAGE) && !defined(_LINKER)
#ifdef VXMICRO_ARCH_arm
#ifdef CONFIG_ARM
#if defined(CONFIG_ISA_THUMB)
@ -155,7 +155,7 @@ A##a:
#define FUNC_CODE()
#define FUNC_INSTR(a)
#endif /* !VXMICRO_ARCH_arm */
#endif /* !CONFIG_ARM */
#endif /* _ASMLANGUAGE && !_LINKER */
@ -168,7 +168,7 @@ A##a:
#if defined(_ASMLANGUAGE) && !defined(_LINKER)
#ifdef VXMICRO_ARCH_arm
#ifdef CONFIG_ARM
#define GTEXT(sym) .global FUNC(sym); .type FUNC(sym),%function
#define GDATA(sym) .global FUNC(sym); .type FUNC(sym),%object
#define WTEXT(sym) .weak FUNC(sym); .type FUNC(sym),%function
@ -191,7 +191,7 @@ A##a:
#define GTEXT(sym) glbl_text sym
#define GDATA(sym) glbl_data sym
#else /* !VXMICRO_ARCH_arm && !VXMICRO_ARCH_arc */
#else /* !CONFIG_ARM && !VXMICRO_ARCH_arc */
#define GTEXT(sym) .globl FUNC(sym); .type FUNC(sym),@function
#define GDATA(sym) .globl FUNC(sym); .type FUNC(sym),@object
#endif
@ -279,7 +279,7 @@ A##a:
#define GEN_ABS_SYM_END }
#if defined(VXMICRO_ARCH_arm)
#if defined(CONFIG_ARM)
/*
* GNU/ARM backend does not have a proper operand modifier which does not

2
kernel/microkernel/k_task.c
View file

@ -137,7 +137,7 @@ void set_state_bit(
* tasks.
*/
#if defined(__GNUC__)
#if defined(VXMICRO_ARCH_arm)
#if defined(CONFIG_ARM)
/*
* Avoid bad code generation by certain gcc toolchains for ARM
* when an optimization setting of -O2 or above is used.

2
kernel/nanokernel/nano_init.c
View file

@ -188,7 +188,7 @@ extern void *__stack_chk_guard;
#if defined(CONFIG_X86_32)
#define _MOVE_INSTR "movl "
#elif defined(VXMICRO_ARCH_arm)
#elif defined(CONFIG_ARM)
#define _MOVE_INSTR "str "
#else
#error "Unknown VXMICRO_ARCH type"

6
samples/include/irq_test_common.h
View file

@ -41,7 +41,7 @@ Interrupt stuff, abstracted across CPU architectures.
#if defined(CONFIG_X86_32)
#define IRQ_PRIORITY 3
#elif defined(VXMICRO_ARCH_arm)
#elif defined(CONFIG_ARM)
#if defined(CONFIG_CPU_CORTEXM)
#define IRQ_PRIORITY _EXC_PRIO(3)
#endif /* CONFIG_CPU_CORTEXM */
@ -90,7 +90,7 @@ static char sw_isr_trigger_1[] = {
};
#endif /* NUM_SW_IRQS >= 2 */
#elif defined(VXMICRO_ARCH_arm)
#elif defined(CONFIG_ARM)
#if defined(CONFIG_CPU_CORTEXM)
#include <nanokernel.h>
static inline void sw_isr_trigger_0(void)
@ -142,7 +142,7 @@ static int initIRQ(struct isrInitInfo *i)
sw_isr_trigger_1[1] = vector;
}
#endif /* NUM_SW_IRQS >= 2 */
#elif defined(VXMICRO_ARCH_arm)
#elif defined(CONFIG_ARM)
#if defined(CONFIG_CPU_CORTEXM)
if (i->isr[0]) {
(void) irq_connect(0, IRQ_PRIORITY, i->isr[0], i->arg[0]);

2
scripts/Makefile.arm.preparch
View file

@ -7,7 +7,7 @@ endif
ifeq ($(CONFIG_CPU_CORTEXM4),y)
arm_FLAGS += -mcpu=cortex-m4 -march=armv7e-m
endif
arm_FLAGS += -DVXMICRO_ARCH_arm
arm_FLAGS += -DCONFIG_ARM
arm_FLAGS += -DVXMICRO_ARCH=arm
arm_FLAGS += $(SECTION_GC_FLAG)
arm_FLAGS += $(LTO_FLAG-$(CONFIG_LTO))