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boards: st: stm32n6570_dk: use I/O delay for Ethernet

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Replace the slew-rate based method of delaying signals with a more
appropriate I/O delay. Also update the comment to better describe
what we are now doing.

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
This commit is contained in:
Mathieu Choplain 2025-06-18 18:58:15 +02:00 • committed by Anas Nashif
commit 2722bbfbf8
1 changed files with 5 additions and 4 deletions
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9
boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi
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@ -345,12 +345,13 @@ zephyr_udc0: &usbotg_hs1 {
};
/**
* Board-specific configuration, required to ensure that
* the Tx CLK and DAT signals arrive in sync at the PHY.
* Without this, the Tx will be unreliable
* Per the RGMII specification, the Tx clock signal must be skewed
* from the Tx data signals by 1~2 ns. On this board, the SoC must
* be configured to add the required delay via pinctrl.
*/
&eth1_rgmii_gtx_clk_pf0 {
slew-rate = "medium-speed";
st,io-delay-path = "output";
st,io-delay-ps = <2000>;
};
&mac {