From 26c38a49a23ac9371e657cb39fdf1bcfb258a7c1 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Wed, 26 Jun 2019 13:34:28 +0200 Subject: [PATCH] soc: arm: uart: Add STM32G0X UART support Add UART support for STM32G0X SoC series. Signed-off-by: Philippe Retornaz Signed-off-by: Francois Ramu Signed-off-by: Francois Ramu --- dts/arm/st/g0/stm32g0.dtsi | 18 ++++++++++++++++++ soc/arm/st_stm32/stm32g0/dts_fixup.h | 19 +++++++++++++++++++ soc/arm/st_stm32/stm32g0/soc.h | 4 ++++ 3 files changed, 41 insertions(+) diff --git a/dts/arm/st/g0/stm32g0.dtsi b/dts/arm/st/g0/stm32g0.dtsi index ded83727ec0..016bd7ec77c 100644 --- a/dts/arm/st/g0/stm32g0.dtsi +++ b/dts/arm/st/g0/stm32g0.dtsi @@ -106,6 +106,24 @@ }; }; + usart1: serial@40013800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40013800 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>; + interrupts = <27 0>; + status = "disabled"; + label = "UART_1"; + }; + + usart2: serial@40004400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>; + interrupts = <28 0>; + status = "disabled"; + label = "UART_2"; + }; + timers3: timers@40000400 { compatible = "st,stm32-timers"; reg = <0x40000400 0x400>; diff --git a/soc/arm/st_stm32/stm32g0/dts_fixup.h b/soc/arm/st_stm32/stm32g0/dts_fixup.h index 31695d4f8fb..1931f00dd6e 100644 --- a/soc/arm/st_stm32/stm32g0/dts_fixup.h +++ b/soc/arm/st_stm32/stm32g0/dts_fixup.h @@ -61,4 +61,23 @@ #define DT_GPIO_STM32_GPIOF_CLOCK_BITS DT_ST_STM32_GPIO_50001400_CLOCK_BITS #define DT_GPIO_STM32_GPIOF_CLOCK_BUS DT_ST_STM32_GPIO_50001400_CLOCK_BUS +/* there is no reference to GPIOE, GPIOG and GPIOH in the dts files */ + +#define DT_UART_STM32_USART_1_BASE_ADDRESS DT_ST_STM32_USART_40013800_BASE_ADDRESS +#define DT_UART_STM32_USART_1_BAUD_RATE DT_ST_STM32_USART_40013800_CURRENT_SPEED +#define DT_UART_STM32_USART_1_IRQ_PRI DT_ST_STM32_USART_40013800_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_1_NAME DT_ST_STM32_USART_40013800_LABEL +#define DT_USART_1_IRQ DT_ST_STM32_USART_40013800_IRQ_0 +#define DT_UART_STM32_USART_1_CLOCK_BITS DT_ST_STM32_USART_40013800_CLOCK_BITS +#define DT_UART_STM32_USART_1_CLOCK_BUS DT_ST_STM32_USART_40013800_CLOCK_BUS + +#define DT_UART_STM32_USART_2_BASE_ADDRESS DT_ST_STM32_USART_40004400_BASE_ADDRESS +#define DT_UART_STM32_USART_2_BAUD_RATE DT_ST_STM32_USART_40004400_CURRENT_SPEED +#define DT_UART_STM32_USART_2_IRQ_PRI DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_2_NAME DT_ST_STM32_USART_40004400_LABEL +#define DT_USART_2_IRQ DT_ST_STM32_USART_40004400_IRQ_0 +#define DT_UART_STM32_USART_2_CLOCK_BITS DT_ST_STM32_USART_40004400_CLOCK_BITS +#define DT_UART_STM32_USART_2_CLOCK_BUS DT_ST_STM32_USART_40004400_CLOCK_BUS +#define DT_UART_STM32_USART_2_HW_FLOW_CONTROL DT_ST_STM32_USART_40004400_HW_FLOW_CONTROL + /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32g0/soc.h b/soc/arm/st_stm32/stm32g0/soc.h index c8de2567204..f3b23f5caf1 100644 --- a/soc/arm/st_stm32/stm32g0/soc.h +++ b/soc/arm/st_stm32/stm32g0/soc.h @@ -44,6 +44,10 @@ #include #endif +#ifdef CONFIG_SERIAL_HAS_DRIVER +#include +#endif + #endif /* !_ASMLANGUAGE */ #endif /* _STM32G0_SOC_H_ */