diff --git a/boards/arm/stm32l562e_dk/CMakeLists.txt b/boards/arm/stm32l562e_dk/CMakeLists.txt
new file mode 100644
index 00000000000..d1b8108cfed
--- /dev/null
+++ b/boards/arm/stm32l562e_dk/CMakeLists.txt
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_PINMUX)
+zephyr_library()
+zephyr_library_sources(pinmux.c)
+zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
+endif()
diff --git a/boards/arm/stm32l562e_dk/Kconfig.board b/boards/arm/stm32l562e_dk/Kconfig.board
new file mode 100644
index 00000000000..44cabce93d3
--- /dev/null
+++ b/boards/arm/stm32l562e_dk/Kconfig.board
@@ -0,0 +1,8 @@
+# STM32L562E-DK Discovery board configuration
+
+# Copyright (c) 2020 Yestin Sun
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_STM32L562E_DK
+	bool "STM32L562E-DK Discovery Development Board"
+	depends on SOC_STM32L562XX
diff --git a/boards/arm/stm32l562e_dk/Kconfig.defconfig b/boards/arm/stm32l562e_dk/Kconfig.defconfig
new file mode 100644
index 00000000000..1a631d7c510
--- /dev/null
+++ b/boards/arm/stm32l562e_dk/Kconfig.defconfig
@@ -0,0 +1,11 @@
+# STM32L562E-DK Discovery board configuration
+
+# Copyright (c) 2020 Yestin Sun
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_STM32L562E_DK
+
+config BOARD
+	default "stm32l562e_dk"
+
+endif # BOARD_STM32L562E_DK
diff --git a/boards/arm/stm32l562e_dk/arduino_r3_connector.dtsi b/boards/arm/stm32l562e_dk/arduino_r3_connector.dtsi
new file mode 100644
index 00000000000..87ee9535e22
--- /dev/null
+++ b/boards/arm/stm32l562e_dk/arduino_r3_connector.dtsi
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2020 Yestin Sun
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	arduino_header: connector {
+		compatible = "arduino-header-r3";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpioa 0 0>,	/* A0 */
+			   <1 0 &gpioa 1 0>,	/* A1 */
+			   <2 0 &gpioa 4 0>,	/* A2 */
+			   <3 0 &gpioa 5 0>,	/* A3 */
+			   <4 0 &gpioc 4 0>,	/* A4 */
+			   <5 0 &gpioc 5 0>,	/* A5 */
+			   <6 0 &gpiob 10 0>,	/* D0 */
+			   <7 0 &gpiob 11 0>,	/* D1 */
+			   <8 0 &gpiod 11 0>,	/* D2 */
+			   <9 0 &gpiod 12 0>,	/* D3 */
+			   <10 0 &gpiof 4 0>,	/* D4 */
+			   <11 0 &gpiod 13 0>,	/* D5 */
+			   <12 0 &gpiob 8 0>,	/* D6 */
+			   <13 0 &gpioc 6 0>,	/* D7 */
+			   <14 0 &gpiog 0 0>,	/* D8 */
+			   <15 0 &gpiob 9 0>,	/* D9 */
+			   <16 0 &gpioe 0 0>,	/* D10 */
+			   <17 0 &gpiob 5 0>,	/* D11 */
+			   <18 0 &gpiob 4 0>,	/* D12 */
+			   <19 0 &gpiog 9 0>,	/* D13 */
+			   <20 0 &gpiob 7 0>,	/* D14 */
+			   <21 0 &gpiob 6 0>;	/* D15 */
+	};
+};
diff --git a/boards/arm/stm32l562e_dk/board.cmake b/boards/arm/stm32l562e_dk/board.cmake
new file mode 100644
index 00000000000..4e000bdbf82
--- /dev/null
+++ b/boards/arm/stm32l562e_dk/board.cmake
@@ -0,0 +1,7 @@
+set_ifndef(BOARD_DEBUG_RUNNER pyocd)
+set_ifndef(BOARD_FLASH_RUNNER pyocd)
+
+board_runner_args(pyocd "--target=stm32l562qeixq")
+
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/arm/stm32l562e_dk/doc/img/stm32l562e_dk.jpg b/boards/arm/stm32l562e_dk/doc/img/stm32l562e_dk.jpg
new file mode 100644
index 00000000000..4a89f61212b
Binary files /dev/null and b/boards/arm/stm32l562e_dk/doc/img/stm32l562e_dk.jpg differ
diff --git a/boards/arm/stm32l562e_dk/doc/index.rst b/boards/arm/stm32l562e_dk/doc/index.rst
new file mode 100644
index 00000000000..b8fc92d1b53
--- /dev/null
+++ b/boards/arm/stm32l562e_dk/doc/index.rst
@@ -0,0 +1,273 @@
+.. _stm32l562e_dk_board:
+
+ST STM32L562E-DK Discovery
+##########################
+
+Overview
+********
+
+The STM32L562E-DK Discovery kit is designed as a complete demonstration and
+development platform for STMicroelectronics Arm |reg| Cortex |reg|-M33 core-based
+STM32L562QEI6QU microcontroller with TrustZone |reg|. Here are some highlights of
+the STM32L562E-DK Discovery board:
+
+
+- STM32L562QEI6QU microcontroller featuring 512 Kbytes of Flash memory and 256 Kbytes of SRAM in BGA132 package
+- 1.54" 240 x 240 pixel-262K color TFT LCD module with parallel interface and touch-control panel
+- USB Type-C |trade| Sink device FS
+- On-board energy meter: 300 nA to 150 mA measurement range with a dedicated USB interface
+- SAI Audio CODEC
+- MEMS digital microphones
+- 512-Mbit Octal-SPI Flash memory
+- Bluetooth |reg| V4.1 Low Energy module
+- iNEMO 3D accelerometer and 3D gyroscope
+- Board connectors
+
+  - STMod+ expansion connector with fan-out expansion board for Wi‑Fi |reg|, Grove and mikroBUS |trade| compatible connectors
+  - Pmod |trade| expansion connector
+  - Audio MEMS daughterboard expansion connector
+  - ARDUINO |reg| Uno V3 expansion connector
+
+- Flexible power-supply options
+
+  - ST-LINK
+  - USB VBUS
+  - external sources
+
+- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability:
+
+  - mass storage
+  - Virtual COM port
+  - debug port
+
+- 2 user LEDs
+- User and reset push-buttons
+
+.. image:: img/stm32l562e_dk.jpg
+   :width: 460px
+   :align: center
+   :height: 474px
+   :alt: STM32L562E-DK Discovery
+
+More information about the board can be found at the `STM32L562E-DK Discovery website`_.
+
+Hardware
+********
+
+The STM32L562xx devices are an ultra-low-power microcontrollers family (STM32L5
+Series) based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core.
+They operate at a frequency of up to 110 MHz.
+
+- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 62 uA/MHz run mode)
+- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU.
+- Performance benchmark:
+
+  - 1.5 DMPIS/MHz (Drystone 2.1)
+  - 442 CoreMark |reg| (4.02 CoreMark |reg| /MHZ)
+
+- Security
+
+  - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals
+  - Flexible life cycle scheme with RDP (readout protection)
+  - Root of trust thanks to unique boot entry and hide protection area (HDP)
+  - Secure Firmware Installation thanks to embedded Root Secure Services
+  - Secure Firmware Update support with TF-M
+  - AES coprocessor
+  - Public key accelerator
+  - On-the-fly decryption of Octo-SPI external memories
+  - HASH hardware accelerator
+  - Active tamper and protection temperature, voltage and frequency attacks
+  - True Random Number Generator NIST SP800-90B compliant
+  - 96-bit unique ID
+  - 512-byte One-Time Programmable for user data
+
+- Clock management:
+
+  - 4 to 48 MHz crystal oscillator
+  - 32 kHz crystal oscillator for RTC (LSE)
+  - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
+  - Internal low-power 32 kHz RC ( |plusminus| 5%)
+  - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
+    LSE (better than  |plusminus| 0.25 % accuracy)
+  - 3 PLLs for system clock, USB, audio, ADC
+
+- Power management
+
+  - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry
+  - Embedded SMPS step-down converter
+  - External SMPS support
+
+- RTC with HW calendar, alarms and calibration
+- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V
+- Up to 22 capacitive sensing channels: support touchkey, linear and rotary touch sensors
+- Up to 16 timers and 2 watchdogs
+
+  - 2x 16-bit advanced motor-control
+  - 2x 32-bit and 5x 16-bit general purpose
+  - 2x 16-bit basic
+  - 3x low-power 16-bit timers (available in Stop mode)
+  - 2x watchdogs
+  - 2x SysTick timer
+
+- Memories
+
+  - Up to 512 MB Flash, 2 banks read-while-write
+  - 512 KB of SRAM including 64 KB with hardware parity check
+  - External memory interface for static memories supporting SRAM, PSRAM, NOR, NAND and FRAM memories
+  - OCTOSPI memory interface
+
+- Rich analog peripherals (independent supply)
+
+  - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS
+  - 2x 12-bit DAC, low-power sample and hold
+  - 2x operational amplifiers with built-in PGA
+  - 2x ultra-low-power comparators
+  - 4x digital filters for sigma delta modulator
+
+- 19x communication interfaces
+
+  - USB Type-C / USB power delivery controller
+  - 2.0 full-speed crystal less solution, LPM and BCD
+  - 2x SAIs (serial audio interface)
+  - 4x I2C FM+(1 Mbit/s), SMBus/PMBus
+  - 6x USARTs (ISO 7816, LIN, IrDA, modem)
+  - 3x SPIs (7x SPIs with USART and OCTOSPI in SPI mode)
+  - 1xFDCAN
+  - 1xSDMMC interface
+  - 2x 14 channel DMA controllers
+
+- CRC calculation unit
+- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade|
+
+
+More information about STM32L562QE can be found here:
+
+- `STM32L562QE on www.st.com`_
+- `STM32L562 reference manual`_
+
+Supported Features
+==================
+
+The Zephyr stm32l562e_dk board configuration supports the following hardware features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port-polling;                |
+|           |            | serial port-interrupt               |
++-----------+------------+-------------------------------------+
+| PINMUX    | on-chip    | pinmux                              |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+
+Other hardware features are not yet supported on this Zephyr port.
+
+The default configuration can be found in the defconfig file:
+``boards/arm/stm32l562e_dk/stm32l562e_dk_defconfig``
+
+
+Connections and IOs
+===================
+
+STM32L562E-DK Discovery Board has 8 GPIO controllers. These controllers are responsible for pin muxing,
+input/output, pull-up, etc.
+
+For mode details please refer to `STM32L562E-DK Discovery board User Manual`_.
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+- USART_1 TX/RX : PA9/PA10
+- USER_PB : PC13
+- LD10 : PG12
+
+System Clock
+------------
+
+STM32L562E-DK System Clock could be driven by internal or external oscillator,
+as well as main PLL clock. By default System clock is driven by PLL clock at
+110MHz, driven by 4MHz medium speed internal oscillator.
+
+Serial Port
+-----------
+
+STM32L562E-DK Discovery board has 6 U(S)ARTs. The Zephyr console output is
+assigned to USART1. Default settings are 115200 8N1.
+
+
+Programming and Debugging
+*************************
+
+Applications for the ``stm32l562e_dk`` board configuration can be built and
+flashed in the usual way (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Flashing
+========
+
+STM32L562E-DK Discovery board includes an ST-LINK/V3E embedded debug tool
+interface. This interface is not yet supported by the openocd version.
+Instead, support can be enabled on pyocd by adding "pack" support with
+the following pyocd command:
+
+.. code-block:: console
+
+   $ pyocd pack --update
+   $ pyocd pack --install stm32l562qe
+
+STM32L562E-DK Discovery board includes an ST-LINK/V2-1 embedded debug tool
+interface.  This interface is supported by the openocd version
+included in the Zephyr SDK since v0.9.2.
+
+Flashing an application to STM32L562E-DK Discovery
+--------------------------------------------------
+
+Connect the STM32L562E-DK Discovery to your host computer using the USB port.
+Then build and flash an application. Here is an example for the
+:ref:`hello_world` application.
+
+Run a serial host program to connect with your Nucleo board:
+
+.. code-block:: console
+
+   $ minicom -D /dev/ttyACM0
+
+Then build and flash the application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: stm32l562e_dk
+   :goals: build flash
+
+You should see the following message on the console:
+
+.. code-block:: console
+
+   Hello World! stm32l562e_dk
+
+Debugging
+=========
+
+You can debug an application in the usual way.  Here is an example for the
+:ref:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: stm32l562e_dk
+   :maybe-skip-config:
+   :goals: debug
+
+.. _STM32L562E-DK Discovery website:
+   https://www.st.com/en/evaluation-tools/stm32l562e-dk.html
+
+.. _STM32L562E-DK Discovery board User Manual:
+   https://www.st.com/resource/en/user_manual/dm00635554.pdf
+
+.. _STM32L562QE on www.st.com:
+   https://www.st.com/en/microcontrollers/stm32l562qe.html
+
+.. _STM32L562 reference manual:
+   http://www.st.com/resource/en/reference_manual/DM00346336.pdf
diff --git a/boards/arm/stm32l562e_dk/pinmux.c b/boards/arm/stm32l562e_dk/pinmux.c
new file mode 100644
index 00000000000..bd11c708788
--- /dev/null
+++ b/boards/arm/stm32l562e_dk/pinmux.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2020 Yestin Sun
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel.h>
+#include <device.h>
+#include <init.h>
+#include <drivers/pinmux.h>
+#include <sys/sys_io.h>
+
+#include <pinmux/stm32/pinmux_stm32.h>
+
+/* pin assignments for STM32L562E-DK Discovery board */
+static const struct pin_config pinconf[] = {
+};
+
+static int pinmux_stm32_init(const struct device *port)
+{
+	ARG_UNUSED(port);
+
+	stm32_setup_pins(pinconf, ARRAY_SIZE(pinconf));
+
+	return 0;
+}
+
+SYS_INIT(pinmux_stm32_init, PRE_KERNEL_1,
+	 CONFIG_PINMUX_STM32_DEVICE_INITIALIZATION_PRIORITY);
diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk.dts b/boards/arm/stm32l562e_dk/stm32l562e_dk.dts
new file mode 100644
index 00000000000..f18d240a455
--- /dev/null
+++ b/boards/arm/stm32l562e_dk/stm32l562e_dk.dts
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2020 Yestin Sun
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include "stm32l562e_dk_common.dtsi"
+
+/ {
+	model = "STMicroelectronics STM32L562E-DK Discovery board";
+	compatible = "st,stm32l562e-dk";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	aliases {
+		led0 = &green_led_10;
+		sw0 = &user_button;
+	};
+};
diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk.yaml b/boards/arm/stm32l562e_dk/stm32l562e_dk.yaml
new file mode 100644
index 00000000000..ae75f43d042
--- /dev/null
+++ b/boards/arm/stm32l562e_dk/stm32l562e_dk.yaml
@@ -0,0 +1,11 @@
+identifier: stm32l562e_dk
+name: ST STM32L562E-DK Discovery
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+ram: 192
+flash: 512
diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk_common.dtsi b/boards/arm/stm32l562e_dk/stm32l562e_dk_common.dtsi
new file mode 100644
index 00000000000..105520544a5
--- /dev/null
+++ b/boards/arm/stm32l562e_dk/stm32l562e_dk_common.dtsi
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2020 Yestin Sun
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l5/stm32l562Xe.dtsi>
+#include <st/l5/stm32l562qeixq-pinctrl.dtsi>
+#include "arduino_r3_connector.dtsi"
+
+/ {
+	leds {
+		compatible = "gpio-leds";
+		red_led_9: led_9 {
+			gpios = <&gpiod 3 GPIO_ACTIVE_HIGH>;
+			label = "User LD9";
+		};
+		green_led_10: led_10 {
+			gpios = <&gpiog 12 GPIO_ACTIVE_HIGH>;
+			label = "User LD10";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button: button {
+			label = "User";
+			gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&usart1 {
+	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
+	current-speed = <115200>;
+	status = "okay";
+};
diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk_defconfig b/boards/arm/stm32l562e_dk/stm32l562e_dk_defconfig
new file mode 100644
index 00000000000..c2579e2a6ef
--- /dev/null
+++ b/boards/arm/stm32l562e_dk/stm32l562e_dk_defconfig
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_STM32L5X=y
+CONFIG_SOC_STM32L562XX=y
+# 110MHz system clock
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=110000000
+
+# enable uart driver
+CONFIG_SERIAL=y
+
+# enable pinmux
+CONFIG_PINMUX=y
+
+# enable GPIO
+CONFIG_GPIO=y
+
+# clock configuration
+CONFIG_CLOCK_CONTROL=y
+# SYSCLK selection
+CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
+# PLL configuration
+CONFIG_CLOCK_STM32_PLL_SRC_MSI=y
+CONFIG_CLOCK_STM32_MSI_RANGE=6
+# produce 110MHz clock at PLL output
+CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1
+CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=55
+CONFIG_CLOCK_STM32_PLL_P_DIVISOR=7
+CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2
+CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
+CONFIG_CLOCK_STM32_AHB_PRESCALER=1
+CONFIG_CLOCK_STM32_APB1_PRESCALER=1
+CONFIG_CLOCK_STM32_APB2_PRESCALER=1
+
+# console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y