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soc: nxp: imxrt118x: add M7 MPU configuration

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Added M7 MPU configuration.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
This commit is contained in:
Yangbo Lu 2024-12-13 16:09:09 +08:00 • committed by Benjamin Cabé
commit 26a59796ed
4 changed files with 41 additions and 6 deletions
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3
soc/nxp/imxrt/CMakeLists.txt
View file

@ -39,9 +39,6 @@ if(CONFIG_SOC_SERIES_IMXRT10XX OR CONFIG_SOC_SERIES_IMXRT11XX)
endif() endif()
if(CONFIG_SOC_SERIES_IMXRT118X) if(CONFIG_SOC_SERIES_IMXRT118X)
if(CONFIG_SOC_MIMXRT1189_CM7)
zephyr_sources(mpu_regions.c)
endif()
if(CONFIG_EXTERNAL_MEM_CONFIG_DATA) if(CONFIG_EXTERNAL_MEM_CONFIG_DATA)
set(boot_hdr_xmcd_data_section ".boot_hdr.xmcd_data") set(boot_hdr_xmcd_data_section ".boot_hdr.xmcd_data")
endif() endif()

4
soc/nxp/imxrt/imxrt118x/CMakeLists.txt
View file

@ -11,6 +11,10 @@ if(CONFIG_SOC_MIMXRT1189_CM33)
zephyr_linker_sources(DTCM_SECTION m33/dtcm.ld) zephyr_linker_sources(DTCM_SECTION m33/dtcm.ld)
endif() endif()
if(CONFIG_SOC_MIMXRT1189_CM7)
zephyr_sources(m7/mpu_regions.c)
endif()
zephyr_include_directories(.) zephyr_include_directories(.)
if(CONFIG_MEMC_MCUX_FLEXSPI) if(CONFIG_MEMC_MCUX_FLEXSPI)

5
soc/nxp/imxrt/imxrt118x/Kconfig
View file

@ -2,7 +2,6 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_IMXRT118X config SOC_SERIES_IMXRT118X
select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS if SOC_MIMXRT1189_CM7
select CPU_CORTEX_M_HAS_DWT select CPU_CORTEX_M_HAS_DWT
select SOC_RESET_HOOK select SOC_RESET_HOOK
select INIT_ARCH_HW_AT_BOOT if SOC_MIMXRT1189_CM33 select INIT_ARCH_HW_AT_BOOT if SOC_MIMXRT1189_CM33
@ -13,8 +12,8 @@ config SOC_SERIES_IMXRT118X
select CPU_HAS_ARM_SAU if SOC_MIMXRT1189_CM33 select CPU_HAS_ARM_SAU if SOC_MIMXRT1189_CM33
select HAS_MCUX select HAS_MCUX
select CPU_HAS_ARM_MPU select CPU_HAS_ARM_MPU
select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS if SOC_MIMXRT1189_CM33 select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
select ARM_MPU if SOC_MIMXRT1189_CM33 select ARM_MPU
select INIT_ARM_PLL select INIT_ARM_PLL
select ARM_TRUSTZONE_M if SOC_MIMXRT1189_CM33 select ARM_TRUSTZONE_M if SOC_MIMXRT1189_CM33
select CPU_HAS_ICACHE select CPU_HAS_ICACHE

35
soc/nxp/imxrt/imxrt118x/m7/mpu_regions.c Normal file
View file

@ -0,0 +1,35 @@
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#define REGION_ITCM_BASE_ADDRESS 0x00000000
#define REGION_ITCM_SIZE REGION_256K
#define REGION_FLEXSPI2_BASE_ADDRESS 0x04000000
#define REGION_FLEXSPI2_SIZE REGION_64M
#define REGION_DTCM_BASE_ADDRESS 0x20000000
#define REGION_DTCM_SIZE REGION_256K
#define REGION_FLEXSPI_BASE_ADDRESS 0x28000000
#define REGION_FLEXSPI_SIZE REGION_128M
#define REGION_PERIPHERAL_BASE_ADDRESS 0x40000000
#define REGION_PERIPHERAL_SIZE REGION_1G
static const struct arm_mpu_region mpu_regions[] = {
MPU_REGION_ENTRY("ITCM", REGION_ITCM_BASE_ADDRESS, REGION_FLASH_ATTR(REGION_ITCM_SIZE)),
MPU_REGION_ENTRY("FLEXSPI2", REGION_FLEXSPI2_BASE_ADDRESS,
REGION_RAM_ATTR(REGION_FLEXSPI2_SIZE)),
MPU_REGION_ENTRY("FLEXSPI", REGION_FLEXSPI_BASE_ADDRESS,
REGION_FLASH_ATTR(REGION_FLEXSPI_SIZE)),
MPU_REGION_ENTRY("DTCM", REGION_DTCM_BASE_ADDRESS, REGION_RAM_ATTR(REGION_DTCM_SIZE)),
MPU_REGION_ENTRY("PERIPHERAL", REGION_PERIPHERAL_BASE_ADDRESS,
REGION_PPB_ATTR(REGION_PERIPHERAL_SIZE)),
};
const struct arm_mpu_config mpu_config = {
.num_regions = ARRAY_SIZE(mpu_regions),
.mpu_regions = mpu_regions,
};