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soc: nxp: mcxn: configure CPU1 TrustZone access level

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Configures AHBSC MASTER_SEC_LEVEL register for the cpu1 before cpu1 is
enabled.  By default, this gives CPU1 secure and privileged access to
the rest of the SOC, same as CPU0.

Signed-off-by: Derek Snell <derek.snell@nxp.com>
This commit is contained in:
Derek Snell 2025-04-29 09:53:18 -04:00 • committed by Benjamin Cabé
commit 26423f2020
2 changed files with 16 additions and 0 deletions
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9
soc/nxp/mcx/mcxn/Kconfig
View file

@ -53,6 +53,15 @@ config MCUX_CORE_SUFFIX
default "_cm33_core1" if SOC_MCXN947_CPU1 default "_cm33_core1" if SOC_MCXN947_CPU1
endif endif
if SECOND_CORE_MCUX
config SECOND_CORE_MCUX_ACCESS_LEVEL
int "default TrustZone access level for secondary core"
default 3
help
Configures AHBSC MASTER_SEC_LEVEL register for the cpu1 before cpu1 is
enabled.
endif
rsource "../../common/Kconfig.flexspi_xip" rsource "../../common/Kconfig.flexspi_xip"
endif # SOC_SERIES_MCXN endif # SOC_SERIES_MCXN

7
soc/nxp/mcx/mcxn/soc.c
View file

@ -44,6 +44,13 @@ DT_FOREACH_STATUS_OKAY(nxp_lpspi, FLEXCOMM_CHECK)
/* This function is also called at deep sleep resume. */ /* This function is also called at deep sleep resume. */
static int second_core_boot(void) static int second_core_boot(void)
{ {
/* Configure CPU1 TrustZone access level before CPU1 is enabled */
AHBSC->MASTER_SEC_LEVEL |=
AHBSC_MASTER_SEC_LEVEL_CPU1(CONFIG_SECOND_CORE_MCUX_ACCESS_LEVEL);
AHBSC->MASTER_SEC_ANTI_POL_REG = (~AHBSC->MASTER_SEC_LEVEL &
~AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) |
AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(2);
/* Boot source for Core 1 from flash */ /* Boot source for Core 1 from flash */
SYSCON->CPBOOT = ((uint32_t)(char *)DT_REG_ADDR(DT_CHOSEN(zephyr_code_cpu1_partition)) & SYSCON->CPBOOT = ((uint32_t)(char *)DT_REG_ADDR(DT_CHOSEN(zephyr_code_cpu1_partition)) &
SYSCON_CPBOOT_CPBOOT_MASK); SYSCON_CPBOOT_CPBOOT_MASK);