michaelh/zephyr
1
0
Fork 0
Code Releases Activity

dts: boards: Add nRF54L15 ENGA configuration

Browse source 
Add conditional DTS compilation in case of ENGA version.

Signed-off-by: Karol Lasończyk <karol.lasonczyk@nordicsemi.no>
This commit is contained in:
Karol Lasończyk 2024-08-22 16:19:40 +02:00 • committed by Carles Cufí
commit 25e90e7bb0
6 changed files with 56 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

2
boards/nordic/nrf54l15pdk/nrf54l15_cpuapp_common.dtsi
View file

@ -6,7 +6,7 @@
/* This file is common to the secure and non-secure domain */
#include <nordic/nrf54l15_cpuapp.dtsi>
#include <nordic/nrf54l15_enga_cpuapp.dtsi>
#include "nrf54l15pdk_nrf54l15-common.dtsi"
/ {

2
boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuflpr.dts
View file

@ -5,7 +5,7 @@
*/
/dts-v1/;
#include <nordic/nrf54l15_cpuflpr.dtsi>
#include <nordic/nrf54l15_enga_cpuflpr.dtsi>
#include "nrf54l15pdk_nrf54l15-common.dtsi"
/ {

4
dts/arm/nordic/nrf54l15_cpuapp.dtsi
View file

@ -44,7 +44,7 @@ nvic: &cpuapp_nvic {};
interrupts = <76 NRF_DEFAULT_IRQ_PRIORITY>;
#mbox-cells = <1>;
nordic,events = <1>;
nordic,events-mask = <0x00008000>;
nordic,events-mask = <0x00100000>;
};
cpuapp_vevif_tx: mailbox@0 {
@ -52,7 +52,7 @@ nvic: &cpuapp_nvic {};
reg = <0x0 0x1000>;
#mbox-cells = <1>;
nordic,tasks = <7>;
nordic,tasks-mask = <0x0003f800>;
nordic,tasks-mask = <0x007f0000>;
status = "disabled";
};
};

18
dts/arm/nordic/nrf54l15_enga_cpuapp.dtsi Normal file
View file

@ -0,0 +1,18 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/nordic/nrf54l15_cpuapp.dtsi>
/delete-node/ &pdm20;
/delete-node/ &pdm21;
&cpuapp_vevif_rx {
nordic,events-mask = <0x00008000>;
};
&cpuapp_vevif_tx {
nordic,tasks-mask = <0x0003f800>;
};

18
dts/riscv/nordic/nrf54l15_cpuflpr.dtsi
View file

@ -27,16 +27,16 @@ clic: &cpuflpr_clic {};
compatible = "nordic,nrf-vevif-task-rx";
status = "disabled";
interrupt-parent = <&cpuflpr_clic>;
interrupts = <11 NRF_DEFAULT_IRQ_PRIORITY>,
<12 NRF_DEFAULT_IRQ_PRIORITY>,
<13 NRF_DEFAULT_IRQ_PRIORITY>,
<14 NRF_DEFAULT_IRQ_PRIORITY>,
<15 NRF_DEFAULT_IRQ_PRIORITY>,
<16 NRF_DEFAULT_IRQ_PRIORITY>,
<17 NRF_DEFAULT_IRQ_PRIORITY>;
interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>,
<17 NRF_DEFAULT_IRQ_PRIORITY>,
<18 NRF_DEFAULT_IRQ_PRIORITY>,
<19 NRF_DEFAULT_IRQ_PRIORITY>,
<20 NRF_DEFAULT_IRQ_PRIORITY>,
<21 NRF_DEFAULT_IRQ_PRIORITY>,
<22 NRF_DEFAULT_IRQ_PRIORITY>;
#mbox-cells = <1>;
nordic,tasks = <7>;
nordic,tasks-mask = <0x0003f800>;
nordic,tasks-mask = <0x007f0000>;
};
};
@ -45,7 +45,7 @@ clic: &cpuflpr_clic {};
compatible = "nordic,nrf-vevif-event-tx";
#mbox-cells = <1>;
nordic,events = <1>;
nordic,events-mask = <0x00008000>;
nordic,events-mask = <0x00100000>;
status = "disabled";
};
};

25
dts/riscv/nordic/nrf54l15_enga_cpuflpr.dtsi Normal file
View file

@ -0,0 +1,25 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <riscv/nordic/nrf54l15_cpuflpr.dtsi>
/delete-node/ &pdm20;
/delete-node/ &pdm21;
&cpuflpr_vevif_rx {
nordic,tasks-mask = <0x0003f800>;
interrupts = <11 NRF_DEFAULT_IRQ_PRIORITY>,
<12 NRF_DEFAULT_IRQ_PRIORITY>,
<13 NRF_DEFAULT_IRQ_PRIORITY>,
<14 NRF_DEFAULT_IRQ_PRIORITY>,
<15 NRF_DEFAULT_IRQ_PRIORITY>,
<16 NRF_DEFAULT_IRQ_PRIORITY>,
<17 NRF_DEFAULT_IRQ_PRIORITY>;
};
&cpuflpr_vevif_tx {
nordic,events-mask = <0x00008000>;
};