From 255f19891a2250edf2ac79f440416580cc91f2cf Mon Sep 17 00:00:00 2001 From: Vincenzo Frascino Date: Mon, 8 May 2017 17:13:53 +0100 Subject: [PATCH] dts: mps2_an385: Initial device tree support This patch adds the intial device tree support to V2M MPS2 AN385 platform. Signed-off-by: Vincenzo Frascino --- .../arm/soc/arm/mps2/Kconfig.defconfig.series | 16 ----- arch/arm/soc/arm/mps2/soc_devices.h | 10 +-- boards/arm/mps2_an385/mps2_an385_defconfig | 5 +- dts/arm/Makefile | 1 + dts/arm/mps2_an385.dts | 72 +++++++++++++++++++ dts/arm/mps2_an385.fixup | 26 +++++++ 6 files changed, 109 insertions(+), 21 deletions(-) create mode 100644 dts/arm/mps2_an385.dts create mode 100644 dts/arm/mps2_an385.fixup diff --git a/arch/arm/soc/arm/mps2/Kconfig.defconfig.series b/arch/arm/soc/arm/mps2/Kconfig.defconfig.series index f926c96931c..8a0e3536bfe 100644 --- a/arch/arm/soc/arm/mps2/Kconfig.defconfig.series +++ b/arch/arm/soc/arm/mps2/Kconfig.defconfig.series @@ -9,26 +9,10 @@ if SOC_SERIES_MPS2 config SOC_SERIES default mps2 -config NUM_IRQ_PRIO_BITS - int - default 3 - config SYS_CLOCK_HW_CYCLES_PER_SEC int default 25000000 -config SRAM_BASE_ADDRESS - default 0x20000000 - -config SRAM_SIZE - default 4096 - -config FLASH_BASE_ADDRESS - default 0x00000000 - -config FLASH_SIZE - default 4096 - source "arch/arm/soc/arm/mps2/Kconfig.defconfig.mps2*" endif # SOC_SERIES_MPS2 diff --git a/arch/arm/soc/arm/mps2/soc_devices.h b/arch/arm/soc/arm/mps2/soc_devices.h index e87e0698986..2fe98e25173 100644 --- a/arch/arm/soc/arm/mps2/soc_devices.h +++ b/arch/arm/soc/arm/mps2/soc_devices.h @@ -25,20 +25,22 @@ #if defined(CONFIG_UART_CMSDK_APB) /* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */ #define CMSDK_APB_UART0 UART_0_BASE_ADDR +#define CMSDK_APB_UART1 UART_1_BASE_ADDR +#define CMSDK_APB_UART2 UART_2_BASE_ADDR +#define CMSDK_APB_UART3 UART_3_BASE_ADDR +#define CMSDK_APB_UART4 UART_4_BASE_ADDR +#ifndef CONFIG_HAS_DTS #define CMSDK_APB_UART_0_IRQ_TX IRQ_UART_0_TX #define CMSDK_APB_UART_0_IRQ_RX IRQ_UART_0_RX -#define CMSDK_APB_UART1 UART_1_BASE_ADDR #define CMSDK_APB_UART_1_IRQ_TX IRQ_UART_1_TX #define CMSDK_APB_UART_1_IRQ_RX IRQ_UART_1_RX -#define CMSDK_APB_UART2 UART_2_BASE_ADDR #define CMSDK_APB_UART_2_IRQ_TX IRQ_UART_2_TX #define CMSDK_APB_UART_2_IRQ_RX IRQ_UART_2_RX -#define CMSDK_APB_UART3 UART_3_BASE_ADDR #define CMSDK_APB_UART_3_IRQ_TX IRQ_UART_3_TX #define CMSDK_APB_UART_3_IRQ_RX IRQ_UART_3_RX -#define CMSDK_APB_UART4 UART_4_BASE_ADDR #define CMSDK_APB_UART_4_IRQ_TX IRQ_UART_4_TX #define CMSDK_APB_UART_4_IRQ_RX IRQ_UART_4_RX +#endif #endif /* CONFIG_UART_CMSDK_APB */ #if defined(CONFIG_WATCHDOG) diff --git a/boards/arm/mps2_an385/mps2_an385_defconfig b/boards/arm/mps2_an385/mps2_an385_defconfig index 427e50246df..9162d2c47c6 100644 --- a/boards/arm/mps2_an385/mps2_an385_defconfig +++ b/boards/arm/mps2_an385/mps2_an385_defconfig @@ -12,6 +12,9 @@ CONFIG_BOARD_MPS2_AN385=y CONFIG_CORTEX_M_SYSTICK=y CONFIG_RUNTIME_NMI=y +#DTS +CONFIG_HAS_DTS=y + # GPIOs CONFIG_GPIO=y @@ -29,4 +32,4 @@ CONFIG_UART_CONSOLE_ON_DEV_NAME="UART_0" # Watchdog CONFIG_WATCHDOG=y -CONFIG_I2C=y \ No newline at end of file +CONFIG_I2C=y diff --git a/dts/arm/Makefile b/dts/arm/Makefile index d452ab91aeb..614ebfc62d1 100644 --- a/dts/arm/Makefile +++ b/dts/arm/Makefile @@ -10,6 +10,7 @@ dtb-$(CONFIG_BOARD_CC3220SF_LAUNCHXL) = cc3220sf_launchxl.dts_compiled dtb-$(CONFIG_BOARD_NUCLEO_L476RG) = nucleo_l476rg.dts_compiled dtb-$(CONFIG_BOARD_NUCLEO_L432KC) = nucleo_l432kc.dts_compiled dtb-$(CONFIG_BOARD_V2M_BEETLE) = v2m_beetle.dts_compiled +dtb-$(CONFIG_BOARD_MPS2_AN385) = mps2_an385.dts_compiled dtb-$(CONFIG_BOARD_OLIMEXINO_STM32) = olimexino_stm32.dts_compiled dtb-$(CONFIG_BOARD_96B_CARBON) = 96b_carbon.dts_compiled dtb-$(CONFIG_BOARD_NUCLEO_F401RE) = nucleo_f401re.dts_compiled diff --git a/dts/arm/mps2_an385.dts b/dts/arm/mps2_an385.dts new file mode 100644 index 00000000000..01bca8db57a --- /dev/null +++ b/dts/arm/mps2_an385.dts @@ -0,0 +1,72 @@ +/dts-v1/; + +#include +#include "arm/mps2/soc_irq.h" + +/ { + compatible = "arm,mps2"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-m3"; + }; + }; + + sram0: memory { + compatible = "sram"; + reg = <0x20000000 0x400000>; + }; + + flash0: flash { + reg = <0 0x400000>; + }; + + soc { + uart0: uart@40004000 { + compatible = "arm,cmsdk-uart"; + reg = <0x40004000 0x14>; + interrupts = ; + current-speed = <115200>; + }; + + uart1: uart@40005000 { + compatible = "arm,cmsdk-uart"; + reg = <0x40005000 0x14>; + interrupts = ; + current-speed = <115200>; + }; + + uart2: uart@40006000 { + compatible = "arm,cmsdk-uart"; + reg = <0x40006000 0x14>; + interrupts = ; + current-speed = <115200>; + }; + + uart3: uart@40007000 { + compatible = "arm,cmsdk-uart"; + reg = <0x40007000 0x14>; + interrupts = ; + current-speed = <115200>; + }; + + uart4: uart@40009000 { + compatible = "arm,cmsdk-uart"; + reg = <0x40009000 0x14>; + interrupts = ; + current-speed = <115200>; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/dts/arm/mps2_an385.fixup b/dts/arm/mps2_an385.fixup new file mode 100644 index 00000000000..40cd1fad7b4 --- /dev/null +++ b/dts/arm/mps2_an385.fixup @@ -0,0 +1,26 @@ +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS + +#define CMSDK_APB_UART_0_IRQ_TX ARM_CMSDK_UART_40004000_IRQ_0 +#define CMSDK_APB_UART_0_IRQ_RX ARM_CMSDK_UART_40004000_IRQ_1 +#define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY +#define CONFIG_UART_CMSDK_APB_PORT0_BAUD_RATE ARM_CMSDK_UART_40004000_CURRENT_SPEED + +#define CMSDK_APB_UART_1_IRQ_TX ARM_CMSDK_UART_40005000_IRQ_0 +#define CMSDK_APB_UART_1_IRQ_RX ARM_CMSDK_UART_40005000_IRQ_1 +#define CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI ARM_CMSDK_UART_40005000_IRQ_0_PRIORITY +#define CONFIG_UART_CMSDK_APB_PORT1_BAUD_RATE ARM_CMSDK_UART_40005000_CURRENT_SPEED + +#define CMSDK_APB_UART_2_IRQ_TX ARM_CMSDK_UART_40006000_IRQ_0 +#define CMSDK_APB_UART_2_IRQ_RX ARM_CMSDK_UART_40006000_IRQ_1 +#define CONFIG_UART_CMSDK_APB_PORT2_IRQ_PRI ARM_CMSDK_UART_40006000_IRQ_0_PRIORITY +#define CONFIG_UART_CMSDK_APB_PORT2_BAUD_RATE ARM_CMSDK_UART_40006000_CURRENT_SPEED + +#define CMSDK_APB_UART_3_IRQ_TX ARM_CMSDK_UART_40007000_IRQ_0 +#define CMSDK_APB_UART_3_IRQ_RX ARM_CMSDK_UART_40007000_IRQ_1 +#define CONFIG_UART_CMSDK_APB_PORT3_IRQ_PRI ARM_CMSDK_UART_40007000_IRQ_0_PRIORITY +#define CONFIG_UART_CMSDK_APB_PORT3_BAUD_RATE ARM_CMSDK_UART_40007000_CURRENT_SPEED + +#define CMSDK_APB_UART_4_IRQ_TX ARM_CMSDK_UART_40009000_IRQ_0 +#define CMSDK_APB_UART_4_IRQ_RX ARM_CMSDK_UART_40009000_IRQ_1 +#define CONFIG_UART_CMSDK_APB_PORT4_IRQ_PRI ARM_CMSDK_UART_40009000_IRQ_0_PRIORITY +#define CONFIG_UART_CMSDK_APB_PORT4_BAUD_RATE ARM_CMSDK_UART_40009000_CURRENT_SPEED