arch: Use dts to set rtc priorities for Intel quark, x86 and arc

Get the name generated through dts as well.
Fix the rtc driver and relevant SoCs accordingly.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka 2018-03-05 13:10:07 +01:00 committed by Anas Nashif
commit 250c4a87ed
12 changed files with 28 additions and 19 deletions

View file

@ -39,9 +39,6 @@ if RTC
config RTC_QMSI
def_bool y
config RTC_0_IRQ_PRI
default 2
endif # RTC
if PWM

View file

@ -43,4 +43,7 @@
#define CONFIG_I2C_1_NAME INTEL_QMSI_I2C_B0002C00_LABEL
#define CONFIG_I2C_1_BITRATE INTEL_QMSI_I2C_B0002C00_CLOCK_FREQUENCY
#define CONFIG_RTC_0_NAME INTEL_QMSI_RTC_B0000400_LABEL
#define CONFIG_RTC_0_IRQ INTEL_QMSI_RTC_B0000400_IRQ_0
#define CONFIG_RTC_0_IRQ_PRI INTEL_QMSI_RTC_B0000400_IRQ_0_PRIORITY
/* End of SoC Level DTS fixup file */

View file

@ -207,6 +207,13 @@
#define CLOCK_SYSTEM_CLOCK_CONTROL (SCSS_REGISTER_BASE + \
SCSS_CCU_SYS_CLK_CTL)
/*
* RTC
*/
#define CONFIG_RTC_0_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH)
static inline void _quark_se_ss_ready(void)
{
shared_data->flags |= ARC_READY;

View file

@ -66,6 +66,7 @@ config RTC_QMSI
def_bool y
config RTC_0_IRQ_PRI
int
default 0
endif # RTC

View file

@ -20,3 +20,7 @@
#define CONFIG_GPIO_QMSI_0_NAME INTEL_QMSI_GPIO_B0000C00_LABEL
#define CONFIG_GPIO_QMSI_0_IRQ INTEL_QMSI_GPIO_B0000C00_IRQ_0
#define CONFIG_GPIO_QMSI_0_IRQ_FLAGS INTEL_QMSI_GPIO_B0000C00_IRQ_0_SENSE
#define CONFIG_RTC_0_NAME INTEL_QMSI_RTC_B0000400_LABEL
#define CONFIG_RTC_0_IRQ INTEL_QMSI_RTC_B0000400_IRQ_0
#define CONFIG_RTC_0_IRQ_FLAGS INTEL_QMSI_RTC_B0000400_IRQ_0_SENSE

View file

@ -181,8 +181,6 @@ endif # WATCHDOG
if RTC
config RTC_QMSI
def_bool y
config RTC_0_IRQ_PRI
default 2
endif # RTC
if BT_H4

View file

@ -32,4 +32,9 @@
#define CONFIG_GPIO_QMSI_1_IRQ_PRI INTEL_QMSI_GPIO_B0800B00_IRQ_0_PRIORITY
#define CONFIG_GPIO_QMSI_1_IRQ_FLAGS INTEL_QMSI_GPIO_B0800B00_IRQ_0_SENSE
#define CONFIG_RTC_0_NAME INTEL_QMSI_RTC_B0000400_LABEL
#define CONFIG_RTC_0_IRQ INTEL_QMSI_RTC_B0000400_IRQ_0
#define CONFIG_RTC_0_IRQ_PRI INTEL_QMSI_RTC_B0000400_IRQ_0_PRIORITY
#define CONFIG_RTC_0_IRQ_FLAGS INTEL_QMSI_RTC_B0000400_IRQ_0_SENSE
/* End of SoC Level DTS fixup file */

View file

@ -20,7 +20,7 @@ if RTC
config RTC_0_NAME
string "Driver instance name"
default "RTC_0"
depends on RTC
depends on RTC && !HAS_DTS
help
RTC driver instance name

View file

@ -7,11 +7,6 @@ config RTC_QMSI
if RTC_QMSI
config RTC_0_IRQ_PRI
int "RTC Driver Interrupt priority"
help
RTC interrupt priority.
config RTC_QMSI_API_REENTRANCY
bool
prompt "RTC shim driver API reentrancy"

View file

@ -142,12 +142,11 @@ static int rtc_qmsi_init(struct device *dev)
k_sem_init(RP_GET(dev), 1, UINT_MAX);
}
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_RTC_0_INT), CONFIG_RTC_0_IRQ_PRI,
qm_rtc_0_isr, NULL,
IOAPIC_EDGE | IOAPIC_HIGH);
IRQ_CONNECT(CONFIG_RTC_0_IRQ, CONFIG_RTC_0_IRQ_PRI,
qm_rtc_0_isr, NULL, CONFIG_RTC_0_IRQ_FLAGS);
/* Unmask RTC interrupt */
irq_enable(IRQ_GET_NUMBER(QM_IRQ_RTC_0_INT));
irq_enable(CONFIG_RTC_0_IRQ);
/* Route RTC interrupt to the current core */
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->rtc_0_int_mask);

View file

@ -58,10 +58,10 @@
rtc: rtc@b0000400 {
compatible = "intel,qmsi-rtc";
reg = <0xb0000400 0x400>;
interrupts = <11 IRQ_TYPE_EDGE_RISING 2>;
interrupt-parent = <&intc>;
clock-frequency = <32768>;
interrupts = <11 IRQ_TYPE_EDGE_RISING 2>;
interrupt-parent = <&intc>;
label = "RTC_0";
};
uart0: uart@b0002000 {

View file

@ -51,7 +51,7 @@
clock-frequency = <32768>;
interrupts = <2 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&intc>;
label = "RTC_0";
};
uart0: uart@b0002000 {