soc: intel_adsp: Unify "active CPUs" state
This feature got written twice for two different purposes (to inform the SOF app of which CPUs are running, and to predicate the delivery of IPIs to the cores ready to receive the interrupt). Use only one. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
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1 changed files with 1 additions and 9 deletions
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@ -88,8 +88,6 @@ static __aligned(XCHAL_DCACHE_LINESIZE) union {
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(*((volatile struct cpustart_rec *) \
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(*((volatile struct cpustart_rec *) \
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z_soc_uncached_ptr(&cpustart_mem.cpustart)))
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z_soc_uncached_ptr(&cpustart_mem.cpustart)))
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static uint32_t cpu_mask;
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/* Simple array of CPUs that are active and available for an IPI. The
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/* Simple array of CPUs that are active and available for an IPI. The
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* IDC interrupt is ALSO used to bring a CPU out of reset, so we need
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* IDC interrupt is ALSO used to bring a CPU out of reset, so we need
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* to be absolutely sure we don't try to IPI a CPU that isn't ready to
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* to be absolutely sure we don't try to IPI a CPU that isn't ready to
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@ -276,7 +274,7 @@ void z_mp_entry(void)
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bool arch_cpu_active(int cpu_num)
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bool arch_cpu_active(int cpu_num)
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{
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{
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return !!(cpu_mask & BIT(cpu_num));
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return cpus_active[cpu_num];
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}
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}
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static ALWAYS_INLINE uint32_t prid(void)
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static ALWAYS_INLINE uint32_t prid(void)
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@ -381,12 +379,6 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
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while (!start_rec.alive)
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while (!start_rec.alive)
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;
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;
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/*
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* No locking needed as long as CPUs can only be powered on by the main
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* CPU and cannot be powered off
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*/
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cpu_mask |= BIT(cpu_num);
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}
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}
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void arch_sched_ipi(void)
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void arch_sched_ipi(void)
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