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riscv: move the tp register from caller-saved to callee-saved

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This is a per-thread register that gets updated only when context
switching. No need to load and save it on every exception entry.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre 2022-03-07 22:48:38 -05:00 • committed by Anas Nashif
commit 247d2c8e3b
8 changed files with 9 additions and 9 deletions
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1
arch/riscv/core/coredump.c
View file

@ -59,7 +59,6 @@ void arch_coredump_info_dump(const z_arch_esf_t *esf)
* registers not presented in coredump.
*/
arch_blk.r.ra = esf->ra;
arch_blk.r.tp = esf->tp;
arch_blk.r.t0 = esf->t0;
arch_blk.r.t1 = esf->t1;
arch_blk.r.t2 = esf->t2;

4
arch/riscv/core/fatal.c
View file

@ -40,9 +40,7 @@ FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason,
LOG_ERR(" a6: " PR_REG " t6: " PR_REG, esf->a6, esf->t6);
LOG_ERR(" a7: " PR_REG, esf->a7);
#ifdef CONFIG_USERSPACE
LOG_ERR(" sp: " PR_REG " tp: " PR_REG, esf->sp, esf->tp);
#else
LOG_ERR(" " NO_REG " tp: " PR_REG, esf->tp);
LOG_ERR(" sp: " PR_REG, esf->sp);
#endif
LOG_ERR(" ra: " PR_REG, esf->ra);
LOG_ERR(" mepc: " PR_REG, esf->mepc);

2
arch/riscv/core/isr.S
View file

@ -56,6 +56,7 @@
op fs11, _thread_offset_to_fs11(reg) ;
#define DO_CALLEE_SAVED(op, reg) \
op s0, _thread_offset_to_tp(reg) ;\
op s0, _thread_offset_to_s0(reg) ;\
op s1, _thread_offset_to_s1(reg) ;\
op s2, _thread_offset_to_s2(reg) ;\
@ -71,7 +72,6 @@
#define DO_CALLER_SAVED(op) \
op ra, __z_arch_esf_t_ra_OFFSET(sp) ;\
op tp, __z_arch_esf_t_tp_OFFSET(sp) ;\
op t0, __z_arch_esf_t_t0_OFFSET(sp) ;\
op t1, __z_arch_esf_t_t1_OFFSET(sp) ;\
op t2, __z_arch_esf_t_t2_OFFSET(sp) ;\

4
arch/riscv/core/offsets/offsets.c
View file

@ -31,8 +31,9 @@ GEN_OFFSET_SYM(_thread_arch_t, swap_return_value);
GEN_OFFSET_SYM(_thread_arch_t, priv_stack_start);
#endif
/* struct coop member offsets */
/* struct _callee_saved member offsets */
GEN_OFFSET_SYM(_callee_saved_t, sp);
GEN_OFFSET_SYM(_callee_saved_t, tp);
GEN_OFFSET_SYM(_callee_saved_t, s0);
GEN_OFFSET_SYM(_callee_saved_t, s1);
GEN_OFFSET_SYM(_callee_saved_t, s2);
@ -64,7 +65,6 @@ GEN_OFFSET_SYM(_callee_saved_t, fs11);
/* esf member offsets */
GEN_OFFSET_SYM(z_arch_esf_t, ra);
GEN_OFFSET_SYM(z_arch_esf_t, tp);
GEN_OFFSET_SYM(z_arch_esf_t, t0);
GEN_OFFSET_SYM(z_arch_esf_t, t1);
GEN_OFFSET_SYM(z_arch_esf_t, t2);

2
arch/riscv/core/thread.c
View file

@ -41,7 +41,7 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
stack_init->a3 = (ulong_t)p3;
#ifdef CONFIG_THREAD_LOCAL_STORAGE
stack_init->tp = (ulong_t)thread->tls;
thread->callee_saved.tp = (ulong_t)thread->tls;
#endif
/*

3
arch/riscv/include/offsets_short_arch.h
View file

@ -20,6 +20,9 @@
#define _thread_offset_to_sp \
(___thread_t_callee_saved_OFFSET + ___callee_saved_t_sp_OFFSET)
#define _thread_offset_to_tp \
(___thread_t_callee_saved_OFFSET + ___callee_saved_t_tp_OFFSET)
#define _thread_offset_to_s0 \
(___thread_t_callee_saved_OFFSET + ___callee_saved_t_s0_OFFSET)

1
include/arch/riscv/exp.h
View file

@ -51,7 +51,6 @@ struct soc_esf {
struct __esf {
ulong_t ra; /* return address */
ulong_t tp; /* thread pointer */
ulong_t t0; /* Caller-saved temporary register */
ulong_t t1; /* Caller-saved temporary register */

1
include/arch/riscv/thread.h
View file

@ -56,6 +56,7 @@
*/
struct _callee_saved {
ulong_t sp; /* Stack pointer, (x2 register) */
ulong_t tp; /* thread pointer */
ulong_t s0; /* saved register/frame pointer */
ulong_t s1; /* saved register */