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riscv: move the tp register from caller-saved to callee-saved

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This is a per-thread register that gets updated only when context
switching. No need to load and save it on every exception entry.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre 2022-03-07 22:48:38 -05:00 • committed by Anas Nashif
commit 247d2c8e3b
8 changed files with 9 additions and 9 deletions
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2
arch/riscv/core/thread.c
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@ -41,7 +41,7 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
stack_init->a3 = (ulong_t)p3;
#ifdef CONFIG_THREAD_LOCAL_STORAGE
stack_init->tp = (ulong_t)thread->tls;
thread->callee_saved.tp = (ulong_t)thread->tls;
#endif
/*