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riscv: move the tp register from caller-saved to callee-saved

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This is a per-thread register that gets updated only when context
switching. No need to load and save it on every exception entry.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre 2022-03-07 22:48:38 -05:00 • committed by Anas Nashif
commit 247d2c8e3b
8 changed files with 9 additions and 9 deletions
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2
arch/riscv/core/isr.S
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@ -56,6 +56,7 @@
op fs11, _thread_offset_to_fs11(reg) ;
#define DO_CALLEE_SAVED(op, reg) \
op s0, _thread_offset_to_tp(reg) ;\
op s0, _thread_offset_to_s0(reg) ;\
op s1, _thread_offset_to_s1(reg) ;\
op s2, _thread_offset_to_s2(reg) ;\
@ -71,7 +72,6 @@
#define DO_CALLER_SAVED(op) \
op ra, __z_arch_esf_t_ra_OFFSET(sp) ;\
op tp, __z_arch_esf_t_tp_OFFSET(sp) ;\
op t0, __z_arch_esf_t_t0_OFFSET(sp) ;\
op t1, __z_arch_esf_t_t1_OFFSET(sp) ;\
op t2, __z_arch_esf_t_t2_OFFSET(sp) ;\