soc: nordic: Add initial support for nRF9280 SiP

The nRF9280 is a SiP (System-in-Package) consisting of the nRF9230 SoC
and additional components such as PMIC and others. Additionally,
the nRF9230 contains several CPUs, similarly to the nRF54h20 SoC.

Update nrfx glue, and add necessary Kconfig and initialization code
to allow building for nRF9280 targets: CPU, Radio and PPR cores.

The nRF9280 is used for all user build targets and Kconfigs,
whereas the nRF9230 is used as the build target for the MDK.

Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
Co-authored-by: Andreas Moltumyr <andreas.moltumyr@nordicsemi.no>

modules/hal_nordic/Kconfig.nrf_regtool

@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 menu "nrf-regtool options"
-	depends on SOC_SERIES_NRF54HX
+	depends on SOC_SERIES_NRF54HX || SOC_SERIES_NRF92X
 
 config NRF_REGTOOL_GENERATE_UICR
 	bool "Generate UICR"

modules/hal_nordic/nrfx/CMakeLists.txt

@@ -52,6 +52,13 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_COMPATIBLE_NRF54L15_CPUAPP NRF_APPLI
 zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9120             NRF9120_XXAA)
 zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9160             NRF9160_XXAA)
 
+zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9230_ENGB_CPUAPP NRF9230_ENGB_XXAA
+                                                                NRF_APPLICATION)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9230_ENGB_CPURAD NRF9230_ENGB_XXAA
+                                                                NRF_RADIOCORE)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9230_ENGB_CPUPPR NRF9230_ENGB_XXAA
+                                                                NRF_PPR)
+
 zephyr_compile_definitions_ifdef(CONFIG_NRF_APPROTECT_LOCK
                                  ENABLE_APPROTECT)
 zephyr_compile_definitions_ifdef(CONFIG_NRF_APPROTECT_USER_HANDLING
@@ -85,6 +92,7 @@ zephyr_library_sources_ifdef(CONFIG_SOC_NRF5340_CPUNET ${MDK_DIR}/system_nrf5340
 zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_NRF54HX ${MDK_DIR}/system_nrf54h.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_NRF54LX ${MDK_DIR}/system_nrf54l.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_NRF91X  ${MDK_DIR}/system_nrf91.c)
+zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_NRF92X  ${MDK_DIR}/system_nrf92.c)
 
 zephyr_library_sources(nrfx_glue.c)
 zephyr_library_sources(${HELPERS_DIR}/nrfx_flag32_allocator.c)
@@ -203,3 +211,6 @@ mdk_svd_ifdef(CONFIG_SOC_NRF54L15_ENGA_CPUAPP nrf54l15_enga_application.svd)
 mdk_svd_ifdef(CONFIG_SOC_NRF54L15_ENGA_CPUFLPR nrf54l15_enga_flpr.svd)
 mdk_svd_ifdef(CONFIG_SOC_NRF9120              nrf9120.svd)
 mdk_svd_ifdef(CONFIG_SOC_NRF9160              nrf9160.svd)
+mdk_svd_ifdef(CONFIG_SOC_NRF9230_ENGB_CPUAPP  nrf9230_engb_application.svd)
+mdk_svd_ifdef(CONFIG_SOC_NRF9230_ENGB_CPUPPR  nrf9230_engb_ppr.svd)
+mdk_svd_ifdef(CONFIG_SOC_NRF9230_ENGB_CPURAD  nrf9230_engb_radiocore.svd)

modules/hal_nordic/nrfx/nrfx_config.h

@@ -1049,6 +1049,12 @@
     #include <nrfx_config_nrf54l15_enga_flpr.h>
 #elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA)
     #include <nrfx_config_nrf91.h>
+#elif defined(NRF9230_ENGB_XXAA) && defined(NRF_APPLICATION)
+    #include <nrfx_config_nrf9230_engb_application.h>
+#elif defined(NRF9230_ENGB_XXAA) && defined(NRF_RADIOCORE)
+    #include <nrfx_config_nrf9230_engb_radiocore.h>
+#elif defined(NRF9230_ENGB_XXAA) && defined(NRF_PPR)
+    #include <nrfx_config_nrf9230_engb_ppr.h>
 #else
     #error "Unknown device."
 #endif

soc/nordic/Kconfig

@@ -18,6 +18,7 @@ rsource "*/Kconfig"
 config NRF_SOC_SECURE_SUPPORTED
 	def_bool !TRUSTED_EXECUTION_NONSECURE || (BUILD_WITH_TFM && TFM_PARTITION_PLATFORM)
 	depends on !SOC_SERIES_NRF54HX
+	depends on !SOC_SERIES_NRF92X
 	help
 	  Hidden function to indicate that the soc_secure functions are
 	  available.

soc/nordic/Kconfig.defconfig

@@ -11,7 +11,7 @@ rsource "*/Kconfig.defconfig"
 if SYS_CLOCK_EXISTS
 
 config CLOCK_CONTROL
-	default y if !SOC_SERIES_NRF54HX
+	default y if (!SOC_SERIES_NRF54HX && !SOC_SERIES_NRF92X)
 
 endif # SYS_CLOCK_EXISTS
 

soc/nordic/Kconfig.soc

@@ -14,6 +14,7 @@ config SOC_SERIES
 	default "nrf54h" if SOC_SERIES_NRF54HX
 	default "nrf54l" if SOC_SERIES_NRF54LX
 	default "nrf91" if SOC_SERIES_NRF91X
+	default "nrf92" if SOC_SERIES_NRF92X
 
 config SOC_FAMILY_NORDIC_NRF
 	bool
@@ -56,4 +57,10 @@ config SOC_SERIES_NRF91X
 	help
 	  Enable support for NRF91 MCU series
 
+config SOC_SERIES_NRF92X
+	bool
+	select SOC_FAMILY_NORDIC_NRF
+	help
+	  Enable support for NRF92 MCU series
+
 rsource "*/Kconfig.soc"

soc/nordic/common/vpr/Kconfig.sysbuild

@@ -4,7 +4,7 @@
 config VPR_LAUNCHER
 	bool "VPR launcher"
 	default y
-	depends on (SOC_NRF54H20_CPUPPR || SOC_NRF54H20_CPUFLPR || SOC_NRF54L15_ENGA_CPUFLPR)
+	depends on (SOC_NRF54H20_CPUPPR || SOC_NRF54H20_CPUFLPR || SOC_NRF54L15_ENGA_CPUFLPR || SOC_NRF9280_CPUPPR)
 	help
 	  Include VPR launcher in build.
 	  VPR launcher is a minimal sample built for an ARM core that starts given VPR core.

soc/nordic/nrf92/CMakeLists.txt

@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Nordic Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_ARM)
+  zephyr_library_sources(soc.c)
+endif()
+
+zephyr_include_directories(.)
+
+# Ensure that image size aligns with 16 bytes so that MRAMC finalizes all writes
+# for the image correctly
+zephyr_linker_sources(SECTIONS SORT_KEY zzz_place_align_at_end align.ld)

soc/nordic/nrf92/Kconfig

@@ -0,0 +1,47 @@
+# Nordic Semiconductor nRF92 MCU line
+
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_NRF92X
+	select HAS_NRFS
+	select HAS_NRFX
+	select HAS_NORDIC_DRIVERS
+	select NRF_PLATFORM_HALTIUM
+
+config SOC_NRF9230_ENGB_CPUAPP
+	select ARM
+	select ARMV8_M_DSP
+	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_DCACHE
+	select CPU_HAS_ICACHE
+	select CPU_HAS_FPU
+	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
+	select HAS_NORDIC_DMM
+	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
+	select NRFS_HAS_CLOCK_SERVICE
+	select NRFS_HAS_DVFS_SERVICE
+	select NRFS_HAS_MRAM_SERVICE
+	select NRFS_HAS_TEMP_SERVICE
+	select NRFS_HAS_VBUS_DETECTOR_SERVICE
+
+config SOC_NRF9230_ENGB_CPURAD
+	select ARM
+	select ARMV8_M_DSP
+	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_DCACHE
+	select CPU_HAS_ICACHE
+	select CPU_HAS_FPU
+	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
+	select HAS_NORDIC_DMM
+	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
+	select NRFS_HAS_CLOCK_SERVICE
+	select NRFS_HAS_MRAM_SERVICE
+	select NRFS_HAS_TEMP_SERVICE
+
+config SOC_NRF9230_ENGB_CPUPPR
+	depends on RISCV_CORE_NORDIC_VPR

soc/nordic/nrf92/Kconfig.defconfig

@@ -0,0 +1,41 @@
+# Nordic Semiconductor nRF92 MCU line
+
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_NRF92X
+
+rsource "Kconfig.defconfig.nrf92*"
+
+if ARM
+
+config CACHE_NRF_CACHE
+	default y if EXTERNAL_CACHE
+
+endif # ARM
+
+if RISCV
+
+DT_CHOSEN_Z_SRAM = zephyr,sram
+DT_CHOSEN_Z_CODE = zephyr,code-partition
+
+config BUILD_OUTPUT_ADJUST_LMA
+	depends on !XIP
+	default "$(dt_chosen_partition_addr_hex,$(DT_CHOSEN_Z_CODE)) - \
+		 $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM))"
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 1000000 if NRF_GRTC_TIMER
+
+endif # RISCV
+
+config SPI_DW_HSSI
+	default y if SPI_DW
+
+config SPI_DW_ACCESS_WORD_ONLY
+	default y if SPI_DW
+
+endif # SOC_SERIES_NRF92X

soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpuapp

@@ -0,0 +1,14 @@
+# Nordic Semiconductor nRF9280 Application MCU
+
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NRF9280_CPUAPP
+
+config NUM_IRQS
+	default 471
+
+config NRF_REGTOOL_GENERATE_UICR
+	default y
+
+endif # SOC_NRF9280_CPUAPP

soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpuppr

@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NRF9280_CPUPPR
+
+config NUM_IRQS
+	default 496
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 1000
+
+endif # SOC_NRF9280_CPUPPR

soc/nordic/nrf92/Kconfig.defconfig.nrf9280_cpurad

@@ -0,0 +1,14 @@
+# Nordic Semiconductor nRF9280 Radio MCU
+
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NRF9280_CPURAD
+
+config NUM_IRQS
+	default 471
+
+config NRF_REGTOOL_GENERATE_UICR
+	default y
+
+endif # SOC_NRF9280_CPURAD

soc/nordic/nrf92/Kconfig.soc

@@ -0,0 +1,66 @@
+# Nordic Semiconductor nRF9280 MCU line
+
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Similarly to other nRF91 family products, the nRF9280 is a
+# SiP (System-in-Package) consisting of the nRF9230 SoC and
+# additional components such as PMIC and others.
+# Additionally, the nRF9230 contains several CPUs, similarly
+# to the nRF54h20 SoC.
+#
+# Like it's done for the nRF91 family, let the nRF9280 SiP
+# be represented by nRF9280 "SoC" in top-level SoC definitions
+# and user-configurable Kconfigs, since that's what visible to users.
+#
+# Keep a nRF9230 Kconfig for the SoC under the hood, complete with
+# the engineering version, because that's what the MDK/nrfx expects
+# as build target, and so that its definition can also be re-used
+# for other SiPs.
+
+config SOC_NRF9230_ENGB
+	bool
+	select SOC_SERIES_NRF92X
+
+config SOC_NRF9230_ENGB_CPUAPP
+	bool
+	select SOC_NRF9230_ENGB
+
+config SOC_NRF9230_ENGB_CPURAD
+	bool
+	select SOC_NRF9230_ENGB
+
+config SOC_NRF9230_ENGB_CPUPPR
+	bool
+	select SOC_NRF9230_ENGB
+
+# The SiP selects the actual SoC complete with engineer revision and appropriate CPU
+config SOC_NRF9280
+	bool
+	select SOC_NRF9230_ENGB_CPUAPP if SOC_NRF9280_CPUAPP
+	select SOC_NRF9230_ENGB_CPURAD if SOC_NRF9280_CPURAD
+	select SOC_NRF9230_ENGB_CPUPPR if SOC_NRF9280_CPUPPR
+	help
+	  nRF9280 SiP
+
+# The CPU select the "SoC" (SiP)
+config SOC_NRF9280_CPUAPP
+	bool
+	select SOC_NRF9280
+	help
+	  nRF9280 CPUAPP
+
+config SOC_NRF9280_CPURAD
+	bool
+	select SOC_NRF9280
+	help
+	  nRF9280 CPURAD
+
+config SOC_NRF9280_CPUPPR
+	bool
+	select SOC_NRF9280
+	help
+	  nRF9280 CPUPPR
+
+config SOC
+	default "nrf9280" if SOC_NRF9280

soc/nordic/nrf92/align.ld

@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+SECTION_PROLOGUE(.align16,,)
+{
+	. = (ALIGN(16) > 0 ? ALIGN(16) : 16) - 1;
+	BYTE(0);
+} GROUP_LINK_IN(ROMABLE_REGION)

soc/nordic/nrf92/soc.c

@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/cache.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <hal/nrf_hsfll.h>
+#include <hal/nrf_lrcconf.h>
+#include <hal/nrf_spu.h>
+#include <soc/nrfx_coredep.h>
+
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#if defined(NRF_APPLICATION)
+#define HSFLL_NODE DT_NODELABEL(cpuapp_hsfll)
+#elif defined(NRF_RADIOCORE)
+#define HSFLL_NODE DT_NODELABEL(cpurad_hsfll)
+#endif
+
+#define FICR_ADDR_GET(node_id, name)                                           \
+	DT_REG_ADDR(DT_PHANDLE_BY_NAME(node_id, nordic_ficrs, name)) +         \
+		DT_PHA_BY_NAME(node_id, nordic_ficrs, name, offset)
+
+#define SPU_INSTANCE_GET(p_addr)                                               \
+	((NRF_SPU_Type *)((p_addr) & (ADDRESS_REGION_Msk |                     \
+				      ADDRESS_SECURITY_Msk |                   \
+				      ADDRESS_DOMAIN_Msk |                     \
+				      ADDRESS_BUS_Msk)))
+
+static void power_domain_init(void)
+{
+	/*
+	 * Set:
+	 *  - LRCCONF010.POWERON.MAIN: 1
+	 *  - LRCCONF010.POWERON.ACT: 1
+	 *  - LRCCONF010.RETAIN.MAIN: 1
+	 *  - LRCCONF010.RETAIN.ACT: 1
+	 *
+	 *  This is done here at boot so that when the idle routine will hit
+	 *  WFI the power domain will be correctly retained.
+	 */
+
+	nrf_lrcconf_poweron_force_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_MAIN, true);
+	nrf_lrcconf_poweron_force_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_0, true);
+
+	nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_MAIN, true);
+	nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_0, true);
+}
+
+static int trim_hsfll(void)
+{
+#if defined(HSFLL_NODE)
+
+	NRF_HSFLL_Type *hsfll = (NRF_HSFLL_Type *)DT_REG_ADDR(HSFLL_NODE);
+	nrf_hsfll_trim_t trim = {
+		.vsup = sys_read32(FICR_ADDR_GET(HSFLL_NODE, vsup)),
+		.coarse = sys_read32(FICR_ADDR_GET(HSFLL_NODE, coarse)),
+		.fine = sys_read32(FICR_ADDR_GET(HSFLL_NODE, fine))
+	};
+
+	LOG_DBG("Trim: HSFLL VSUP: 0x%.8x", trim.vsup);
+	LOG_DBG("Trim: HSFLL COARSE: 0x%.8x", trim.coarse);
+	LOG_DBG("Trim: HSFLL FINE: 0x%.8x", trim.fine);
+
+	nrf_hsfll_clkctrl_mult_set(hsfll,
+				   DT_PROP(HSFLL_NODE, clock_frequency) /
+					   DT_PROP(DT_CLOCKS_CTLR(HSFLL_NODE), clock_frequency));
+	nrf_hsfll_trim_set(hsfll, &trim);
+
+	nrf_hsfll_task_trigger(hsfll, NRF_HSFLL_TASK_FREQ_CHANGE);
+
+	LOG_DBG("NRF_HSFLL->TRIM.VSUP = %d", hsfll->TRIM.VSUP);
+	LOG_DBG("NRF_HSFLL->TRIM.COARSE = %d", hsfll->TRIM.COARSE);
+	LOG_DBG("NRF_HSFLL->TRIM.FINE = %d", hsfll->TRIM.FINE);
+
+#endif /* defined(HSFLL_NODE) */
+
+	return 0;
+}
+
+static int nordicsemi_nrf92_init(void)
+{
+	sys_cache_instr_enable();
+	sys_cache_data_enable();
+
+	power_domain_init();
+
+	trim_hsfll();
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(ccm030), okay)
+	/* DMASEC is set to non-secure by default, which prevents CCM from
+	 * accessing secure memory. Change DMASEC to secure.
+	 */
+	uint32_t ccm030_addr = DT_REG_ADDR(DT_NODELABEL(ccm030));
+	NRF_SPU_Type *spu = SPU_INSTANCE_GET(ccm030_addr);
+
+	nrf_spu_periph_perm_dmasec_set(spu, nrf_address_slave_get(ccm030_addr), true);
+#endif
+
+	return 0;
+}
+
+void arch_busy_wait(uint32_t time_us)
+{
+	nrfx_coredep_delay_us(time_us);
+}
+
+SYS_INIT(nordicsemi_nrf92_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/nordic/nrf92/soc.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef SOC_ARM_NORDIC_NRF_NRF9280_SOC_H_
+#define SOC_ARM_NORDIC_NRF_NRF9280_SOC_H_
+
+#include <soc_nrf_common.h>
+
+#endif /* SOC_ARM_NORDIC_NRF_NRF9280_SOC_H_ */

soc/nordic/soc.yml

@@ -39,6 +39,13 @@ family:
           - name: nrf9151
           - name: nrf9160
           - name: nrf9161
+      - name: nrf92
+        socs:
+          - name: nrf9280
+            cpuclusters:
+              - name: cpuapp
+              - name: cpurad
+              - name: cpuppr
 
 # Recovery/erase is only needed once per core. Prevent resetting the cores whilst flashing
 # multiple images until all images for each core have been flashed, this allows security
@@ -91,6 +98,10 @@ runners:
               - nrf54h20/cpuapp
               - nrf54h20/cpurad
               - nrf54h20/cpuppr
+          - qualifiers:
+              - nrf9280/cpuapp
+              - nrf9280/cpurad
+              - nrf9280/cpuppr
     '--erase':
       - runners:
           - nrfjprog
@@ -138,6 +149,10 @@ runners:
               - nrf54h20/cpuapp
               - nrf54h20/cpurad
               - nrf54h20/cpuppr
+          - qualifiers:
+              - nrf9280/cpuapp
+              - nrf9280/cpurad
+              - nrf9280/cpuppr
     '--reset':
       - runners:
           - nrfjprog
@@ -185,3 +200,7 @@ runners:
               - nrf54h20/cpuapp
               - nrf54h20/cpurad
               - nrf54h20/cpuppr
+          - qualifiers:
+              - nrf9280/cpuapp
+              - nrf9280/cpurad
+              - nrf9280/cpuppr