doc: fix misspellings in Kconfig files

Fix misspellings in Kconfig files missed during regular reviews.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
This commit is contained in:
David B. Kinder 2019-10-28 16:17:17 -07:00 committed by Anas Nashif
commit 241044f178
11 changed files with 14 additions and 14 deletions

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@ -76,8 +76,8 @@ config CUSTOM_SECTION_MIN_ALIGN_SIZE
int "Custom Section Align Size"
default 32
help
Custom algin size of memory section in linker scripts. Usually
it should consume less alignment memory. Alougth this alignment
Custom align size of memory section in linker scripts. Usually
it should consume less alignment memory. Although this alignment
size is configured by users, it must also respect the power of
two regulation if hardware requires.

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@ -85,7 +85,7 @@ config CLOCK_CONTROL_NRF_CALIBRATION_TEMP_DIFF
this amount since the last calibration.
config CLOCK_CONTROL_NRF_CALIBRATION_DEBUG
bool "Calibration intrumentation"
bool "Calibration instrumentation"
help
Enables retrieving debug information like number of performed or
skipped calibrations.

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@ -23,7 +23,7 @@ config ESPI_PERIPHERAL_UART
def_bool y
config ESPI_PERIPHERAL_UART_SOC_MAPPING
int "SoC port exposed as logcial eSPI UART"
int "SoC port exposed as logical eSPI UART"
default 2
depends on ESPI_PERIPHERAL_UART
help

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@ -19,14 +19,14 @@ config KSCAN_XEC_COLUMN_SIZE
default 16
help
Adjust the value to your keyboard columns. The maximum
colum size for the Microchip XEC family is 18 (from 0 to 17).
column size for the Microchip XEC family is 18 (from 0 to 17).
config KSCAN_XEC_ROW_SIZE
int "KSCAN_XEC_ROW_SIZE"
default 8
help
Adjust the value to your keyboard rows. The maximum
colum size for the Microchip XEC family is 8 (from 0 to 7).
column size for the Microchip XEC family is 8 (from 0 to 7).
config KSCAN_XEC_DEBOUNCE_DOWN
int "KSCAN_XEC_DEBOUNCE_DOWN"

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@ -292,7 +292,7 @@ config MBEDTLS_HAVE_ASM
default y if !ARM
help
Enable use of assembly code in mbedTLS. This improves the performances
of asymetric cryptography, however this might have an impact on the
of asymmetric cryptography, however this might have an impact on the
code size.
config MBEDTLS_ENTROPY_ENABLED

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@ -30,13 +30,13 @@ config ESPI_GPIO_DEV0
string "Name of the GPIO port 0"
default "GPIO_0"
help
Name of the port used in mimimal handshake
Name of the port used in minimal handshake
config ESPI_GPIO_DEV1
string "Name of the GPIO port 1"
default "GPIO_1"
help
Name of the port used in mimimal handshake
Name of the port used in minimal handshake
config ESPI_INIT_PIN
int "eSPI master enable pin"

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@ -39,6 +39,6 @@ config STM32H7_BOOT_CM7_CM4GATED
Cortex-M7 and Cortex-M4 running from the flash (each from a bank)
Cortex-M7 boots , performs the System configuration then enable the
Cortex-M4 boot using RCC.
This mode requires option byte setting update (BCM4 uncheked)
This mode requires option byte setting update (BCM4 unchecked)
endchoice

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@ -364,7 +364,7 @@ config BT_KEYS_SAVE_AGING_COUNTER_ON_PAIRING
help
With this option enabled, aging counter will be stored in settings every
time a successful pairing occurs. This increases flash wear out but offers
a more correct finding of the oldest unused paiting info.
a more correct finding of the oldest unused pairing info.
endif # BT_SMP

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@ -142,7 +142,7 @@ config NET_SOCKETS_CAN_RECEIVERS
Socket-CAN interface.
config NET_SOCKETS_NET_MGMT
bool "Enable network mangement socket support [EXPERIMENTAL]"
bool "Enable network management socket support [EXPERIMENTAL]"
depends on NET_MGMT_EVENT
select NET_MGMT_EVENT_INFO
help

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@ -83,7 +83,7 @@ config USB_DEVICE_DISABLE_ZLP_EPIN_HANDLING
bool
help
Stack should not handle ZLP for Variable-length Data Stage
bacause it is taken over by the hardware.
because it is taken over by the hardware.
config USB_DEVICE_BOS
bool "Enable USB Binary Device Object Store (BOS)"