From 23f11933b9e913b72de695de25e337f8e59162b2 Mon Sep 17 00:00:00 2001 From: Sathish Kuttan Date: Fri, 23 Nov 2018 21:49:38 -0800 Subject: [PATCH] dts: intel_s1000: enable DTS for GPIO Added GPIO to SoC device tree Updated SoC DTS fixup Removed Kconfig variables now replaced by DT Signed-off-by: Sathish Kuttan --- .../xtensa/intel_s1000_crb/Kconfig.defconfig | 5 ----- dts/xtensa/intel_s1000.dtsi | 12 ++++++++++++ soc/xtensa/intel_s1000/dts_fixup.h | 19 +++++++++++++++++++ soc/xtensa/intel_s1000/soc.h | 5 ----- 4 files changed, 31 insertions(+), 10 deletions(-) diff --git a/boards/xtensa/intel_s1000_crb/Kconfig.defconfig b/boards/xtensa/intel_s1000_crb/Kconfig.defconfig index 7ff5f698cce..155e2611c96 100644 --- a/boards/xtensa/intel_s1000_crb/Kconfig.defconfig +++ b/boards/xtensa/intel_s1000_crb/Kconfig.defconfig @@ -46,11 +46,6 @@ config CAVS_ISR_TBL_OFFSET config DW_ISR_TBL_OFFSET default 3RD_LVL_ISR_TBL_OFFSET -config GPIO_DW_0_NAME - default "GPIO_PORTA" -config GPIO_DW_0_IRQ_PRI - default 1 - config I2C_0_DEFAULT_CFG default 0x12 if DMA_CAVS diff --git a/dts/xtensa/intel_s1000.dtsi b/dts/xtensa/intel_s1000.dtsi index 4ac06c5ff57..d0188761b2c 100644 --- a/dts/xtensa/intel_s1000.dtsi +++ b/dts/xtensa/intel_s1000.dtsi @@ -1,5 +1,6 @@ #include "skeleton.dtsi" #include +#include / { cpus { @@ -84,6 +85,17 @@ interrupt-parent = <&cavs0>; }; + gpio0: gpio@80c00 { + compatible = "snps,designware-gpio"; + reg = <0x00080c00 0x400>; + bits = <32>; + label = "GPIO"; + interrupts = <4 1 0>; + interrupt-parent = <&dw_intc>; + + gpio-controller; + #gpio-cells = <2>; + }; uart0: uart@80800 { compatible = "ns16550"; diff --git a/soc/xtensa/intel_s1000/dts_fixup.h b/soc/xtensa/intel_s1000/dts_fixup.h index 247eec12a45..f5706615570 100644 --- a/soc/xtensa/intel_s1000/dts_fixup.h +++ b/soc/xtensa/intel_s1000/dts_fixup.h @@ -58,4 +58,23 @@ #define DT_SPI_DW_IRQ_FLAGS DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_SENSE #define DT_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_PRIORITY + +#define DT_GPIO_DW_0_BASE_ADDR \ + DT_SNPS_DESIGNWARE_GPIO_80C00_BASE_ADDRESS +#define DT_GPIO_DW_0_BITS \ + DT_SNPS_DESIGNWARE_GPIO_80C00_BITS +#define DT_GPIO_INTC_IRQ \ + (DT_SNPS_DESIGNWARE_GPIO_80C00_IRQ_0 << INTR_CNTL_IRQ_NUM_SHIFT) +#define DT_GPIO_CAVS_IRQ \ + (DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0 << CAVS_IRQ_NUM_SHIFT) +#define DT_GPIO_XTENSA_IRQ \ + (DT_INTEL_CAVS_INTC_78800_IRQ_0 << XTENSA_IRQ_NUM_SHIFT) +#define DT_GPIO_DW_0_IRQ \ + (DT_GPIO_INTC_IRQ | DT_GPIO_CAVS_IRQ | DT_GPIO_XTENSA_IRQ) +#define CONFIG_GPIO_DW_0_IRQ_PRI \ + DT_SNPS_DESIGNWARE_GPIO_80C00_IRQ_0_PRIORITY +#define DT_GPIO_DW_0_IRQ_FLAGS 0 +#define CONFIG_GPIO_DW_0_NAME \ + DT_SNPS_DESIGNWARE_GPIO_80C00_LABEL + /* End of SoC Level DTS fixup file */ diff --git a/soc/xtensa/intel_s1000/soc.h b/soc/xtensa/intel_s1000/soc.h index 2477cc00648..e92d7404326 100644 --- a/soc/xtensa/intel_s1000/soc.h +++ b/soc/xtensa/intel_s1000/soc.h @@ -36,12 +36,7 @@ #define DW_ICTL_NUM_IRQS 9 /* GPIO */ -#define DT_GPIO_DW_0_BASE_ADDR 0x00080C00 -#define DT_GPIO_DW_0_BITS 32 #define GPIO_DW_PORT_0_INT_MASK 0 -#define DT_GPIO_DW_0_IRQ_FLAGS 0 -#define DT_GPIO_DW_0_IRQ 0x00040706 -#define GPIO_DW_0_IRQ_ICTL_OFFSET INTR_CNTL_IRQ_NUM(DT_GPIO_DW_0_IRQ) /* low power DMACs */ #define LP_GP_DMA_SIZE 0x00001000