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soc: arm: atmel_sam: same70: Rework clock_init

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Update clock_init for the Atmel SAME70 SoC using the new PMC API.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
This commit is contained in:
Pieter De Gendt 2024-01-04 14:23:00 +01:00 • committed by Fabio Baltieri
commit 23edb87cab
1 changed files with 53 additions and 173 deletions
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226
soc/arm/atmel_sam/same70/soc.c
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@ -17,41 +17,14 @@
#include <zephyr/cache.h> #include <zephyr/cache.h>
#include <zephyr/arch/cache.h> #include <zephyr/arch/cache.h>
#include <soc.h> #include <soc.h>
#include <soc_pmc.h>
#include <soc_supc.h>
#include <cmsis_core.h> #include <cmsis_core.h>
#include <zephyr/logging/log.h> #include <zephyr/logging/log.h>
#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
LOG_MODULE_REGISTER(soc); LOG_MODULE_REGISTER(soc);
/* Power Manager Controller */
/*
* PLL clock = Main * (MULA + 1) / DIVA
*
* By default, MULA == 24, DIVA == 1.
* With main crystal running at 12 MHz,
* PLL = 12 * (24 + 1) / 1 = 300 MHz
*
* With Processor Clock prescaler at 1
* Processor Clock (HCLK)=300 MHz.
*/
#define PMC_CKGR_PLLAR_MULA \
(CKGR_PLLAR_MULA(CONFIG_SOC_ATMEL_SAME70_PLLA_MULA))
#define PMC_CKGR_PLLAR_DIVA \
(CKGR_PLLAR_DIVA(CONFIG_SOC_ATMEL_SAME70_PLLA_DIVA))
#if CONFIG_SOC_ATMEL_SAME70_MDIV == 1
#define SOC_ATMEL_SAME70_MDIV PMC_MCKR_MDIV_EQ_PCK
#elif CONFIG_SOC_ATMEL_SAME70_MDIV == 2
#define SOC_ATMEL_SAME70_MDIV PMC_MCKR_MDIV_PCK_DIV2
#elif CONFIG_SOC_ATMEL_SAME70_MDIV == 3
#define SOC_ATMEL_SAME70_MDIV PMC_MCKR_MDIV_PCK_DIV3
#elif CONFIG_SOC_ATMEL_SAME70_MDIV == 4
#define SOC_ATMEL_SAME70_MDIV PMC_MCKR_MDIV_PCK_DIV4
#else
#error "Invalid CONFIG_SOC_ATMEL_SAME70_MDIV define value"
#endif
/** /**
* @brief Setup various clocks on SoC at boot time. * @brief Setup various clocks on SoC at boot time.
* *
@ -60,174 +33,89 @@ LOG_MODULE_REGISTER(soc);
*/ */
static ALWAYS_INLINE void clock_init(void) static ALWAYS_INLINE void clock_init(void)
{ {
uint32_t reg_val; /* Switch the main clock to the internal OSC with 12MHz */
soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ);
#ifdef CONFIG_SOC_ATMEL_SAME70_EXT_SLCK /* Switch MCK (Master Clock) to the main clock */
/* Switch slow clock to the external 32 kHz crystal oscillator */ soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK);
SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL;
/* Wait for oscillator to be stabilized */ EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE;
while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL)) {
;
}
#endif /* CONFIG_SOC_ATMEL_SAME70_EXT_SLCK */
#ifdef CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK soc_pmc_enable_clock_failure_detector();
/*
* Setup main external crystal oscillator if not already done
* by a previous program i.e. bootloader
*/
if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL_Msk)) { if (IS_ENABLED(CONFIG_SOC_ATMEL_SAME70_EXT_SLCK)) {
/* Start the external crystal oscillator */ soc_supc_slow_clock_select_crystal_osc();
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
/* We select maximum setup time.
* While start up time could be shortened
* this optimization is not deemed
* critical now.
*/
| CKGR_MOR_MOSCXTST(0xFFu)
/* RC OSC must stay on */
| CKGR_MOR_MOSCRCEN
| CKGR_MOR_MOSCXTEN;
/* Wait for oscillator to be stabilized */
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
;
}
/* Select the external crystal oscillator as main clock */
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
| CKGR_MOR_MOSCSEL
| CKGR_MOR_MOSCXTST(0xFFu)
| CKGR_MOR_MOSCRCEN
| CKGR_MOR_MOSCXTEN;
/* Wait for external oscillator to be selected */
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
;
}
} }
/* Turn off RC OSC, not used any longer, to save power */
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
| CKGR_MOR_MOSCSEL
| CKGR_MOR_MOSCXTST(0xFFu)
| CKGR_MOR_MOSCXTEN;
/* Wait for RC OSC to be turned off */ if (IS_ENABLED(CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK)) {
while (PMC->PMC_SR & PMC_SR_MOSCRCS) { /*
; * Setup main external crystal oscillator.
*/
/* We select maximum setup time.
* While start up time could be shortened
* this optimization is not deemed
* critical now.
*/
soc_pmc_switch_mainck_to_xtal(false, 0xff);
} }
#ifdef CONFIG_SOC_ATMEL_SAME70_WAIT_MODE
/*
* Instruct CPU to enter Wait mode instead of Sleep mode to
* keep Processor Clock (HCLK) and thus be able to debug
* CPU using JTAG
*/
PMC->PMC_FSMR |= PMC_FSMR_LPM;
#endif
#else
/* Attempt to change main fast RC oscillator frequency */
/* /*
* NOTE: MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR * Set FWS (Flash Wait State) value before increasing Master Clock
* register, should normally be the case here * (MCK) frequency.
* TODO: set FWS based on the actual MCK frequency and VDDIO value
* rather than maximum supported 150 MHz at standard VDDIO=2.7V
*/ */
while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) { EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE;
;
}
/* Set main fast RC oscillator to 12 MHz */
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
| CKGR_MOR_MOSCRCF_12_MHz
| CKGR_MOR_MOSCRCEN;
/* Wait for oscillator to be stabilized */
while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
;
}
#endif /* CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK */
/* /*
* Setup PLLA * Setup PLLA
*/ */
/* Switch MCK (Master Clock) to the main clock first */
reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk;
PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_MAIN_CLK;
/* Wait for clock selection to complete */
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
;
}
/* Setup PLLA */
PMC->CKGR_PLLAR = CKGR_PLLAR_ONE
| PMC_CKGR_PLLAR_MULA
| CKGR_PLLAR_PLLACOUNT(0x3Fu)
| PMC_CKGR_PLLAR_DIVA;
/* /*
* NOTE: Both MULA and DIVA must be set to a value greater than 0 or * PLL clock = Main * (MULA + 1) / DIVA
* otherwise PLL will be disabled. In this case we would get stuck in *
* the following loop. * By default, MULA == 24, DIVA == 1.
* With main crystal running at 12 MHz,
* PLL = 12 * (24 + 1) / 1 = 300 MHz
*
* With Processor Clock prescaler at 1
* Processor Clock (HCLK)=300 MHz.
*/ */
soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAME70_PLLA_MULA, 0x3Fu,
CONFIG_SOC_ATMEL_SAME70_PLLA_DIVA);
/* Wait for PLL lock */
while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
;
}
/* Setup UPLL */ soc_pmc_enable_upllck(0x3Fu);
PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(0x3Fu) | CKGR_UCKR_UPLLEN;
/* Wait for PLL lock */
while (!(PMC->PMC_SR & PMC_SR_LOCKU)) {
;
}
/* /*
* Final setup of the Master Clock * Final setup of the Master Clock
*/ */
/* /* Setting PLLA as MCK, first prescaler, then divider and source last */
* NOTE: PMC_MCKR must not be programmed in a single write operation. soc_pmc_mck_set_prescaler(1);
* If CSS, MDIV or PRES are modified we must wait for MCKRDY bit to be soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAME70_MDIV);
* set again. soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
*/
/* Setup prescaler - PLLA Clock / Processor Clock (HCLK) */
reg_val = PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk;
PMC->PMC_MCKR = reg_val | PMC_MCKR_PRES_CLK_1;
/* Wait for Master Clock setup to complete */ /* Disable internal fast RC if we have an external crystal oscillator */
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { if (IS_ENABLED(CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK)) {
; soc_pmc_osc_disable_fastrc();
}
/* Setup divider - Processor Clock (HCLK) / Master Clock (MCK) */
reg_val = PMC->PMC_MCKR & ~PMC_MCKR_MDIV_Msk;
PMC->PMC_MCKR = reg_val | SOC_ATMEL_SAME70_MDIV;
/* Wait for Master Clock setup to complete */
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
;
}
/* Finally select PLL as Master Clock source */
reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk;
PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_PLLA_CLK;
/* Wait for Master Clock setup to complete */
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
;
} }
} }
void z_arm_platform_init(void) void z_arm_platform_init(void)
{ {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAME70_WAIT_MODE)) {
/*
* Instruct CPU to enter Wait mode instead of Sleep mode to
* keep Processor Clock (HCLK) and thus be able to debug
* CPU using JTAG.
*/
soc_pmc_enable_waitmode();
}
/* /*
* DTCM is enabled by default at reset, therefore we have to disable * DTCM is enabled by default at reset, therefore we have to disable
* it first to get the caches into a state where then the * it first to get the caches into a state where then the
@ -242,14 +130,6 @@ void z_arm_platform_init(void)
sys_cache_instr_enable(); sys_cache_instr_enable();
sys_cache_data_enable(); sys_cache_data_enable();
/*
* Set FWS (Flash Wait State) value before increasing Master Clock
* (MCK) frequency.
* TODO: set FWS based on the actual MCK frequency and VDDIO value
* rather than maximum supported 150 MHz at standard VDDIO=2.7V
*/
EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE;
/* Setup system clocks */ /* Setup system clocks */
clock_init(); clock_init();
} }