diff --git a/arch/arm/soc/st_stm32/stm32l4/Makefile b/arch/arm/soc/st_stm32/stm32l4/Makefile index 85f5b267bdf..ada8aa63b65 100644 --- a/arch/arm/soc/st_stm32/stm32l4/Makefile +++ b/arch/arm/soc/st_stm32/stm32l4/Makefile @@ -1,4 +1,3 @@ obj-y += soc.o obj-$(CONFIG_GPIO) += soc_gpio.o -obj-$(CONFIG_PINMUX) += soc_pinmux.o diff --git a/arch/arm/soc/st_stm32/stm32l4/soc_gpio.c b/arch/arm/soc/st_stm32/stm32l4/soc_gpio.c index bbf17ed0370..de7e3e29e11 100644 --- a/arch/arm/soc/st_stm32/stm32l4/soc_gpio.c +++ b/arch/arm/soc/st_stm32/stm32l4/soc_gpio.c @@ -20,30 +20,9 @@ #include #include "soc.h" #include "soc_registers.h" -#include "soc_pinmux.h" #include #include -enum { - STM32L4X_MODER_INPUT_MODE = 0x0, - STM32L4X_MODER_OUTPUT_MODE = 0x1, - STM32L4X_MODER_ALT_MODE = 0x2, - STM32L4X_MODER_ANALOG_MODE = 0x3, - STM32L4X_MODER_MASK = 0x3, -}; - -enum { - STM32L4X_OTYPER_PUSH_PULL = 0x0, - STM32L4X_OTYPER_OPEN_DRAIN = 0x1, - STM32L4X_OTYPER_MASK = 0x1, -}; - -enum { - STM32L4X_PUPDR_NO_PULL = 0x0, - STM32L4X_PUPDR_PULL_UP = 0x1, - STM32L4X_PUPDR_PULL_DOWN = 0x2, - STM32L4X_PUPDR_MASK = 0x3, -}; enum { STM32L4X_PIN3 = 3, @@ -70,86 +49,28 @@ struct stm32l4x_gpio { u32_t ascr; /* Only present on STM32L4x1, STM32L4x5, STM32L4x6 */ }; -/** - * @brief map pin function to MODE register value - */ -static u32_t func_to_mode(int conf, unsigned int afnum) -{ - /* If an alternate function is specified */ - if (afnum) { - return STM32L4X_MODER_ALT_MODE; - } - - switch (conf) { - case STM32L4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE: - case STM32L4X_PIN_CONFIG_BIAS_PULL_UP: - case STM32L4X_PIN_CONFIG_BIAS_PULL_DOWN: - return STM32L4X_MODER_INPUT_MODE; - case STM32L4X_PIN_CONFIG_ANALOG: - return STM32L4X_MODER_ANALOG_MODE; - default: - return STM32L4X_MODER_OUTPUT_MODE; - } - - return STM32L4X_MODER_INPUT_MODE; -} - -static u32_t func_to_otype(int conf) -{ - switch (conf) { - case STM32L4X_PIN_CONFIG_OPEN_DRAIN: - case STM32L4X_PIN_CONFIG_OPEN_DRAIN_PULL_UP: - case STM32L4X_PIN_CONFIG_OPEN_DRAIN_PULL_DOWN: - return STM32L4X_OTYPER_OPEN_DRAIN; - default: - return STM32L4X_OTYPER_PUSH_PULL; - } - - return STM32L4X_OTYPER_PUSH_PULL; -} - -static u32_t func_to_pupd(int conf) -{ - switch (conf) { - case STM32L4X_PIN_CONFIG_ANALOG: - case STM32L4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE: - case STM32L4X_PIN_CONFIG_PUSH_PULL: - case STM32L4X_PIN_CONFIG_OPEN_DRAIN: - return STM32L4X_PUPDR_NO_PULL; - case STM32L4X_PIN_CONFIG_BIAS_PULL_UP: - case STM32L4X_PIN_CONFIG_PUSH_PULL_PULL_UP: - case STM32L4X_PIN_CONFIG_OPEN_DRAIN_PULL_UP: - return STM32L4X_PUPDR_PULL_UP; - case STM32L4X_PIN_CONFIG_BIAS_PULL_DOWN: - case STM32L4X_PIN_CONFIG_PUSH_PULL_PULL_DOWN: - case STM32L4X_PIN_CONFIG_OPEN_DRAIN_PULL_DOWN: - return STM32L4X_PUPDR_PULL_DOWN; - } - - return STM32L4X_PUPDR_NO_PULL; -} - int stm32_gpio_flags_to_conf(int flags, int *pincfg) { int direction = flags & GPIO_DIR_MASK; + int pud = flags & GPIO_PUD_MASK; if (!pincfg) { return -EINVAL; } if (direction == GPIO_DIR_OUT) { - *pincfg = STM32L4X_PIN_CONFIG_PUSH_PULL; + *pincfg = STM32_MODER_OUTPUT_MODE; } else { - int pud = flags & GPIO_PUD_MASK; - /* pull-{up,down} maybe? */ + *pincfg = STM32_MODER_INPUT_MODE; + if (pud == GPIO_PUD_PULL_UP) { - *pincfg = STM32L4X_PIN_CONFIG_BIAS_PULL_UP; + *pincfg = *pincfg | STM32_PUPDR_PULL_UP; } else if (pud == GPIO_PUD_PULL_DOWN) { - *pincfg = STM32L4X_PIN_CONFIG_BIAS_PULL_DOWN; + *pincfg = *pincfg | STM32_PUPDR_PULL_DOWN; } else { /* floating */ - *pincfg = STM32L4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE; + *pincfg = *pincfg | STM32_PUPDR_NO_PULL; } } @@ -160,26 +81,27 @@ int stm32_gpio_configure(u32_t *base_addr, int pin, int pinconf, int afnum) { volatile struct stm32l4x_gpio *gpio = (struct stm32l4x_gpio *)(base_addr); - unsigned int mode, otype, pupd; + unsigned int mode, otype, ospeed, pupd; unsigned int pin_shift = pin << 1; unsigned int afr_bank = pin / 8; unsigned int afr_shift = (pin % 8) << 2; u32_t scratch; - mode = func_to_mode(pinconf, afnum); - otype = func_to_otype(pinconf); - pupd = func_to_pupd(pinconf); + mode = (pinconf >> STM32_MODER_SHIFT) & STM32_MODER_MASK; + otype = (pinconf >> STM32_OTYPER_SHIFT) & STM32_OTYPER_MASK; + ospeed = (pinconf >> STM32_OSPEEDR_SHIFT) & STM32_OSPEEDR_MASK; + pupd = (pinconf >> STM32_PUPDR_SHIFT) & STM32_PUPDR_MASK; - scratch = gpio->moder & ~(STM32L4X_MODER_MASK << pin_shift); + scratch = gpio->moder & ~(STM32_MODER_MASK << pin_shift); gpio->moder = scratch | (mode << pin_shift); - scratch = gpio->otyper & ~(STM32L4X_OTYPER_MASK << pin); + scratch = gpio->otyper & ~(STM32_OTYPER_MASK << pin); gpio->otyper = scratch | (otype << pin); - scratch = gpio->pupdr & ~(STM32L4X_PUPDR_MASK << pin_shift); + scratch = gpio->pupdr & ~(STM32_PUPDR_MASK << pin_shift); gpio->pupdr = scratch | (pupd << pin_shift); - scratch = gpio->afr[afr_bank] & ~(STM32L4X_AFR_MASK << afr_shift); + scratch = gpio->afr[afr_bank] & ~(STM32_AFR_MASK << afr_shift); gpio->afr[afr_bank] = scratch | (afnum << afr_shift); return 0; diff --git a/arch/arm/soc/st_stm32/stm32l4/soc_pinmux.c b/arch/arm/soc/st_stm32/stm32l4/soc_pinmux.c deleted file mode 100644 index ed1d322c0dc..00000000000 --- a/arch/arm/soc/st_stm32/stm32l4/soc_pinmux.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (c) 2016 Open-RnD Sp. z o.o. - * Copyright (c) 2016 BayLibre, SAS - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include "soc.h" -#include "soc_pinmux.h" -#include -#include -#include -#include - -static const stm32_pin_func_t pin_pa9_funcs[] = { - [STM32L4X_PINMUX_FUNC_PA9_USART1_TX - 1] = - STM32L4X_PIN_CONFIG_PUSH_PULL, -}; - -static const stm32_pin_func_t pin_pa10_funcs[] = { - [STM32L4X_PINMUX_FUNC_PA10_USART1_RX - 1] = - STM32L4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE, -}; - -static const stm32_pin_func_t pin_pa2_funcs[] = { - [STM32L4X_PINMUX_FUNC_PA2_USART2_TX - 1] = - STM32L4X_PIN_CONFIG_PUSH_PULL, -}; - -static const stm32_pin_func_t pin_pa3_funcs[] = { - [STM32L4X_PINMUX_FUNC_PA3_USART2_RX - 1] = - STM32L4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE, -}; - -static const stm32_pin_func_t pin_pb6_funcs[] = { - [STM32L4X_PINMUX_FUNC_PB6_I2C1_SCL - 1] = - STM32L4X_PIN_CONFIG_OPEN_DRAIN_PULL_UP, - [STM32L4X_PINMUX_FUNC_PB6_USART1_TX - 1] = - STM32L4X_PIN_CONFIG_PUSH_PULL, -}; - -static const stm32_pin_func_t pin_pb7_funcs[] = { - [STM32L4X_PINMUX_FUNC_PB7_I2C1_SDA - 1] = - STM32L4X_PIN_CONFIG_OPEN_DRAIN_PULL_UP, - [STM32L4X_PINMUX_FUNC_PB7_USART1_RX - 1] = - STM32L4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE, -}; - -static const stm32_pin_func_t pin_pb10_funcs[] = { - [STM32L4X_PINMUX_FUNC_PB10_USART3_TX - 1] = - STM32L4X_PIN_CONFIG_PUSH_PULL, -}; - -static const stm32_pin_func_t pin_pb11_funcs[] = { - [STM32L4X_PINMUX_FUNC_PB11_USART3_RX - 1] = - STM32L4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE, -}; - -static const stm32_pin_func_t pin_pa0_funcs[] = { - [STM32L4X_PINMUX_FUNC_PA0_PWM2_CH1 - 1] = - STM32L4X_PIN_CONFIG_PUSH_PULL, -}; - -/** - * @brief pin configuration - */ -static const struct stm32_pinmux_conf pins[] = { - STM32_PIN_CONF(STM32_PIN_PA0, pin_pa0_funcs), - STM32_PIN_CONF(STM32_PIN_PA2, pin_pa2_funcs), - STM32_PIN_CONF(STM32_PIN_PA3, pin_pa3_funcs), - STM32_PIN_CONF(STM32_PIN_PA9, pin_pa9_funcs), - STM32_PIN_CONF(STM32_PIN_PA10, pin_pa10_funcs), - STM32_PIN_CONF(STM32_PIN_PB6, pin_pb6_funcs), - STM32_PIN_CONF(STM32_PIN_PB7, pin_pb7_funcs), - STM32_PIN_CONF(STM32_PIN_PB10, pin_pb10_funcs), - STM32_PIN_CONF(STM32_PIN_PB11, pin_pb11_funcs), -}; - -int stm32_get_pin_config(int pin, int func) -{ - /* GPIO function is always available, to save space it is not - * listed in alternate functions array - */ - if (func == STM32_PINMUX_FUNC_GPIO) { - return STM32L4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE; - } - - /* analog function is another 'known' setting */ - if (func == STM32_PINMUX_FUNC_ANALOG) { - return STM32L4X_PIN_CONFIG_ANALOG; - } - - for (int i = 0; i < ARRAY_SIZE(pins); i++) { - if (pins[i].pin == pin) { - if ((func - 1) >= pins[i].nfuncs) { - return -EINVAL; - } - - return pins[i].funcs[func - 1]; - } - } - return -EINVAL; -} diff --git a/arch/arm/soc/st_stm32/stm32l4/soc_pinmux.h b/arch/arm/soc/st_stm32/stm32l4/soc_pinmux.h deleted file mode 100644 index b1590650bca..00000000000 --- a/arch/arm/soc/st_stm32/stm32l4/soc_pinmux.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2016 Open-RnD Sp. z o.o. - * Copyright (c) 2016 BayLibre, SAS - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _STM32L4X_SOC_PINMUX_H_ -#define _STM32L4X_SOC_PINMUX_H_ - -/* IO pin functions */ -enum stm32l4x_pin_config_mode { - STM32L4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE = 0, - STM32L4X_PIN_CONFIG_BIAS_PULL_UP, - STM32L4X_PIN_CONFIG_BIAS_PULL_DOWN, - STM32L4X_PIN_CONFIG_ANALOG, - STM32L4X_PIN_CONFIG_OPEN_DRAIN, - STM32L4X_PIN_CONFIG_OPEN_DRAIN_PULL_UP, - STM32L4X_PIN_CONFIG_OPEN_DRAIN_PULL_DOWN, - STM32L4X_PIN_CONFIG_PUSH_PULL, - STM32L4X_PIN_CONFIG_PUSH_PULL_PULL_UP, - STM32L4X_PIN_CONFIG_PUSH_PULL_PULL_DOWN, -}; - -#endif /* _STM32L4X_SOC_PINMUX_H_ */ diff --git a/drivers/pinmux/stm32/pinmux_stm32.c b/drivers/pinmux/stm32/pinmux_stm32.c index fa41be645e2..46e9b672b63 100644 --- a/drivers/pinmux/stm32/pinmux_stm32.c +++ b/drivers/pinmux/stm32/pinmux_stm32.c @@ -92,20 +92,23 @@ static int stm32_pin_configure(int pin, int func, int altf) int _pinmux_stm32_set(u32_t pin, u32_t func, struct device *clk) { - int config; - /* make sure to enable port clock first */ if (enable_port(STM32_PORT(pin), clk)) { return -EIO; } +#ifdef CONFIG_SOC_SERIES_STM32L4X + return stm32_pin_configure(pin, func, func & STM32_AFR_MASK); +#else /* determine config for alternate function */ - config = stm32_get_pin_config(pin, func); + int config = stm32_get_pin_config(pin, func); + if (config < 0) { return config; } return stm32_pin_configure(pin, config, func); +#endif /* CONFIG_SOC_SERIES_STM32L4X */ } /** @@ -124,6 +127,7 @@ void stm32_setup_pins(const struct pin_config *pinconf, for (i = 0; i < pins; i++) { _pinmux_stm32_set(pinconf[i].pin_num, - pinconf[i].mode, clk); + pinconf[i].mode, + clk); } } diff --git a/drivers/pinmux/stm32/pinmux_stm32.h b/drivers/pinmux/stm32/pinmux_stm32.h index 7c90440773d..d0392a55c74 100644 --- a/drivers/pinmux/stm32/pinmux_stm32.h +++ b/drivers/pinmux/stm32/pinmux_stm32.h @@ -16,6 +16,58 @@ #include #include "pinmux/pinmux.h" + +/** + * @brief PIN configuration bitfield + * + * Pin configuration is coded with the following + * fields + * Alternate Function [ 0 : 7 ] + * GPIO Mode [ 8 : 9 ] + * GPIO Output type [ 10 ] + * GPIO Speed [ 11 : 12 ] + * GPIO PUPD config [ 13 : 14 ] + * + * Applicable to STM32F3, STM32F4, STM32L4 series + */ + +#define STM32_AFR_MASK 0xF + +/* GPIO Mode */ +#define STM32_MODER_INPUT_MODE (0x0<