arch: arm: stm32l4: Rework pinmux driver
STM32L4 pinmux handler is reworked to support future pinmux dts
generation.
Preliminary change is done to move pin configuration
informations in a {pin, conf} structure closer to dts fields
"pins" array is removed and information is transferred to
"pinconf" array
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou
Kumar Gala
parent
63aa5edfc4
commit
2366d23573
7 changed files with 156 additions and 300 deletions
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@ -1,4 +1,3 @@
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obj-y += soc.o
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obj-$(CONFIG_GPIO) += soc_gpio.o
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obj-$(CONFIG_PINMUX) += soc_pinmux.o
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@ -20,30 +20,9 @@
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#include <device.h>
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#include "soc.h"
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#include "soc_registers.h"
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#include "soc_pinmux.h"
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#include <gpio.h>
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#include <gpio/gpio_stm32.h>
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enum {
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STM32L4X_MODER_INPUT_MODE = 0x0,
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STM32L4X_MODER_OUTPUT_MODE = 0x1,
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STM32L4X_MODER_ALT_MODE = 0x2,
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STM32L4X_MODER_ANALOG_MODE = 0x3,
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STM32L4X_MODER_MASK = 0x3,
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};
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enum {
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STM32L4X_OTYPER_PUSH_PULL = 0x0,
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STM32L4X_OTYPER_OPEN_DRAIN = 0x1,
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STM32L4X_OTYPER_MASK = 0x1,
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};
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enum {
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STM32L4X_PUPDR_NO_PULL = 0x0,
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STM32L4X_PUPDR_PULL_UP = 0x1,
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STM32L4X_PUPDR_PULL_DOWN = 0x2,
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STM32L4X_PUPDR_MASK = 0x3,
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};
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enum {
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STM32L4X_PIN3 = 3,
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@ -70,86 +49,28 @@ struct stm32l4x_gpio {
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u32_t ascr; /* Only present on STM32L4x1, STM32L4x5, STM32L4x6 */
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};
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/**
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* @brief map pin function to MODE register value
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*/
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static u32_t func_to_mode(int conf, unsigned int afnum)
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{
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/* If an alternate function is specified */
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if (afnum) {
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return STM32L4X_MODER_ALT_MODE;
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}
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switch (conf) {
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case STM32L4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
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case STM32L4X_PIN_CONFIG_BIAS_PULL_UP:
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case STM32L4X_PIN_CONFIG_BIAS_PULL_DOWN:
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return STM32L4X_MODER_INPUT_MODE;
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case STM32L4X_PIN_CONFIG_ANALOG:
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return STM32L4X_MODER_ANALOG_MODE;
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default:
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return STM32L4X_MODER_OUTPUT_MODE;
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}
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return STM32L4X_MODER_INPUT_MODE;
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}
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static u32_t func_to_otype(int conf)
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{
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switch (conf) {
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case STM32L4X_PIN_CONFIG_OPEN_DRAIN:
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case STM32L4X_PIN_CONFIG_OPEN_DRAIN_PULL_UP:
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case STM32L4X_PIN_CONFIG_OPEN_DRAIN_PULL_DOWN:
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return STM32L4X_OTYPER_OPEN_DRAIN;
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default:
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return STM32L4X_OTYPER_PUSH_PULL;
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}
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return STM32L4X_OTYPER_PUSH_PULL;
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}
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static u32_t func_to_pupd(int conf)
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{
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switch (conf) {
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case STM32L4X_PIN_CONFIG_ANALOG:
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case STM32L4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
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case STM32L4X_PIN_CONFIG_PUSH_PULL:
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case STM32L4X_PIN_CONFIG_OPEN_DRAIN:
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return STM32L4X_PUPDR_NO_PULL;
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case STM32L4X_PIN_CONFIG_BIAS_PULL_UP:
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case STM32L4X_PIN_CONFIG_PUSH_PULL_PULL_UP:
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case STM32L4X_PIN_CONFIG_OPEN_DRAIN_PULL_UP:
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return STM32L4X_PUPDR_PULL_UP;
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case STM32L4X_PIN_CONFIG_BIAS_PULL_DOWN:
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case STM32L4X_PIN_CONFIG_PUSH_PULL_PULL_DOWN:
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case STM32L4X_PIN_CONFIG_OPEN_DRAIN_PULL_DOWN:
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return STM32L4X_PUPDR_PULL_DOWN;
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}
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return STM32L4X_PUPDR_NO_PULL;
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}
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int stm32_gpio_flags_to_conf(int flags, int *pincfg)
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{
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int direction = flags & GPIO_DIR_MASK;
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int pud = flags & GPIO_PUD_MASK;
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if (!pincfg) {
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return -EINVAL;
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}
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if (direction == GPIO_DIR_OUT) {
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*pincfg = STM32L4X_PIN_CONFIG_PUSH_PULL;
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*pincfg = STM32_MODER_OUTPUT_MODE;
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} else {
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int pud = flags & GPIO_PUD_MASK;
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/* pull-{up,down} maybe? */
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*pincfg = STM32_MODER_INPUT_MODE;
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if (pud == GPIO_PUD_PULL_UP) {
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*pincfg = STM32L4X_PIN_CONFIG_BIAS_PULL_UP;
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*pincfg = *pincfg | STM32_PUPDR_PULL_UP;
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} else if (pud == GPIO_PUD_PULL_DOWN) {
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*pincfg = STM32L4X_PIN_CONFIG_BIAS_PULL_DOWN;
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*pincfg = *pincfg | STM32_PUPDR_PULL_DOWN;
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} else {
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/* floating */
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*pincfg = STM32L4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE;
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*pincfg = *pincfg | STM32_PUPDR_NO_PULL;
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}
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}
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@ -160,26 +81,27 @@ int stm32_gpio_configure(u32_t *base_addr, int pin, int pinconf, int afnum)
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{
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volatile struct stm32l4x_gpio *gpio =
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(struct stm32l4x_gpio *)(base_addr);
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unsigned int mode, otype, pupd;
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unsigned int mode, otype, ospeed, pupd;
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unsigned int pin_shift = pin << 1;
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unsigned int afr_bank = pin / 8;
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unsigned int afr_shift = (pin % 8) << 2;
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u32_t scratch;
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mode = func_to_mode(pinconf, afnum);
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otype = func_to_otype(pinconf);
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pupd = func_to_pupd(pinconf);
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mode = (pinconf >> STM32_MODER_SHIFT) & STM32_MODER_MASK;
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otype = (pinconf >> STM32_OTYPER_SHIFT) & STM32_OTYPER_MASK;
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ospeed = (pinconf >> STM32_OSPEEDR_SHIFT) & STM32_OSPEEDR_MASK;
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pupd = (pinconf >> STM32_PUPDR_SHIFT) & STM32_PUPDR_MASK;
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scratch = gpio->moder & ~(STM32L4X_MODER_MASK << pin_shift);
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scratch = gpio->moder & ~(STM32_MODER_MASK << pin_shift);
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gpio->moder = scratch | (mode << pin_shift);
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scratch = gpio->otyper & ~(STM32L4X_OTYPER_MASK << pin);
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scratch = gpio->otyper & ~(STM32_OTYPER_MASK << pin);
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gpio->otyper = scratch | (otype << pin);
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scratch = gpio->pupdr & ~(STM32L4X_PUPDR_MASK << pin_shift);
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scratch = gpio->pupdr & ~(STM32_PUPDR_MASK << pin_shift);
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gpio->pupdr = scratch | (pupd << pin_shift);
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scratch = gpio->afr[afr_bank] & ~(STM32L4X_AFR_MASK << afr_shift);
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scratch = gpio->afr[afr_bank] & ~(STM32_AFR_MASK << afr_shift);
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gpio->afr[afr_bank] = scratch | (afnum << afr_shift);
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return 0;
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@ -1,105 +0,0 @@
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/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2016 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include "soc.h"
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#include "soc_pinmux.h"
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#include <device.h>
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#include <misc/util.h>
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#include <pinmux/stm32/pinmux_stm32.h>
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#include <drivers/clock_control/stm32_clock_control.h>
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static const stm32_pin_func_t pin_pa9_funcs[] = {
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[STM32L4X_PINMUX_FUNC_PA9_USART1_TX - 1] =
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STM32L4X_PIN_CONFIG_PUSH_PULL,
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};
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static const stm32_pin_func_t pin_pa10_funcs[] = {
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[STM32L4X_PINMUX_FUNC_PA10_USART1_RX - 1] =
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STM32L4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
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};
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static const stm32_pin_func_t pin_pa2_funcs[] = {
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[STM32L4X_PINMUX_FUNC_PA2_USART2_TX - 1] =
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STM32L4X_PIN_CONFIG_PUSH_PULL,
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};
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static const stm32_pin_func_t pin_pa3_funcs[] = {
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[STM32L4X_PINMUX_FUNC_PA3_USART2_RX - 1] =
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STM32L4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
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};
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static const stm32_pin_func_t pin_pb6_funcs[] = {
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[STM32L4X_PINMUX_FUNC_PB6_I2C1_SCL - 1] =
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STM32L4X_PIN_CONFIG_OPEN_DRAIN_PULL_UP,
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[STM32L4X_PINMUX_FUNC_PB6_USART1_TX - 1] =
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STM32L4X_PIN_CONFIG_PUSH_PULL,
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};
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static const stm32_pin_func_t pin_pb7_funcs[] = {
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[STM32L4X_PINMUX_FUNC_PB7_I2C1_SDA - 1] =
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STM32L4X_PIN_CONFIG_OPEN_DRAIN_PULL_UP,
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[STM32L4X_PINMUX_FUNC_PB7_USART1_RX - 1] =
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STM32L4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
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};
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static const stm32_pin_func_t pin_pb10_funcs[] = {
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[STM32L4X_PINMUX_FUNC_PB10_USART3_TX - 1] =
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STM32L4X_PIN_CONFIG_PUSH_PULL,
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};
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static const stm32_pin_func_t pin_pb11_funcs[] = {
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[STM32L4X_PINMUX_FUNC_PB11_USART3_RX - 1] =
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STM32L4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
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};
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static const stm32_pin_func_t pin_pa0_funcs[] = {
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[STM32L4X_PINMUX_FUNC_PA0_PWM2_CH1 - 1] =
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STM32L4X_PIN_CONFIG_PUSH_PULL,
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};
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/**
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* @brief pin configuration
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*/
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static const struct stm32_pinmux_conf pins[] = {
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STM32_PIN_CONF(STM32_PIN_PA0, pin_pa0_funcs),
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STM32_PIN_CONF(STM32_PIN_PA2, pin_pa2_funcs),
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STM32_PIN_CONF(STM32_PIN_PA3, pin_pa3_funcs),
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STM32_PIN_CONF(STM32_PIN_PA9, pin_pa9_funcs),
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STM32_PIN_CONF(STM32_PIN_PA10, pin_pa10_funcs),
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STM32_PIN_CONF(STM32_PIN_PB6, pin_pb6_funcs),
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STM32_PIN_CONF(STM32_PIN_PB7, pin_pb7_funcs),
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STM32_PIN_CONF(STM32_PIN_PB10, pin_pb10_funcs),
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STM32_PIN_CONF(STM32_PIN_PB11, pin_pb11_funcs),
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};
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int stm32_get_pin_config(int pin, int func)
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{
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/* GPIO function is always available, to save space it is not
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* listed in alternate functions array
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*/
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if (func == STM32_PINMUX_FUNC_GPIO) {
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return STM32L4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE;
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}
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/* analog function is another 'known' setting */
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if (func == STM32_PINMUX_FUNC_ANALOG) {
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return STM32L4X_PIN_CONFIG_ANALOG;
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}
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for (int i = 0; i < ARRAY_SIZE(pins); i++) {
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if (pins[i].pin == pin) {
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if ((func - 1) >= pins[i].nfuncs) {
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return -EINVAL;
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}
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return pins[i].funcs[func - 1];
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}
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}
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return -EINVAL;
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}
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@ -1,25 +0,0 @@
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/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2016 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _STM32L4X_SOC_PINMUX_H_
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#define _STM32L4X_SOC_PINMUX_H_
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/* IO pin functions */
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enum stm32l4x_pin_config_mode {
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STM32L4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE = 0,
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STM32L4X_PIN_CONFIG_BIAS_PULL_UP,
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STM32L4X_PIN_CONFIG_BIAS_PULL_DOWN,
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STM32L4X_PIN_CONFIG_ANALOG,
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STM32L4X_PIN_CONFIG_OPEN_DRAIN,
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STM32L4X_PIN_CONFIG_OPEN_DRAIN_PULL_UP,
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STM32L4X_PIN_CONFIG_OPEN_DRAIN_PULL_DOWN,
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STM32L4X_PIN_CONFIG_PUSH_PULL,
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STM32L4X_PIN_CONFIG_PUSH_PULL_PULL_UP,
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STM32L4X_PIN_CONFIG_PUSH_PULL_PULL_DOWN,
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};
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#endif /* _STM32L4X_SOC_PINMUX_H_ */
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@ -92,20 +92,23 @@ static int stm32_pin_configure(int pin, int func, int altf)
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int _pinmux_stm32_set(u32_t pin, u32_t func,
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struct device *clk)
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{
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int config;
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/* make sure to enable port clock first */
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if (enable_port(STM32_PORT(pin), clk)) {
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return -EIO;
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}
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#ifdef CONFIG_SOC_SERIES_STM32L4X
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return stm32_pin_configure(pin, func, func & STM32_AFR_MASK);
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#else
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/* determine config for alternate function */
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config = stm32_get_pin_config(pin, func);
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int config = stm32_get_pin_config(pin, func);
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if (config < 0) {
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return config;
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}
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return stm32_pin_configure(pin, config, func);
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#endif /* CONFIG_SOC_SERIES_STM32L4X */
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}
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/**
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@ -124,6 +127,7 @@ void stm32_setup_pins(const struct pin_config *pinconf,
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for (i = 0; i < pins; i++) {
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_pinmux_stm32_set(pinconf[i].pin_num,
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pinconf[i].mode, clk);
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pinconf[i].mode,
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clk);
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}
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}
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@ -16,6 +16,58 @@
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#include <clock_control.h>
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#include "pinmux/pinmux.h"
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/**
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* @brief PIN configuration bitfield
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*
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* Pin configuration is coded with the following
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* fields
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* Alternate Function [ 0 : 7 ]
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* GPIO Mode [ 8 : 9 ]
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* GPIO Output type [ 10 ]
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* GPIO Speed [ 11 : 12 ]
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* GPIO PUPD config [ 13 : 14 ]
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*
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* Applicable to STM32F3, STM32F4, STM32L4 series
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*/
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#define STM32_AFR_MASK 0xF
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/* GPIO Mode */
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#define STM32_MODER_INPUT_MODE (0x0<<STM32_MODER_SHIFT)
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#define STM32_MODER_OUTPUT_MODE (0x1<<STM32_MODER_SHIFT)
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#define STM32_MODER_ALT_MODE (0x2<<STM32_MODER_SHIFT)
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#define STM32_MODER_ANALOG_MODE (0x3<<STM32_MODER_SHIFT)
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#define STM32_MODER_MASK 0x3
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#define STM32_MODER_SHIFT 4
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/* GPIO Output type */
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#define STM32_OTYPER_PUSH_PULL (0x0<<STM32_OTYPER_SHIFT)
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#define STM32_OTYPER_OPEN_DRAIN (0x1<<STM32_OTYPER_SHIFT)
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#define STM32_OTYPER_MASK 0x1
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#define STM32_OTYPER_SHIFT 6
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/* GPIO speed */
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#define STM32_OSPEEDR_LOW_SPEED (0x0<<STM32_OSPEEDR_SHIFT)
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#define STM32_OSPEEDR_MEDIUM_SPEED (0x1<<STM32_OSPEEDR_SHIFT)
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#define STM32_OSPEEDR_HIGH_SPEED (0x2<<STM32_OSPEEDR_SHIFT)
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#define STM32_OSPEEDR_VERY_HIGH_SPEED (0x3<<STM32_OSPEEDR_SHIFT)
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#define STM32_OSPEEDR_MASK 0x3
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#define STM32_OSPEEDR_SHIFT 7
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/* GPIO High impedance/Pull-up/pull-down */
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#define STM32_PUPDR_NO_PULL (0x0<<STM32_PUPDR_SHIFT)
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#define STM32_PUPDR_PULL_UP (0x1<<STM32_PUPDR_SHIFT)
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#define STM32_PUPDR_PULL_DOWN (0x2<<STM32_PUPDR_SHIFT)
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#define STM32_PUPDR_MASK 0x3
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#define STM32_PUPDR_SHIFT 9
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/* Add usefull defines */
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#define STM32_PUSHPULL_NOPULL (STM32_OTYPER_PUSH_PULL | \
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STM32_PUPDR_NO_PULL)
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#define STM32_OPENDRAIN_PULLUP (STM32_OTYPER_OPEN_DRAIN | \
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STM32_PUPDR_PULL_UP)
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/**
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* @brief numerical IDs for IO ports
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*/
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@ -44,26 +96,43 @@ enum stm32_pin_port {
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/*
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*/
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enum stm32_pin_alt_func {
|
||||
STM32_PINMUX_FUNC_ALT_0 = 0, /* GPIO */
|
||||
STM32_PINMUX_FUNC_ALT_1,
|
||||
STM32_PINMUX_FUNC_ALT_2,
|
||||
STM32_PINMUX_FUNC_ALT_3,
|
||||
STM32_PINMUX_FUNC_ALT_4,
|
||||
STM32_PINMUX_FUNC_ALT_5,
|
||||
STM32_PINMUX_FUNC_ALT_6,
|
||||
STM32_PINMUX_FUNC_ALT_7,
|
||||
STM32_PINMUX_FUNC_ALT_8,
|
||||
STM32_PINMUX_FUNC_ALT_9,
|
||||
STM32_PINMUX_FUNC_ALT_10,
|
||||
STM32_PINMUX_FUNC_ALT_11,
|
||||
STM32_PINMUX_FUNC_ALT_12,
|
||||
STM32_PINMUX_FUNC_ALT_13,
|
||||
STM32_PINMUX_FUNC_ALT_14,
|
||||
STM32_PINMUX_FUNC_ALT_15,
|
||||
STM32_PINMUX_FUNC_ALT_16,
|
||||
STM32_PINMUX_FUNC_ALT_MAX
|
||||
STM32_FUNC_ALT_0 = 0, /* GPIO */
|
||||
STM32_FUNC_ALT_1,
|
||||
STM32_FUNC_ALT_2,
|
||||
STM32_FUNC_ALT_3,
|
||||
STM32_FUNC_ALT_4,
|
||||
STM32_FUNC_ALT_5,
|
||||
STM32_FUNC_ALT_6,
|
||||
STM32_FUNC_ALT_7,
|
||||
STM32_FUNC_ALT_8,
|
||||
STM32_FUNC_ALT_9,
|
||||
STM32_FUNC_ALT_10,
|
||||
STM32_FUNC_ALT_11,
|
||||
STM32_FUNC_ALT_12,
|
||||
STM32_FUNC_ALT_13,
|
||||
STM32_FUNC_ALT_14,
|
||||
STM32_FUNC_ALT_15,
|
||||
STM32_FUNC_ALT_16,
|
||||
STM32_FUNC_ALT_MAX
|
||||
};
|
||||
|
||||
#define STM32_PINMUX_ALT_FUNC_0 (STM32_FUNC_ALT_0 | STM32_MODER_ALT_MODE)
|
||||
#define STM32_PINMUX_ALT_FUNC_1 (STM32_FUNC_ALT_1 | STM32_MODER_ALT_MODE)
|
||||
#define STM32_PINMUX_ALT_FUNC_2 (STM32_FUNC_ALT_2 | STM32_MODER_ALT_MODE)
|
||||
#define STM32_PINMUX_ALT_FUNC_3 (STM32_FUNC_ALT_3 | STM32_MODER_ALT_MODE)
|
||||
#define STM32_PINMUX_ALT_FUNC_4 (STM32_FUNC_ALT_4 | STM32_MODER_ALT_MODE)
|
||||
#define STM32_PINMUX_ALT_FUNC_5 (STM32_FUNC_ALT_5 | STM32_MODER_ALT_MODE)
|
||||
#define STM32_PINMUX_ALT_FUNC_6 (STM32_FUNC_ALT_6 | STM32_MODER_ALT_MODE)
|
||||
#define STM32_PINMUX_ALT_FUNC_7 (STM32_FUNC_ALT_7 | STM32_MODER_ALT_MODE)
|
||||
#define STM32_PINMUX_ALT_FUNC_8 (STM32_FUNC_ALT_8 | STM32_MODER_ALT_MODE)
|
||||
#define STM32_PINMUX_ALT_FUNC_9 (STM32_FUNC_ALT_9 | STM32_MODER_ALT_MODE)
|
||||
#define STM32_PINMUX_ALT_FUNC_10 (STM32_FUNC_ALT_10 | STM32_MODER_ALT_MODE)
|
||||
#define STM32_PINMUX_ALT_FUNC_11 (STM32_FUNC_ALT_11 | STM32_MODER_ALT_MODE)
|
||||
#define STM32_PINMUX_ALT_FUNC_12 (STM32_FUNC_ALT_12 | STM32_MODER_ALT_MODE)
|
||||
#define STM32_PINMUX_ALT_FUNC_13 (STM32_FUNC_ALT_13 | STM32_MODER_ALT_MODE)
|
||||
#define STM32_PINMUX_ALT_FUNC_14 (STM32_FUNC_ALT_14 | STM32_MODER_ALT_MODE)
|
||||
#define STM32_PINMUX_ALT_FUNC_15 (STM32_FUNC_ALT_15 | STM32_MODER_ALT_MODE)
|
||||
|
||||
#define STM32_PINMUX_FUNC_GPIO 0
|
||||
#define STM32_PINMUX_FUNC_ANALOG (STM32_PINMUX_FUNC_ALT_MAX)
|
||||
|
||||
|
|
|
|||
|
|
@ -13,68 +13,60 @@
|
|||
*/
|
||||
|
||||
/* Port A */
|
||||
#define STM32L4X_PINMUX_FUNC_PA0_PWM2_CH1 STM32_PINMUX_FUNC_ALT_1
|
||||
#define STM32L4X_PINMUX_FUNC_PA2_USART2_TX STM32_PINMUX_FUNC_ALT_7
|
||||
#define STM32L4X_PINMUX_FUNC_PA3_USART2_RX STM32_PINMUX_FUNC_ALT_7
|
||||
#define STM32L4X_PINMUX_FUNC_PA4_SPI1_NSS STM32_PINMUX_FUNC_ALT_5
|
||||
#define STM32L4X_PINMUX_FUNC_PA5_SPI1_SCK STM32_PINMUX_FUNC_ALT_5
|
||||
#define STM32L4X_PINMUX_FUNC_PA6_SPI1_MISO STM32_PINMUX_FUNC_ALT_5
|
||||
#define STM32L4X_PINMUX_FUNC_PA7_SPI1_MOSI STM32_PINMUX_FUNC_ALT_5
|
||||
#define STM32L4X_PINMUX_FUNC_PA9_USART1_TX STM32_PINMUX_FUNC_ALT_7
|
||||
#define STM32L4X_PINMUX_FUNC_PA10_USART1_RX STM32_PINMUX_FUNC_ALT_7
|
||||
#define STM32L4X_PINMUX_FUNC_PA15_PWM2_CH1 STM32_PINMUX_FUNC_ALT_1
|
||||
#define STM32L4X_PINMUX_FUNC_PA15_USART2_RX STM32_PINMUX_FUNC_ALT_3
|
||||
#define STM32L4X_PINMUX_FUNC_PA15_SPI3_NSS STM32_PINMUX_FUNC_ALT_6
|
||||
#define STM32L4X_PINMUX_FUNC_PA0_PWM2_CH1 STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PA2_USART2_TX STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PA3_USART2_RX STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL
|
||||
#define STM32L4X_PINMUX_FUNC_PA4_SPI1_NSS STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PA5_SPI1_SCK STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PA6_SPI1_MISO STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PA7_SPI1_MOSI STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PA9_USART1_TX STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PA10_USART1_RX STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL
|
||||
#define STM32L4X_PINMUX_FUNC_PA15_PWM2_CH1 STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PA15_USART2_RX STM32_PINMUX_ALT_FUNC_3 | STM32_PUPDR_NO_PULL
|
||||
|
||||
/* Port B */
|
||||
#define STM32L4X_PINMUX_FUNC_PB3_SPI1_SCK STM32_PINMUX_FUNC_ALT_5
|
||||
#define STM32L4X_PINMUX_FUNC_PB3_SPI3_SCK STM32_PINMUX_FUNC_ALT_6
|
||||
#define STM32L4X_PINMUX_FUNC_PB4_SPI3_MISO STM32_PINMUX_FUNC_ALT_6
|
||||
#define STM32L4X_PINMUX_FUNC_PB5_SPI3_MOSI STM32_PINMUX_FUNC_ALT_6
|
||||
#define STM32L4X_PINMUX_FUNC_PB6_I2C1_SCL STM32_PINMUX_FUNC_ALT_4
|
||||
#define STM32L4X_PINMUX_FUNC_PB6_USART1_TX STM32_PINMUX_FUNC_ALT_7
|
||||
#define STM32L4X_PINMUX_FUNC_PB7_I2C1_SDA STM32_PINMUX_FUNC_ALT_4
|
||||
#define STM32L4X_PINMUX_FUNC_PB7_USART1_RX STM32_PINMUX_FUNC_ALT_7
|
||||
#define STM32L4X_PINMUX_FUNC_PB8_I2C1_SCL STM32_PINMUX_FUNC_ALT_4
|
||||
#define STM32L4X_PINMUX_FUNC_PB9_I2C1_SDA STM32_PINMUX_FUNC_ALT_4
|
||||
#define STM32L4X_PINMUX_FUNC_PB10_I2C2_SCL STM32_PINMUX_FUNC_ALT_4
|
||||
#define STM32L4X_PINMUX_FUNC_PB10_USART3_TX STM32_PINMUX_FUNC_ALT_7
|
||||
#define STM32L4X_PINMUX_FUNC_PB11_I2C2_SDA STM32_PINMUX_FUNC_ALT_4
|
||||
#define STM32L4X_PINMUX_FUNC_PB11_USART3_RX STM32_PINMUX_FUNC_ALT_7
|
||||
#define STM32L4X_PINMUX_FUNC_PB12_SPI2_NSS STM32_PINMUX_FUNC_ALT_5
|
||||
#define STM32L4X_PINMUX_FUNC_PB13_I2C2_SCL STM32_PINMUX_FUNC_ALT_4
|
||||
#define STM32L4X_PINMUX_FUNC_PB13_SPI2_SCK STM32_PINMUX_FUNC_ALT_5
|
||||
#define STM32L4X_PINMUX_FUNC_PB14_I2C2_SDA STM32_PINMUX_FUNC_ALT_4
|
||||
#define STM32L4X_PINMUX_FUNC_PB14_SPI2_MISO STM32_PINMUX_FUNC_ALT_5
|
||||
#define STM32L4X_PINMUX_FUNC_PB15_SPI2_MOSI STM32_PINMUX_FUNC_ALT_5
|
||||
#define STM32L4X_PINMUX_FUNC_PB3_SPI1_SCK STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PB3_SPI3_SCK STM32_PINMUX_ALT_FUNC_6 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PB4_SPI3_MISO STM32_PINMUX_ALT_FUNC_6 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PB5_SPI3_MOSI STM32_PINMUX_ALT_FUNC_6 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PB6_I2C1_SCL STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP
|
||||
#define STM32L4X_PINMUX_FUNC_PB6_USART1_TX STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PB7_I2C1_SDA STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP
|
||||
#define STM32L4X_PINMUX_FUNC_PB7_USART1_RX STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL
|
||||
#define STM32L4X_PINMUX_FUNC_PB8_I2C1_SCL STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP
|
||||
#define STM32L4X_PINMUX_FUNC_PB9_I2C1_SDA STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP
|
||||
#define STM32L4X_PINMUX_FUNC_PB10_I2C2_SCL STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP
|
||||
#define STM32L4X_PINMUX_FUNC_PB10_USART3_TX STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PB11_I2C2_SDA STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP
|
||||
#define STM32L4X_PINMUX_FUNC_PB11_USART3_RX STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL
|
||||
#define STM32L4X_PINMUX_FUNC_PB13_I2C2_SCL STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP
|
||||
#define STM32L4X_PINMUX_FUNC_PB14_I2C2_SDA STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP
|
||||
|
||||
/* Port C */
|
||||
#define STM32L4X_PINMUX_FUNC_PC0_I2C3_SCL STM32_PINMUX_FUNC_ALT_4
|
||||
#define STM32L4X_PINMUX_FUNC_PC1_I2C3_SDA STM32_PINMUX_FUNC_ALT_4
|
||||
#define STM32L4X_PINMUX_FUNC_PC4_USART3_TX STM32_PINMUX_FUNC_ALT_7
|
||||
#define STM32L4X_PINMUX_FUNC_PC5_USART3_RX STM32_PINMUX_FUNC_ALT_7
|
||||
#define STM32L4X_PINMUX_FUNC_PC10_SPI3_SCK STM32_PINMUX_FUNC_ALT_6
|
||||
#define STM32L4X_PINMUX_FUNC_PC10_USART3_TX STM32_PINMUX_FUNC_ALT_7
|
||||
#define STM32L4X_PINMUX_FUNC_PC11_SPI3_MISO STM32_PINMUX_FUNC_ALT_6
|
||||
#define STM32L4X_PINMUX_FUNC_PC11_USART3_RX STM32_PINMUX_FUNC_ALT_7
|
||||
#define STM32L4X_PINMUX_FUNC_PC12_SPI3_MOSI STM32_PINMUX_FUNC_ALT_6
|
||||
#define STM32L4X_PINMUX_FUNC_PC0_I2C3_SCL STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP
|
||||
#define STM32L4X_PINMUX_FUNC_PC1_I2C3_SDA STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP
|
||||
#define STM32L4X_PINMUX_FUNC_PC4_USART3_TX STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PC5_USART3_RX STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL
|
||||
#define STM32L4X_PINMUX_FUNC_PC10_USART3_TX STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PC11_USART3_RX STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL
|
||||
|
||||
/* Port D */
|
||||
#define STM32L4X_PINMUX_FUNC_PD5_USART2_TX STM32_PINMUX_FUNC_ALT_7
|
||||
#define STM32L4X_PINMUX_FUNC_PD6_USART2_RX STM32_PINMUX_FUNC_ALT_7
|
||||
#define STM32L4X_PINMUX_FUNC_PD8_USART3_TX STM32_PINMUX_FUNC_ALT_7
|
||||
#define STM32L4X_PINMUX_FUNC_PD9_USART3_RX STM32_PINMUX_FUNC_ALT_7
|
||||
#define STM32L4X_PINMUX_FUNC_PD5_USART2_TX STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PD6_USART2_RX STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL
|
||||
#define STM32L4X_PINMUX_FUNC_PD8_USART3_TX STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PD9_USART3_RX STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL
|
||||
|
||||
/* Port F */
|
||||
#define STM32L4X_PINMUX_FUNC_PF1_I2C3_SCL STM32_PINMUX_FUNC_ALT_4
|
||||
#define STM32L4X_PINMUX_FUNC_PF0_I2C3_SDA STM32_PINMUX_FUNC_ALT_4
|
||||
#define STM32L4X_PINMUX_FUNC_PF1_I2C3_SCL STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP
|
||||
#define STM32L4X_PINMUX_FUNC_PF0_I2C3_SDA STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP
|
||||
|
||||
/* Port G */
|
||||
#define STM32L4X_PINMUX_FUNC_PG7_I2C3_SCL STM32_PINMUX_FUNC_ALT_4
|
||||
#define STM32L4X_PINMUX_FUNC_PG8_I2C3_SDA STM32_PINMUX_FUNC_ALT_4
|
||||
#define STM32L4X_PINMUX_FUNC_PG9_USART1_TX STM32_PINMUX_FUNC_ALT_7
|
||||
#define STM32L4X_PINMUX_FUNC_PG10_USART1_RX STM32_PINMUX_FUNC_ALT_7
|
||||
#define STM32L4X_PINMUX_FUNC_PG14_I2C1_SCL STM32_PINMUX_FUNC_ALT_4
|
||||
#define STM32L4X_PINMUX_FUNC_PG13_I2C1_SDA STM32_PINMUX_FUNC_ALT_4
|
||||
#define STM32L4X_PINMUX_FUNC_PG7_I2C3_SCL STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP
|
||||
#define STM32L4X_PINMUX_FUNC_PG8_I2C3_SDA STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP
|
||||
#define STM32L4X_PINMUX_FUNC_PG9_USART1_TX STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL
|
||||
#define STM32L4X_PINMUX_FUNC_PG10_USART1_RX STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL
|
||||
#define STM32L4X_PINMUX_FUNC_PG14_I2C1_SCL STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP
|
||||
#define STM32L4X_PINMUX_FUNC_PG13_I2C1_SDA STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP
|
||||
|
||||
#endif /* _STM32L4X_PINMUX_H_ */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue