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drivers: pinctrl: nrf: initial support

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Add initial support for nRF pin controller driver. The implementation in
this patch does not yet support any peripheral. Only states
representation and basic driver functionality is introduced.

Note:
The nrf_pin_configure function has been marked as __unused since it may
not be used in certain scenarios until all peripherals are supported by
the pinctrl driver. For example, if only UART/E is supported but the
board does not enable UART, the function will never get called. However,
that board will likely have other peripherals that will gain support in
the future.

Thanks to Marti Bolivar for bindings documentation.

Co-authored-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit is contained in:
Gerard Marull-Paretas 2021-08-10 11:22:31 +02:00 • committed by Carles Cufí
commit 22c8c02145
9 changed files with 414 additions and 0 deletions
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121
include/dt-bindings/pinctrl/nrf-pinctrl.h Normal file
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/*
* Copyright (c) 2021 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_
/*
* The whole nRF pin configuration information is encoded in a 32-bit bitfield
* organized as follows:
*
* - 31..16: Pin function.
* - 15..13: Reserved.
* - 12: Pin low power mode.
* - 11..8: Pin output drive configuration.
* - 7..6: Pin pull configuration.
* - 5..0: Pin number (combination of port and pin).
*/
/**
* @name nRF pin configuration bit field positions and masks.
* @{
*/
/** Position of the function field. */
#define NRF_FUN_POS 16U
/** Mask for the function field. */
#define NRF_FUN_MSK 0xFFFFU
/** Position of the low power field. */
#define NRF_LP_POS 12U
/** Mask for the low power field. */
#define NRF_LP_MSK 0x1U
/** Position of the drive configuration field. */
#define NRF_DRIVE_POS 8U
/** Mask for the drive configuration field. */
#define NRF_DRIVE_MSK 0xFU
/** Position of the pull configuration field. */
#define NRF_PULL_POS 6U
/** Mask for the pull configuration field. */
#define NRF_PULL_MSK 0x3U
/** Position of the pin field. */
#define NRF_PIN_POS 0U
/** Mask for the pin field. */
#define NRF_PIN_MSK 0x3FU
/** @} */
/**
* @name nRF pinctrl pin functions.
* @{
*/
/** @} */
/**
* @name nRF pinctrl output drive.
* @note Values match nrf_gpio_pin_drive_t constants.
* @{
*/
/** Standard '0', standard '1'. */
#define NRF_DRIVE_S0S1 0U
/** High drive '0', standard '1'. */
#define NRF_DRIVE_H0S1 1U
/** Standard '0', high drive '1'. */
#define NRF_DRIVE_S0H1 2U
/** High drive '0', high drive '1'. */
#define NRF_DRIVE_H0H1 3U
/** Disconnect '0' standard '1'. */
#define NRF_DRIVE_D0S1 4U
/** Disconnect '0', high drive '1'. */
#define NRF_DRIVE_D0H1 5U
/** Standard '0', disconnect '1'. */
#define NRF_DRIVE_S0D1 6U
/** High drive '0', disconnect '1'. */
#define NRF_DRIVE_H0D1 7U
/** Extra high drive '0', extra high drive '1'. */
#define NRF_DRIVE_E0E1 11U
/** @} */
/**
* @name nRF pinctrl pull-up/down.
* @note Values match nrf_gpio_pin_pull_t constants.
* @{
*/
/** Pull-up disabled. */
#define NRF_PULL_NONE 0U
/** Pull-down enabled. */
#define NRF_PULL_DOWN 1U
/** Pull-up enabled. */
#define NRF_PULL_UP 3U
/** @} */
/**
* @name nRF pinctrl low power mode.
* @{
*/
/** Input. */
#define NRF_LP_DISABLE 0U
/** Output. */
#define NRF_LP_ENABLE 1U
/** @} */
/**
* @brief Utility macro to build nRF psels property entry.
*
* @param fun Pin function configuration (see NRF_FUNC_{name} macros).
* @param port Port (0 or 1).
* @param pin Pin (0..31).
*/
#define NRF_PSEL(fun, port, pin) \
((((((port) * 32U) + (pin)) & NRF_PIN_MSK) << NRF_PIN_POS) | \
((NRF_FUN_ ## fun & NRF_FUN_MSK) << NRF_FUN_POS))
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_ */