boards: riscv: add basic neorv32 board definition
Add a basic board definition for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
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13 changed files with 405 additions and 0 deletions
31
boards/riscv/neorv32/CMakeLists.txt
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31
boards/riscv/neorv32/CMakeLists.txt
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# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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if((CONFIG_BOARD_NEORV32) AND (CONFIG_BUILD_OUTPUT_BIN))
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# Generate NEORV32 image formats for initialising IMEM.
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find_program(IMAGE_GEN image_gen)
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if(NOT ${IMAGE_GEN} STREQUAL IMAGE_GEN-NOTFOUND)
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set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
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COMMAND ${IMAGE_GEN}
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ARGS -app_bin
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${CONFIG_KERNEL_BIN_NAME}.bin
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${CONFIG_KERNEL_BIN_NAME}_exe.bin
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${PROJECT_BINARY_DIR}
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WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
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)
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message(STATUS "neorv32 binary will be written to: ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}_exe.bin")
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set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
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COMMAND ${IMAGE_GEN}
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ARGS -app_img
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${CONFIG_KERNEL_BIN_NAME}.bin
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${CONFIG_KERNEL_BIN_NAME}.vhd
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${PROJECT_BINARY_DIR}
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WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
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)
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message(STATUS "neorv32 VHDL will be written to: ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.vhd")
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else()
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message(STATUS "The neorv32 image_gen utility was not found, neorv32 image files cannot be generated")
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endif()
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endif()
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6
boards/riscv/neorv32/Kconfig.board
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6
boards/riscv/neorv32/Kconfig.board
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# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_NEORV32
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bool "NEORV32 Processor (SoC)"
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depends on SOC_SERIES_NEORV32
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9
boards/riscv/neorv32/Kconfig.defconfig
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9
boards/riscv/neorv32/Kconfig.defconfig
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# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_NEORV32
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config BOARD
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default "neorv32"
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endif # BOARD_NEORV32
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5
boards/riscv/neorv32/board.cmake
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5
boards/riscv/neorv32/board.cmake
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# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(openocd "--use-elf" "--cmd-reset-halt" "halt")
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
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184
boards/riscv/neorv32/doc/index.rst
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184
boards/riscv/neorv32/doc/index.rst
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.. _neorv32:
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NEORV32
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#######
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Overview
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********
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The NEORV32 is an open-source RISC-V compatible processor system intended as a
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ready-to-go auxiliary processor within larger SoC designs or as a stand-alone
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customizable microcontroller.
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.. figure:: ./neorv32_logo_transparent.png
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:width: 813px
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:align: center
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:alt: NEORV32
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NEORV32 (Credit: Stephan Nolting)
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For more information about the NEORV32, see the following websites:
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- `The NEORV32 RISC-V Processor GitHub`_
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- `The NEORV32 RISC-V Processor Datasheet`_
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- `The NEORV32 RISC-V Processor User Guide`_
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Supported Features
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==================
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The ``neorv32`` board configuration can be used a generic definition for NEORV32
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based boards. Customisation to fit custom NEORV32 implementations can be done
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using :ref:`devicetree overlays <use-dt-overlays>`.
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Zephyr currently supports the following hardware features of the NEORV32
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Processor (SoC):
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| INTC | on-chip | interrupt controller |
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+-----------+------------+-------------------------------------+
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| MTIME | on-chip | system timer |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio, non-interrupt |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial port-polling; |
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| | | serial port-interrupt |
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+-----------+------------+-------------------------------------+
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The default board configuration for the NEORV32 Processor (SoC) can be found in
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the defconfig file: :file:`boards/riscv/neorv32/neorv32_defconfig`.
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System Clock
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============
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The default board configuration assumes a system clock of 100 MHz. The clock
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frequency can be overridden by changing the ``clock-frequency`` property of the
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``cpu0`` devicetree node.
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CPU
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===
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The default board configuration assumes the NEORV32 CPU implementation has the
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following RISC-V ISA extensions enabled:
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- C (Compresses Instructions)
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- M (Integer Multiplication and Division)
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- Zicsr (Control and Status Register (CSR) Instructions)
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Internal Instruction Memory
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===========================
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The default board configuration assumes the NEORV32 SoC implementation has a 64k
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byte internal instruction memory (IMEM) for code execution. The size of the
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instruction memory can be overridden by changing the ``reg`` property of the
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``imem`` devicetree node.
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Internal Data Memory
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====================
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The default board configuration assumes the NEORV32 SoC implementation has a 32k
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byte internal data memory (DMEM). The size of the data memory can be overridden
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by changing the ``reg`` property of the ``dmem`` devicetree node.
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Serial Port
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===========
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The default configuration assumes the NEORV32 SoC implements UART0 for use as
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system console.
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.. note::
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The default configuration uses a baud rate of 19200 to match that of the
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standard NEORV32 bootloader. The baudrate can be changed by modifying the
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``current-speed`` property of the ``uart0`` devicetree node.
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Programming and Debugging
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*************************
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First, configure the FPGA with the NEORV32 bitstream as described in the NEORV32
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user guide.
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Next, build and flash applications as usual (see :ref:`build_an_application` and
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:ref:`application_run` for more details).
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Configuring a Console
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=====================
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Use the following settings with your serial terminal of choice (minicom, putty,
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etc.):
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- Speed: 19200
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- Data: 8 bits
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- Parity: None
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- Stop bits: 1
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Flashing via JTAG
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=================
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Here is an example for building and flashing the :ref:`hello_world` application
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for the NEORV32 via JTAG. Flashing via JTAG requires a NEORV32 SoC
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implementation with the On-Chip Debugger (OCD) and bootloader enabled.
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.. note::
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If the bootloader is not enabled, the internal instruction memory (IMEM) is
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configured as ROM which cannot be modified via JTAG.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: neorv32
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:goals: flash
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After flashing, you should see message similar to the following in the terminal:
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.. code-block:: console
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*** Booting Zephyr OS build zephyr-vn.n.nn ***
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Hello World! neorv32
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Note, however, that the application was not persisted in flash memory by the
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above steps. It was merely written to internal block RAM in the FPGA. It will
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revert to the application stored in the block RAM within the FPGA bitstream
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the next time the FPGA is configured.
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The steps to persist the application within the FPGA bitstream are covered by
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the NEORV32 user guide. If the :kconfig:`CONFIG_BUILD_OUTPUT_BIN` is enabled and
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the NEORV32 ``image_gen`` binary is available, the build system will
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automatically generate a :file:`zephyr.vhd` file suitable for initialising the
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internal instruction memory of the NEORV32.
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Uploading via UART
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==================
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If the :kconfig:`CONFIG_BUILD_OUTPUT_BIN` is enabled and the NEORV32
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``image_gen`` binary is available, the build system will automatically generate
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a :file:`zephyr_exe.bin` file suitable for uploading to the NEORV32 via the
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built-in bootloader as described in the NEORV32 user guide.
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Debugging via JTAG
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==================
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Here is an example for the :ref:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: neorv32
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:goals: debug
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Step through the application in your debugger, and you should see a message
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similar to the following in the terminal:
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.. code-block:: console
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*** Booting Zephyr OS build zephyr-vn.n.nn ***
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Hello World! neorv32
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.. _The NEORV32 RISC-V Processor GitHub:
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https://github.com/stnolting/neorv32
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.. _The NEORV32 RISC-V Processor Datasheet:
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https://stnolting.github.io/neorv32/
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.. _The NEORV32 RISC-V Processor User Guide:
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https://stnolting.github.io/neorv32/ug/
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BIN
boards/riscv/neorv32/doc/neorv32_logo_transparent.png
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BIN
boards/riscv/neorv32/doc/neorv32_logo_transparent.png
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Binary file not shown.
After Width: | Height: | Size: 6.5 KiB |
85
boards/riscv/neorv32/neorv32.dts
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85
boards/riscv/neorv32/neorv32.dts
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/*
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* Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <neorv32.dtsi>
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#include <freq.h>
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#include <mem.h>
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/ {
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aliases {
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led0 = &led0;
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led1 = &led1;
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led2 = &led2;
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led3 = &led3;
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};
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chosen {
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zephyr,flash = &imem;
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zephyr,sram = &dmem;
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,uart-pipe = &uart0;
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};
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soc {
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imem: memory@0 {
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compatible = "soc-nv-flash", "mmio-sram";
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reg = <0x0 DT_SIZE_K(64)>;
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};
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bootrom: memory@ffff0000 {
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compatible = "soc-nv-flash", "mmio-sram";
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reg = <0xffff0000 DT_SIZE_K(4)>;
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};
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dmem: memory@80000000 {
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compatible = "mmio-sram";
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reg = <0x80000000 DT_SIZE_K(32)>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led0: led0 {
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gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
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label = "LED_0";
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};
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led1: led1 {
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gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
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label = "LED_1";
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};
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led2: led2 {
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gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
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label = "LED_2";
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};
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led3: led3 {
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gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
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label = "LED_3";
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};
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};
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};
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&cpu0 {
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clock-frequency = <DT_FREQ_M(100)>;
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};
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&uart0 {
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status = "okay";
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current-speed = <19200>;
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};
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&gpio_lo {
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status = "okay";
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};
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&gpio_hi {
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status = "okay";
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};
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11
boards/riscv/neorv32/neorv32.yaml
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11
boards/riscv/neorv32/neorv32.yaml
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identifier: neorv32
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name: NEORV32 Processor (SoC)
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type: mcu
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arch: riscv32
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toolchain:
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- cross-compile
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- zephyr
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ram: 32
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flash: 64
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supported:
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- gpio
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4
boards/riscv/neorv32/neorv32_1_6_1.conf
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4
boards/riscv/neorv32/neorv32_1_6_1.conf
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# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SOC_NEORV32_V1_6_1=y
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12
boards/riscv/neorv32/neorv32_defconfig
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12
boards/riscv/neorv32/neorv32_defconfig
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# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SOC_SERIES_NEORV32=y
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CONFIG_SOC_NEORV32_ISA_C=y
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CONFIG_BOARD_NEORV32=y
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CONFIG_RISCV_MACHINE_TIMER=y
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CONFIG_SERIAL=y
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_GPIO=y
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7
boards/riscv/neorv32/revision.cmake
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7
boards/riscv/neorv32/revision.cmake
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# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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board_check_revision(
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FORMAT MAJOR.MINOR.PATCH
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DEFAULT_REVISION 1.6.1
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)
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34
boards/riscv/neorv32/support/neorv32.cfg
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34
boards/riscv/neorv32/support/neorv32.cfg
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# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME neorv32
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}
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 256
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}
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if { [info exists WORKAREAADDR] } {
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set _WORKAREAADDR $WORKAREAADDR
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} else {
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set _WORKAREAADDR 0x80000000
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x0cafe001
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}
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transport select jtag
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jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
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$_TARGETNAME.0 configure -work-area-phys $_WORKAREAADDR -work-area-size $_WORKAREASIZE -work-area-backup 1
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17
boards/riscv/neorv32/support/openocd.cfg
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17
boards/riscv/neorv32/support/openocd.cfg
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# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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adapter driver ftdi
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ftdi_vid_pid 0x0403 0x6010
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ftdi_channel 0
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if { [info exists _ZEPHYR_BOARD_SERIAL] } {
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ftdi_serial $_ZEPHYR_BOARD_SERIAL
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}
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ftdi_layout_init 0x0038 0x003b
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adapter speed 1000
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ftdi_layout_signal nTRST -ndata 0x0010 -noe 0x0040
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source [find neorv32.cfg]
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